The evening begins at the Keysight office, Thursday, April 28, at 5:00pm with the ESD Alliance Annual Membership Meeting. You'll get an overview of the past year's activities and discover what's in store for 2022. The meeting flows directly into a Welcome Reception followed by the powerful CEO Outlook.
Enjoy a lively, nourishing networking reception that kicks off the CEO Outlook panel. Hear influential executives from Arm | Cadence | D2S | Keysight | Siemens share their insights on the current and future state of the design and semiconductor industries. Ed Sperling, Editor-in-Chief of Semiconductor Engineering, moderates a spirited, robust discussion, including an audience Q&A.
Registration | FREE for ESD Alliance and SEMI members | Non-member: $49 per person.
Keysight 5301 Stevens Creek Blvd. Building 5 Santa Clara, CA95051 United States
5:00 pm
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5:30 pm
Bob Smith
Executive Director
ESD Alliance
ESD Alliance Annual Membership Meeting
Overview of ESD Alliance activities for 2021 and plans for 2022.
5:30 pm
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6:30 pm
Networking
Enjoy light food and refreshments as you network with your peers.
6:30 pm
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7:30 pm
Ed Sperling | Moderator
Editor in Chief
Semiconductor Engineering
Moderator & Panelists
Hear panelists from ARM | CADENCE | D2S | Keysight | Siemens EDA discuss the state of the electronic system design industry as well as their views of the outlook for the coming years.
ESD Alliance and co-sponsor Keysight welcome you to join us in-person for the Annual ESDA Membership Meeting & CEO Outlook at the Keysight office in Santa Clara, CA.
ESDA CEO Outlook & Membership Meeting
April 28, 2022
5:00 PM - 7:30 PM
5:00 pm - 7:30 pm
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Add to Calendar2022-04-28 17:00:002022-04-28 19:30:00ESDA CEO Outlook & Membership MeetingESD Alliance and co-sponsor Keysight welcome you to join us in-person for the Annual ESDA Membership Meeting & CEO Outlook at the Keysight office in Santa Clara, CA.Keysight 5301 Stevens Creek Blvd. Building 5 Santa Clara, CA 95051 United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
SEMI MSIG PNT Gap Analysis Workshop
Registration Details
Registration is free of charge, but must be done in advance
Massachusetts Institute of Technology—MIT 50 Memorial Dr, Samberg Conference Center, Chang Building (E52) Cambridge, MA02142 United States
1:00 pm
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3:00 pm
Phase 2 Project Introductions
- Low-SWaP-C, GPS-free PNT technology
- Novel materials, fabrication & packaging techniques and approaches
- Advancements in atomic clock and quantum sensor photonics
3:00 pm
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4:30 pm
Break Out Sessions
Thrust Area 1: Novel Materials, Fabrication, and Packaging Techniques for Low-SWaP Inertial and PNT Sensors
Thrust Area 2: Advanced Active and Passive Integrated Photonics for Low-SWaP Atomic Clocks, Quantum Systems, & PNT Sensors
Thrust Area 3: Advancements Towards Low-SWaP, GPS-Free PNT Technologies
SEMI MSIG has another $5M in R&D funding for sensor positioning, navigation, and timing (PNT) technology development! Register now to attend our half-day Gap Analysis workshop, taking place May 22nd, the afternoon before our premier sensor technology-event, the MEMS & Sensors Technical Congress (MSTC). Meet US Gov’t subject matter experts (SME’s) to discuss PNT pain points and get insights into this year’s request for proposals (RFP) expected in June 2023.
The workshop will feature presentations from the new 2023 PNT projects and identify areas for this year’s RFP.
Have your voice heard, as SEMI MSIG and the Army Research Lab work to fund PNT R&D technology improvements in a 5-year (2022-2027) $25M program. This gap analysis workshop is a critical component of the program’s 2nd year activities.
SEMI MSIG PNT Gap Analysis Workshop
Learn About Phase 2 of the Positioning, Navigation and Timing (PNT) Funding Program
1:00 pm - 5:00 pm
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Hotel
Cambridge hotels are expensive in late May, so we have made a deal for you, click here!
We have a room block reserved at DoubleTree Suites by Hilton Hotel Boston, Cambridge for May 21, 2023 through May 25, 2023. Booking your room is simple, just select "Book a Room" to receive your group's preferred rate. Must book rooms before May 12th to obtain discounted rate.
Please book your hotel reservations online for MSTC 2023 Conference or guests can call our 24-7 reservations desk to book your room or please ask for the Front Desk and then provide the Group Code: MSTC
Sponsorships are tailored to meet your branding and marketing objectives. To learn about please contact: Shane Poblete | 1.202.847.5983 | [email protected]
Perched on a mountain slope with panoramic views of the surrounding valley and Phoenix skyline, Raven Golf Club's upscale amenities rival those of America's finest private country clubs. The club boasts a beautiful clubhouse featuring a full-service golf shop with its Gary Panks/David Graham-designed championship layout as the centerpiece.
SEMI ARIZONA CHAPTER STEM SCHOLARSHIP—PURCHASE A MULLIGAN + RAFFLE TICKETS
PURCHASE MULLIGAN(s) and Raffle Tickets—SUPPORT THE SEMI ARIZONA CHAPTER STEM SCHOLARSHIP
The scholarship is awarded to a deserving University in the Arizona Region. Raffle tickets and mulligans are $5 each, available for purchase electronically in advance or onsite. Proceeds from the sales directly fund the scholarship. Players and non-players are welcome to support the scholarship.
To donate a raffle prize separately, please contact—Karen Popp | [email protected]
PLAYER AWARDS
Closest to Pin
Longest Drive
Putting Contest
Best Foursome
Needs Most Improvement
DRESS CODE
Proper golf attire must be worn at all times. All players are required to wear collared shirts. Slacks, shorts, or skirts must be hemmed and in good condition. Recommended short/skirt length is mid-thigh. Tank tops, swimwear, cutoffs, gym shorts, and the like are not acceptable.
Raven Golf Course is a spikeless facility. Metal Spikes are not allowed on the golf course.
HOTELS
If you are traveling from out of town, the following hotels are a short drive from the Raven Golf Course:
Raven Golf Course 3636 E Baseline Road Phoenix, AZ85042 United States
Thursday, May 7, 2026 | Mountain Time
6:30 am
Registration | Grab & Go Breakfast
Breakfast Sponsored by Sundt
7:30 am
Shotgun Start
1:00 pm
Networking Lunch | Awards Presentation
Sold Out—Thank You for Your Interest!
5th Annual SEMI Arizona Golf Classic
Join us for a morning of golf, fun, and networking at the beautiful Raven Golf Course in Phoenix, Arizona. Whether you're a beginner or a pro—enjoy friendly competition and camaraderie with your colleagues and customers.
SEMI Arizona Golf Classic
May 7, 2026
Raven Golf Course, Phoenix, AZ
6:30 am - 3:00 pm
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The CHIPS Act and FABS Act propose significant new incentives for semiconductor manufacturing in the United States. Both have advanced in Congress, but the legislative process remains unfinished while other countries are pursuing and implementing additional incentives. These incentives are essential to put the U.S. on a strong footing to compete for the next wave of new semiconductor manufacturing capacity, strengthen the supply chain in the U.S. and address shortages that have impacted countless downstream industries. It is also clear that the microelectronics industry doesn't only have a supply chain problem, but a significant workforce shortfall. Diversifying and growing the talent pipeline will be critical to meet the growing demands of the industry.
Join leaders in Congress and industry experts to discuss:
CHIPS Act funding – where it stands and what it means for industry
The FABS Act and federal tax incentives for U.S. semiconductor manufacturing
Supply Chain Challenges & Opportunities
Critical need and initiatives for diversifying and building a robust workforce
Join your fellow members for the FOA Annual Collaborative Forum - live and in-person - for informative new case studies, networking, dinners, and exhibits.
8:00 am - 10:00 pm
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Add to Calendar2026-02-24 08:00:002026-02-26 22:00:00FOA Summit (Q1 Collaborative Forum)Join your fellow members for the FOA Annual Collaborative Forum - live and in-person - for informative new case studies, networking, dinners, and exhibits. This event is for FOA Members only. To learn more about becoming an FOA member, email [email protected]. Visit the FOA web pages.Austin Marriott South 4415 South IH-35 Austin, TX 78744 United StatesSEMI.org[email protected]America/Chicagopublic
America/Chicago
About the Speaker: Rich Boardman is a 15-year veteran of the Semiconductor industry whose expertise lies in equipment sets, process technology and consumables related to wafer or substrate dicing, grinding or polishing. Rich is a Senior Sales Engineer at GDSI, located in San Jose, California.
United States
Richard Boardman
Senior Sales Engineer
GDSI
Join us for this second webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication.
In this session, GDSI will provide an introduction of the Stealth Dicing process, highlight the applications it is most well suited to, and share design rules and process window specifications.
The Stealth laser dicing process is a water-free, particle-free wafer singulation method. It is particularly well suited to MEMS, Quantum, bio-sensing and Silicon Photonics to name a few use cases. Secondarily, it offers great value for multi-project wafer (MPW) applications since it allows singulation of the whole wafer in a single process step, negating the need for wafer sub-dicing and remounting.
Find out if your current wafer layout is compatible with the Stealth Dicing process, and if not, what must be done to ensure initial success with this innovative dicing technology. .
MSIG Webinar: The New GDSI Dicing Process
March 30, 2002 8-9 AM PT
8:00 am - 9:00 am
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Add to Calendar2022-03-30 08:00:002022-03-30 09:00:00MSIG Webinar GDSI Dicing ProcessJoin us for this second webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication.
In this session, GDSI will provide an introduction of the Stealth Dicing process, highlight the applications it is most well suited to, and share design rules and process window specifications.
The Stealth laser dicing process is a water-free, particle-free wafer singulation method. It is particularly well suited to MEMS, Quantum, bio-sensing and Silicon Photonics to name a few use cases. Secondarily, it offers great value for multi-project wafer (MPW) applications since it allows singulation of the whole wafer in a single process step, negating the need for wafer sub-dicing and remounting.
Find out if your current wafer layout is compatible with the Stealth Dicing process, and if not, what must be done to ensure initial success with this innovative dicing technology. .United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
Workforce Shortage—Meeting Challenges for the Semiconductor Industry
As demand for semiconductors is increasing, foundries and other makers of chips are expanding their manufacturing capacities. With new fabs that will bring thousands of new jobs to the US, Arizona and Texas are poised to gain many of those positions. Where will we find the talent to fill the upcoming surge of engineering and technical personnel needed to support our existing infrastructure, but also support the new fabs coming in just two-four years?
The SEMI Arizona and Texas Chapters will explore this topic by hearing from Arizona and Texas-based leadership on the current market conditions, trends and outlook. We will also hear from the semiconductor industry, experts from industry, universities/colleges and military who will provide insight into preparing a new workforce to meet our current workforce needs and needs of our not-to-distant future.
About the Speaker: Robert MacDonald is a MEMS engineer at GE’s Research. His research is focused on high performance inertial sensors. He has over 20 years of experience in the MEMS and semiconductor industries. His work has covered the product life cycle of chemical, inertial and optical sensors from design through market introduction and manufacturing.
Join us for this first webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication.
In this first in the series, GE Research will present their new MEMS process suitable for bulk silicon motion sensors. The process aims to deliver many features of complex MEMS flows, such as wafer level packaging with through silicon vias (TSVs), with a short cycle times and low mask counts. This webinar will introduce the Polaris process within the GE Research foundry and explain how to design the process, and our model for delivering new designs.
Designing MEMS with GE’s Polaris Process for Motion Sensor Fabrication
8:00 am - 9:00 am
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Add to Calendar2022-03-02 08:00:002022-03-02 09:00:00MSIG Webinar GE Polaris ProcessJoin us for this first webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication.
In this first in the series, GE Research will present their new MEMS process suitable for bulk silicon motion sensors. The process aims to deliver many features of complex MEMS flows, such as wafer level packaging with through silicon vias (TSVs), with a short cycle times and low mask counts. This webinar will introduce the Polaris process within the GE Research foundry and explain how to design the process, and our model for delivering new designs.United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
Moore’s Law continues to evolve - dramatically changing the Field Effect Transistor (FET). As FinFETs reach their performance limits, attention is turning to Gate All Around (GAA) architectures based on Horizontal Nanosheet technology. Such a fundamental shift in transistor architecture will create new challenges to processes and materials, presenting opportunities for companies well-positioned for this shift.
In this webinar, SEMI EMG brings experts to explain the technology trends driving the industry adoption of Gate All Around, how the major players are approaching this transition, and the implications this will have on the material supply chain
Gate All Around Transistors - Opportunities Abound
Position yourself for the next chapter of Moore's Law
10:00 am - 11:00 am
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SEMI is pleased to once again partner with the HIR Symposium for this 5th Annual Symposium. See the full Agenda.
Don't miss the plenary talk by SEMI President and CEO, Ajit Manocha at 7:40 am PST!
7:30 am - 12:30 pm
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Add to Calendar2022-02-23 07:30:002022-02-24 12:30:00Fifth Annual Symposium on Heterogeneous IntegrationSEMI is pleased to once again partner with the HIR Symposium for this 5th Annual Symposium. See the full Agenda.
Don't miss the plenary talk by SEMI President and CEO, Ajit Manocha at 7:40 am PST!Virtual, Online United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
