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Registrants will receive the presentation recording and PDFs of Webinar #2
Taylor Zhao
Manager, Programs & Committees
[email protected]
SiC—Silicon Carbide Webinar #2:
Non-CMOS Compatible SiC Power Device Fabrication in Volume Si Fabs
SiC devices are displacing their incumbent Si counterparts in several high-volume power applications. As SiC market share continues to grow, the industry is lifting the last barriers to mass commercialization that include higher than Si device cost, relative lack of wafer planarity, the presence of defects like basal plane dislocations, reliability and ruggedness concerns, and the need for a workforce skilled in SiC power technology to keep up with the rising demand. To enable cost-effective manufacturing, high-yielding SiC fabrication in conventional Si fabs is desirable.
In this webinar, I will summarize key aspects of SiC fabrication technology and outline non-CMOS compatible processes that have been streamlined to allow for mass SiC chip fabrication in conventional Si mature fabs. The SiC industry has successfully leveraged the Si fab infrastructure and has made the relatively small financial investments required to allow existing Si fabs to process SiC. Consequently, SiC chip fabrication in volume fabs alongside Si has emerged as a “cost reduction” model that exploits “silicon” manufacturing economies of scale. Today’s SiC fab infrastructure is vibrant, mirrors that of silicon, and is rapidly expanding.
View Previous Webinar in the SiC Series
- Webinar #1—Silicon Carbide Material Properties, Key Applications, and Fabrication Basics: Making the Transition from Silicon
- Webinar #2—Non-CMOS Compatible SiC Power Device Fabrication in Volume Si Fabs
- Webinar #3—Bidirectional SiC and GaN Switch Technology
- Webinar #4—Understanding SiC Chip Cost, the Impact of Defects, and the Case of Price Parity with Si at the System Level
- Webinar #5—SiC Edge Termination Technology
Meet the Speaker
Biography
United States
Now Available On-Demand!
Join us online as we dive into SiC fabrication technology and non-CMOS compatible processes that have been streamlined to allow for mass SiC chip fabrication in conventional Si mature fabs.
