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Course Description 

This course provides a comprehensive introduction to semiconductor manufacturing, guiding participants through the complete journey from silicon fundamentals to chip fabrication and packaging. Designed for professionals new to the semiconductor industry, the course explains key concepts, terminology, devices, and manufacturing processes used in modern fabs. 

This course is divided into four modules, enabling a progressive learning experience that builds from fundamentals to manufacturing execution. Participants will gain a clear understanding of how chips are made, the role of transistors, and the steps involved in front-end manufacturing, followed by back-end assembly and packaging processes. The course also introduces the broader semiconductor ecosystem, including supply chain players, helping learners connect technical fundamentals with real-world manufacturing practices. 

Who Should Attend

This course is designed for sales and marketing professionals, as well as new employees, students, and anyone interested in gaining a knowledge about semiconductor manufacturing.   

Learning Objectives

Upon completion of the course, participants should be able to:

  • Explain fundamental semiconductor concepts, including silicon materials, doping, PN junctions, and basic device behavior. 
  • Identify and correctly use common semiconductor manufacturing terminology.
  • Outline the key steps involved in front-end wafer fabrication, from bare silicon to patterned wafers.
  • Summarize back-end manufacturing processes, including assembly, packaging, and testing.

Topics Included

  • Module 1: Semiconductor Fundamentals

    Introduces semiconductor basics, silicon materials, doping PN junctions, and core device concepts, building a foundation for understanding how electronic devices function.

  • Module 2: Semiconductor Terminologies and Manufacturing Context

    Covers essential semiconductor terminology, cleanroom concepts, supply chain players, process nodes, and packaging to help learners navigate manufacturing discussions with confidence.

  • Module 3: Front-end and Back-end Semiconductor Manufacturing

    Provides an overview of the key steps involved in front-end wafer fabrication and back-end assembly, packaging, and testing processes.

  • Module 4: Transistors and Their Operation

    Explains different types of transistors and their working principles, showing how transistors function as switches and amplifiers inside integrated circuits. 

Important Information

Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access the course knowledge. 

Can't find the training link on the day of the training? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders 24 hours in advance and 1 hour before, with the same link. Please keep these emails on hand to access the training on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.

 

Mayura Padmanabhan
Program Manager
SEMI

 

Singapore

SEMI U

Strengthen your knowledge and skills by learning about the journey from silicon fundamentals to chip fabrication and packaging. 

  • Singapore: 8:00 am - 12:00 pm 
  • San Francisco: 5:00 pm - 9:00 pm
Pricing                     
  • Members:  $199
  • Non-Members:  $249


Any questions, please contact [email protected]

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Registration

For questions, please contact [email protected]

United States Japan Taiwan South Korea Malaysia Singapore Vietnam Business Training Featured Speakers

Leverage SEMI U learning opportunities to accelerate your professional development in 2027. Our commitment remains focused on delivering comprehensive technical education that helps you build the knowledge and skills needed to thrive in the semiconductor industry.

Join us for our upcoming, "Kickoff to SEMI U 2027," where you'll get an exclusive preview of new learning opportunities, upcoming training events, and special savings available to learners. 

During this webinar, you will:

  • Discover the latest updates and enhancements to SEMI U's on-demand course catalog.  
  • Explore upcoming virtual and in-person instructor-led training programs scheduled for the first half of 2027. 
  • Learn how to maximize your professional development with SEMI U resources and learning pathways. 
  • Receive access to a special 10% discount on all on-demand courses

Don't miss this opportunity to plan your learning journey and stay ahead in a rapidly evolving industry. Register today to reserve your spot.

United States

Headshot of Naresh Naik
Naresh Naik
Director, SEMI University
SEMI
SEMI U Workforce Development

Join us to explore SEMI U's current course offerings and upcoming virtual and in-person training opportunities designed to support your professional growth in the semiconductor industry. You'll also have the chance to engage directly with our team during a live Q&A session. As a thank you for attending this free webinar, you'll receive:

  • A 10% discount code valid on all SEMI U on-demand courses. 
  • Entry into a raffle to win a complimentary course bundle valued at $100
6:00 pm - 6:30 pm Off Add to Calendar 2027-01-27 18:00:00 2027-01-27 18:30:00 Kickoff to SEMI U - Free Webinar (PM Session) - ASIA Join us to explore SEMI U's current course offerings and upcoming virtual and in-person training opportunities designed to support your professional growth in the semiconductor industry. You'll also have the chance to engage directly with our team during a live Q&A session. As a thank you for attending this free webinar, you'll receive:A 10% discount code valid on all SEMI U on-demand courses. Entry into a raffle to win a complimentary course bundle valued at $100.  United States SEMI.org [email protected] America/Los_Angeles public
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SEMI Japan
26F, xLINK Marunouchi Eiraku Bldg.
1-4-1 Marunouchi
Chiyoda-ku, Tokyo
1010005
Japan

Standards

3D Packaging & Integration  Japan TC Chapter Meeting 

Date: Friday, September 25, 2026

Time: 2:00 PM - 4:00 PM JST

via OVTCCM/ SEMI Japan Office (Hybrid)

 

AGENDA

 

Standards Contact Information:

Akiko Yoshida

Manager, SEMI Japan

Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

Questions? Contact your local staff coordinator: Click here

2:00 pm - 4:00 pm Off Add to Calendar 2026-09-25 14:00:00 2026-09-25 16:00:00 3D Packaging & Integration Japan TC Chapter Meeting 3D Packaging & Integration  Japan TC Chapter Meeting Date: Friday, September 25, 2026Time: 2:00 PM - 4:00 PM JSTvia OVTCCM/ SEMI Japan Office (Hybrid) AGENDA Standards Contact Information:Akiko YoshidaManager, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click here SEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi Chiyoda-ku, Tokyo 1010005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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SEMI Japan
26F, xLINK Marunouchi Eiraku Bldg.
1-4-1 Marunouchi
Chiyoda-ku, Tokyo
1010005
Japan

Standards

EHS Japan TC Chapter Meeting 

 

Date: Wednesday, September 16, 2026

Time: 10:00 AM - 12:00 PM JST

Location: SEMI Japan/ Official Virtual TC Chapter Meeting (Hybrid)

 

AGENDA

 

Standards Contact Information:

Akiko Yoshida

Manager, Standards & EHS, SEMI Japan
Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

Questions? Contact your local staff coordinator: Click here

10:00 am - 12:00 pm Off Add to Calendar 2026-09-16 10:00:00 2026-09-16 12:00:00 EHS Japan TC Chapter Meeting EHS Japan TC Chapter Meeting  Date: Wednesday, September 16, 2026Time: 10:00 AM - 12:00 PM JSTLocation: SEMI Japan/ Official Virtual TC Chapter Meeting (Hybrid) AGENDA Standards Contact Information:Akiko YoshidaManager, Standards & EHS, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click here SEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi Chiyoda-ku, Tokyo 1010005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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SEMI Japan
1-4-1 Marunouchi,
Chiyoda-ku, Tokyo
1000005
Japan

Standards

Physical Interfaces & Carriers Japan TC Chapter Meeting 

Date: Friday, September 11, 2026

Time: 1:30 pm - 4:30 pm JST

Venue: SEMI Japan Office Board Room + OVTCCM (Hybrid)

 

AGENDA

 

Standards Contact Information:

Takeaki Hirabara

Standards & EHS, SEMI Japan

Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

Questions? Contact your local staff coordinator: Click here

1:30 pm - 4:30 pm Off Add to Calendar 2026-09-11 13:30:00 2026-09-11 16:30:00 Physical Interfaces & Carriers Japan TC Chapter Meeting Physical Interfaces & Carriers Japan TC Chapter Meeting Date: Friday, September 11, 2026Time: 1:30 pm - 4:30 pm JSTVenue: SEMI Japan Office Board Room + OVTCCM (Hybrid) AGENDA Standards Contact Information:Takeaki HirabaraStandards & EHS, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click here SEMI Japan 1-4-1 Marunouchi, Chiyoda-ku, Tokyo 1000005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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SEMI Japan
26F, xLINK Marunouchi Eiraku Bldg.
1-4-1 Marunouchi,
Chiyoda-ku, Tokyo
1000005
Japan

Standards

Information & Control Japan TC Chapter Meeting 

Date: Friday, September 11, 2026

Time: 10:00 am - 12:00 pm JST

Venue: SEMI Japan Office Room 1 + OVTCCM (Hybrid)

 

AGENDA

 

Standards Contact Information:

Takeaki Hirabara

Standards & EHS, SEMI Japan

Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

Questions? Contact your local staff coordinator: Click here

10:00 am - 12:00 pm Off Add to Calendar 2026-09-11 10:00:00 2026-09-11 12:00:00 Information & Control Japan TC Chapter Meeting Information & Control Japan TC Chapter Meeting Date: Friday, September 11, 2026Time: 10:00 am - 12:00 pm JSTVenue: SEMI Japan Office Room 1 + OVTCCM (Hybrid) AGENDA Standards Contact Information:Takeaki HirabaraStandards & EHS, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click here SEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi, Chiyoda-ku, Tokyo 1000005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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SEMI Japan
26F, xLINK Marunouchi Eiraku Bldg.
1-4-1 Marunouchi
Chiyoda-ku, Tokyo
1000005
Japan

Standards

Liquid Chemicals Japan TC Chapter Meeting 

Date: Friday, September 4, 2026

Time: 3:30 pm - 5:00 pm JST

Venue: SEMI Japan Office + OVTCCM (Hybrid)

 

AGENDA

 

Standards Contact Information:

Takeaki Hirabara

Standards & EHS, SEMI Japan

Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

Questions? Contact your local staff coordinator: Click here

3:30 pm - 5:00 pm Off Add to Calendar 2026-09-04 15:30:00 2026-09-04 17:00:00 Liquid Chemicals Japan TC Chapter Meeting Liquid Chemicals Japan TC Chapter Meeting Date: Friday, September 4, 2026Time: 3:30 pm - 5:00 pm JSTVenue: SEMI Japan Office + OVTCCM (Hybrid) AGENDA Standards Contact Information:Takeaki HirabaraStandards & EHS, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click here SEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi Chiyoda-ku, Tokyo 1000005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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SEMI Japan
26F, xLINK Marunouchi Eiraku Bldg.
1-4-1 Marunouchi
Chiyoda-ku, Tokyo
1000005
Japan

Standards

Silicon Wafer Japan TC Chapter Meeting


Date: Friday, August 28, 2026

Time: 1:00PM - 4:00PM JST

Location: SEMI Japan Office/ Official Virtual TC Chapter Meeting (Hybrid)

 


AGENDA

 

Standards Contact Information:

Akiko Yoshida
Manager, SEMI Japan
E-mail: [email protected] 

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend SEMI Standards meetings.

If you are not a Program Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress. Complete an application form today!

Questions? Contact your local staff coordinator: Click here

1:00 pm - 4:00 pm Off Add to Calendar 2026-08-28 13:00:00 2026-08-28 16:00:00 Silicon Wafer Japan TC Chapter Meeting Silicon Wafer Japan TC Chapter MeetingDate: Friday, August 28, 2026Time: 1:00PM - 4:00PM JSTLocation: SEMI Japan Office/ Official Virtual TC Chapter Meeting (Hybrid) AGENDA Standards Contact Information:Akiko YoshidaManager, SEMI JapanE-mail: [email protected]  NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend SEMI Standards meetings.If you are not a Program Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress. Complete an application form today!Questions? Contact your local staff coordinator: Click here SEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi Chiyoda-ku, Tokyo 1000005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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Verific App Store Opens with
Downloadable Examples of Parser Platform Applications

• Initial offerings include a hierarchy explorer, linter, HDL editor, signal tracer, essential tools for hardware design and verification
• Verific App Store opens July 27 as 63rd DAC begins in Long Beach, Calif.

ALAMEDA, CALIF. –– July 22, 2026 –– Verific Design Automation today announced the Verific App Store with a toolkit and downloadable example applications showcasing a variety of essential electronic design automation (EDA) point tools and solutions built using its Parser Platforms.

The Verfic App Store will open Monday, July 27, as the 63rd Design Automation Conference (DAC) convenes at the Long Beach Convention Center in Long Beach, Calif. Verific will offer in DAC Booth #1052 demonstrations of the new Verific App Store examples along with demonstrations of its SystemVerilog, Verilog, VHDL and UPF front-end Parser Platforms.

“We want to show how you can build really cool EDA products with our Platform," remarks Rob Dekker, Verific's president, founder and CTO. "In the Verific App Store, we started with a number of useful EDA point tools that are fast running, simple to license and easy to use by AI and HI (Human Intelligence) alike.”

As the leading provider of front-end platforms, Verific powers EDA with its SystemVerilog, Verilog, VHDL and UPF parser software used as the foundation for both in-house and commercially available EDA tools and flows. Applications range from synthesis and formal verification to emulation, debugging, virtual prototyping, low-power design and design-for-test tools.

Currently Available Parser Platform Apps
Example apps currently available at the Verific App Store include a hierarchy explorer, a linter, an HDL editor and a signal tracer, essential tools for hardware design and verification.

HierRTL is a Hierarchy Explorer that reports the structural hierarchy of Verilog, SystemVerilog, and VHDL designs directly from the parse tree without the need for elaboration. Engineers can visualize and navigate the hierarchical structure of their designs and understand relationships between different modules and components, making it easier to manage complex designs.

LintRTL is a Linter tool for SystemVerilog and VHDL that identifies design issues early with configurable lint rules and advanced synthesizability checks. It analyzes code for potential errors, style issues and adherence to coding standards. It helps ensure that the HDL code is clean and maintainable, reducing bugs before simulation or synthesis.

SnapRTL is an automated HDL editor used to analyze, modify and export designs while preserving the original code and formatting. It gives engineers confidence to be able to modify their designs in a specialized environment for writing and editing HDL code. SnapRTL features syntax highlighting, code completion and error detection, streamlining the coding process and improving productivity.

TraceRTL is a Signal Tracer for SystemVerilog and VHDL to improve traceability and speed debug. It monitors and analyzes signals within the design and provides insights into signal behavior during simulation, helping engineers effectively debug and optimize their designs.

Additional apps will be added in the future.

Availability and Pricing
"We will be adding more EDA point tools as we go,” says Dekker. “Currently most base products are free of charge, and we only charge a small fee for more advanced product features.”

The Verific App Store will open July 27. Tool flow developers can download the tools in the Verific Toolkit with or without being an existing Verific customer, but registration is required. New users will be asked to register with a Verific Passport account.

Basic tools are currently free, but advanced features require a monthly subscription fee. Free evaluations are available for 14 days.

The Verific App Store can be found at: https://store.verific.com/

Verific at DAC
Attendees can arrange demos or private meetings with Verific during DAC exhibit hours July 27-29 by sending email to [email protected].

DAC registration is open.

About Verific Design Automation
Verific Design Automation is the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups worldwide to develop advanced electronic design automation (EDA) products quickly and cost effectively. Verific’s software serves as the front end to synthesis, formal verification, emulation, debugging, virtual prototyping, low-power design and design-for-test tools. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 80,000 copies of its software used by the EDA and semiconductor industry since it was founded in 1999.

Engage with Verific at:
Email: [email protected]
Website: www.verific.com
LinkedIn: https://www.linkedin.com/company/verific-design-automation-inc/

Brno, Czech Republic - July 10, 2026

Tescan, a pioneer in electron microscopy, announces the successful completion of its full acquisition by Shimadzu Corporation. As of July 7th, Tescan officially becomes a member of the Shimadzu Group, marking an important milestone in the company’s continued growth and evolution.

This step builds on the strong business alliance established in 2024 and reflects a shared commitment to advancing scientific discoveries and industrial innovations worldwide.
 

“For Tescan customers, this new chapter brings enhanced capabilities, broader expertise, and expanded access to integrated solutions, while preserving the agility, innovation, and customer focus that define the Tescan way,” said Sirine Assaf, CRO, Tescan. 

By combining Tescan’s leadership in surface analysis and electron microscopy technologies, including SEM, FIB-SEM, and TEM, with Shimadzu’s strengths in compositional and materials analysis, customers will benefit from:
 

  • More comprehensive solutions across research, development, and production workflows

  • Deeper application support through combined expertise in materials science, life sciences, and semiconductors

  • Accelerated innovation driven by joint R&D and shared technologies

  • Access to a larger global support network and enhanced service capabilities

  • Expanded product portfolio and future integrated offerings

Importantly, Tescan remains committed to maintaining its customer-centric approach, strong technical support and responsiveness, ensuring continuity in partnerships and daily operations.

Tescan’s growth will be further supported by Shimadzu’s global presence, particularly in Asia, alongside strengthened positions in Europe and the Americas. This will allow Tescan to:
 

  • Reach new markets and customers worldwide 

  • Scale manufacturing and service capabilities

  • Enhance operational efficiency while maintaining flexibility 

At the same time, Tescan will continue to operate from its headquarters in Brno, preserving its identity, expertise, and innovation culture. 

Since its founding in 1991, Tescan has delivered over 4,000 electron microscopes across more than 80 countries, supporting customers in both research and industrial environments. 

This acquisition reinforces Tescan’s long-term strategy to expand its technological leadership and deliver higher-value solutions, ensuring customers remain at the center of its development. 

The successful collaboration between Tescan and Shimadzu has already been demonstrated through the joint “Shimadzu by Tescan” SEM product line introduced in Japan. 

Building on this strong foundation, the integration marks a natural next step in deepening cooperation across technologies and markets. As part of this evolution, Tescan will adopt a new endorsed brand identity, “Tescan, A Shimadzu Company,” across its portfolio and communications. This reflects both the strength of the combined organizations and Tescan’s continued commitment to delivering innovative, customer-focused solutions under a globally recognized framework.

This acquisition is in fully synergy with Tescan and Shimadzu strategic plans and it makrs an acceleration of what Tescan already does best: delivering high-performance systems, application-driven innovation, and close collaboration with customers.

Tescan develops and manufactures advanced electron microscopy solutions for materials science, life sciences, semiconductor research, industrial R&D, and quality control. With a focus on imaging performance, automation, usability, and long-term collaboration, Tescan helps researchers see the invisible and accelerate discovery through reliable, future-ready microscopy workflows.