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In today’s fast-paced and interconnected world, the electronics industry faces unprecedented challenges from global disruptions, geopolitical uncertainties, and supply chain vulnerabilities. To remain competitive and resilient, organizations must adopt robust risk management frameworks that proactively identify and mitigate risks.


This webinar is brought to you by the Resiliency Working Group, part of the SEMI Supply Chain Management Initiative. We will explore the creation and implementation of an industry-standard risk management framework tailored to the unique complexities of the electronics supply chain. Attendees will learn how to assess potential risks, develop mitigation strategies, and leverage cutting-edge tools to improve visibility and responsiveness across their supply networks.

Key topics include:


•     The critical risks impacting electronics supply chains and how to address them.
•     Best practices for building a resilient and adaptable risk management framework.
•     Strategies for real-time risk monitoring, supplier risk assessments, and scenario planning.
•     How to align your supply chain with industry standards for business continuity and operational stability.

Who should attend:


•    Supply chain managers
•    Risk officers
•    Operations executives
•    Anyone involved in supply chain planning and resilience in the electronics sector

Join us to discover actionable insights and practical approaches to future-proof your electronics supply chain, ensuring it remains resilient, efficient, and prepared for any disruption.
 

Speaker bio:

Austin Evans is the Director of Supply Chain Risk Management at Intel.  He is responsible for overseeing risk management for Intel’s supply chain as well as Intel’s Contingent Workforce Program Office.  His organization is responsible for business continuity, governance, resilience, supply chain security and compliance. 

United States

Austin Evans.jpg
Austin Evans
Director of Supply Chain Risk Management
Intel
Standards

Join us for a deep dive into the new industry-standard risk management framework tailored to the unique complexities of the electronics supply chain. Hosted by the SEMI Resiliency Working Group, this webinar will equip supply chain professionals with actionable insights on assessing critical risks, developing robust mitigation strategies, and leveraging advanced tools for real-time monitoring.

Off Add to Calendar 2024-10-24 00:00:00 2024-10-24 00:00:00 Building Resilient Supply Chains Join us for a deep dive into the new industry-standard risk management framework tailored to the unique complexities of the electronics supply chain. Hosted by the SEMI Resiliency Working Group, this webinar will equip supply chain professionals with actionable insights on assessing critical risks, developing robust mitigation strategies, and leveraging advanced tools for real-time monitoring. United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles
Event format

Brooks Instrument, a world leader in advanced flow measurement and control, recently celebrated a grand opening for its new manufacturing facility in Penang, Malaysia, where it produces mass flow controllers (MFCs) used in semiconductor and other critical gas flow control applications.

The 57,000-square-foot plant, which began shipping MFCs in January 2024, is Brooks Instrument’s fourth global production area. The other locations are in the U.S., Hungary, and Korea.

Brooks Instrument is owned by Illinois Tool Works (ITW), one of the world’s leading diversified manufacturers of specialized industrial equipment. ITW has a 42-year history of investment in Penang, with ITW Meritex providing packaging solutions for chips that support semiconductor back-end customers.

The Brooks Instrument grand opening took place at the end of August and included Dato’ Seri SH Wong, President of the Malaysia Semiconductor Industry Association (MSIA) and Dato’ Loo Lee Lian, CEO of InvestPenang, along with several other government officials, industry dignitaries, and customers.

Patty Hartzell, Executive Vice President, Test & Measurement and Electronics at ITW, gave the keynote address and paid tribute to the efforts of the team who made the new facility operational in record time.

“I am proud to say it took less than a year from the time we approved the capital expenditure to the day when the first mass flow controllers were produced in the factory,” said Hartzell.

She also recognized the support Brooks Instrument received from several government and industry groups, including InvestPenang, Majlis Bandaraya Seberang Perai (MBSP), the Malaysian Investment Development Authority (MIDA), Penang Development Corporation (PDC) and MSIA.

The new Penang site includes Brooks Instrument’s largest Class 100 clean room manufacturing area and will allow the company to double its worldwide MFC production capacity. The high-volume facility is mainly producing GF100 series mass flow controllers, which are often viewed as the semiconductor industry standard for reliable and repeatable delivery of process gasses.

The factory also serves as an additional location for manufacturing and parts inventory, complementing the company’s other production facilities while reducing the risk of a supply chain disruption.

About Brooks Instrument
Since 1946, Brooks Instrument has been a leader in precision fluid measurement and control technology. Providing instrumentation for flow, pressure and vapor delivery, the company serves customers in semiconductor and high-tech manufacturing, laboratories and other processes and industries. With manufacturing, sales and service locations in the Americas, Europe and Asia, Brooks Instrument has the world’s largest installed base of mass flow controllers.

For more information, please visit www.BrooksInstrument.com. The company is also on LinkedIn (www.linkedin.com/company/Brooks-Instrument) and YouTube (www.youtube.com/user/Brooks407).

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Heterogeneous Integration (HI) has come a long way in 50 years. The world of multi-chip modules (MCMs) has given way to a vast ecosystem of chiplets, 3D stacked die, and co-packaging of antenna, high-bandwidth memory (HBM), and optics. HI is at the center of “More than Moore” development activities, as innovative engineers look for creative ways to overcome the slower scaling of silicon technology. The promise of HI is new devices with superior power, performance, area, and cost (PPAC). All these promises come with new challenges. Managing different process nodes, physical characteristics, mechanical stresses, and other system-level challenges not found in monolithic system-on-chip (SoC) devices, creates a great opportunity for design and manufacturing companies to reshape our industry. 

 

In this webinar, we’ll explore this enabling technology from both the device maker and material supplier perspectives. We will learn about demands placed on devices by new applications and what new tools are needed to meet these demands. We will also hear about the challenges placed on materials and equipment suppliers to develop processes capable of manufacturing the individual components and integrating them into final products. Join us as our panel of experts address the issues and opportunities involved with heterogeneous integration. 
 

United States

Arsalam Alam
Arsalan Alam, PhD
Member of Technical Staff (MTS), 3D Stacking Technology Group
AMD Packaging

2nd Generation 3D V-Cache™ Enablement

Andrea Chacko
Andrea Chacko, PhD
Director of Packaging Solutions
Brewer Science
Dong Shun Bai
Dongshun Bai, PhD
Business Development Director and Senior Technologist of Packaging Solutions
Brewer Science

Enabling Heterogeneous Integration through Material Design

The realization of Heterogeneous Integration (HI) has been key in driving advancements in semiconductor technology. The complexities of integrating dissimilar materials continue to be a challenge for HI. All advanced packaging technologies rely on advanced materials to address the many challenges in achieving continued shrinking and improved performance of devices. Novel materials capable of managing mechanical stresses and increased thermal budgets with strict cleanliness requirements are required for processes such as wafer thinning, fan-out wafer-level packaging, and hybrid bonding. This presentation will highlight how advanced materials can address the growing challenges in the industry.

Andrea Maret
Andrea Maret
Senior Knowledge Manager
Entegris

Webinar Moderator

APHI CAST EHS NBMC Smart MFG SMG Sustainability EMG ESD Alliance FlexTech FOA ITL MSIG SCIS SE&A SiPAT SOI

Dive into the dynamic world of semiconductor materials and discover the future landscape as the industry experts provide a glimpse into the future of the semiconductor ecosystem in the era of heterogenous integration.

10:00 am - 11:00 am Off Add to Calendar 2024-10-16 10:00:00 2024-10-16 11:00:00 Heterogeneous Integration finds its place Dive into the dynamic world of semiconductor materials and discover the future landscape as the industry experts provide a glimpse into the future of the semiconductor ecosystem in the era of heterogenous integration. United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles REGISTER NOW
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Chip Integration Technology Center (CITC) today announced the appointment of Toni Versluijs as the new chairman of its Supervisory Board. Versluijs will serve as the incoming chairman from September through December. Effective January 1, 2025, he will take over the responsibilities from chairman Roel Fonville who is retiring.

Versluijs has an extensive background of more than 25 years in the semiconductor industry, of which more than 15 years in general and executive management roles. Prior to this appointment, he worked for NXP, where he led the In-Vehicle Networking product line and was NXP Nijmegen site director and statutory director of NXP Netherlands. Most recently, he led the Business Group MOS at Nexperia, served as statutory director for Nexperia in the UK and was part of the company’s global executive leadership team.

He explains his choice for CITC: “I look forward to using my many years of experience in the semiconductor industry to contribute to the success of CITC in Nijmegen. Nijmegen is a location with a long heritage in semiconductor packages that have changed the world. CITC is a unique venture and has a unique position between private parties, the academic world and knowledge institutes.”

CITC is a smaller and different kind of organization than his previous employers, but Versluijs sees the potential: “CITC has attracted quite some talent in recent years, built partnerships and initiated new developments. In short: it has laid the foundation for growth, and it will flourish in the coming years. I am convinced that it has the potential to change the world of semiconductor packaging again.”

The current chairman of the CITC Supervisory Board, Roel Fonville, adds: “The Supervisory Board is very pleased to welcome Toni Versluijs to our midst. His personality and broad experience in the industry and in the Nijmegen region will help the Board to fulfill its role in securing the continued development of the organization.”

About CITC
Chip Integration Technology Center (CITC) is a non-profit, joint innovation center specializing in heterogeneous integration and advanced chip packaging technology. CITC has created an effective ecosystem in which companies, research and educational institutes work on bridging the gap between academics and industry. CITC's contribution to the ecosystem is to provide access to innovation, infrastructure, and education. CITC was founded in 2019 with strategic partners TNO and Delft University of Technology and is supported by local and regional governments.
www.citc.org

Certified B CorporationTM recertification and 2024 Impact Report accredit commitment to positive impact.

Rolla, MO – July 30, 2024 – Brewer Science, Inc., a global leader in semiconductor innovation, is thrilled to announce its recertification as a Certified B Corporation™. This achievement underscores Brewer Science's steadfast commitment to sustainable business practices and ethical operations.

Certified B Corporations meet high standards of verified social and environmental performance, transparency, and accountability. Brewer Science's recertification reaffirms its dedication to People Using Business as a Force for Good®, aligning with a global movement of companies seeking to balance profit with purpose. Brewer Science received its initial B Corp Certification in 2021. Certified B Corporations are required to renew their certification every three years, by completing a meticulous assessment process conducted by B Lab™, the certifying body of B Corps, which examines over 170 factors while reviewing Brewer Science’s customers and vendors, record of inclusion, community involvement, corporate governance and environmental impact. Key elements such as average employee tenure, charitable giving, energy savings plan, recycling policies, employee volunteer service, and employee upward mobility are also analyzed.

Alongside this milestone, Brewer Science is proud to unveil its 2024 Impact Report, offering a detailed overview of the company's impact across the five key areas identified by B Corp: Governance, Workers, Community, Environment, and Customers.

The 2024 Impact Report showcases Brewer Science's significant achievements and progress in fostering positive impacts within its sphere of influence. Highlights include:

• Environment Impact
o Reducing carbon footprint for Scope 1 and Scope 2 GHG by 80% from baselines (2018) by 2030
o Achieving net zero carbon footprint by 2050

• Customer Impact
o Building a collaborative supply chain
o Participating in industry consortiums, such as SEMI

• Employee Impact
o Improving employee benefits, such as community service leave
o Assessing employee satisfaction through third-party anonymous survey

• Community Impact
o Collaborating with companies, like Askinosie Chocolate, to improve public health
o Supporting STEM education in schools and community organizations

• Governance Impact
o Ensuring equity by being Certified Employee-Owned
o Providing transparency through third-party audits, such as GreenCircle Certified

"Renewing our Certified B Corporation status underscores Brewer Science's ongoing dedication to integrating social and environmental responsibility into our core business strategy," states Terry Brewer, Founder and Executive Chairman of Brewer Science. "Since our initial certification, we've leveraged over three years of experience to amplify our impact across global operations, benefiting our employees, communities, and customers worldwide. We believe in the mission to Use Business as a Force for Good, and we will continue to deliver on our promise to drive positive change and create lasting value for all stakeholders."

Brewer Science's recertification reflects its continuous journey towards driving positive change within the semiconductor industry and beyond. By maintaining B Corp status, the company remains part of a global community of like-minded organizations dedicated to redefining success in business.

To access the 2024 Impact Report and learn more about Brewer Science's sustainability initiatives, please visit www.brewerscience.com/going-green.

About Brewer Science
Brewer Science is a global leader in developing and manufacturing next-generation materials and processes that foster the technology needed for tomorrow. Since 1981, we’ve expanded our technology portfolio within advanced lithography, advanced packaging, smart devices, and printed electronics to enable cutting-edge microdevices and unique quality monitoring systems for water and air applications. We are Certified Employee-Owned and a Certified B Corporation™, using our business as a force for good. Our headquarters are in Rolla, Missouri, with customer support throughout the world. Learn more at: www.brewerscience.com.

About B Lab
B Lab is transforming the global economy to benefit all people, communities, and the planet. A leader in economic systems change, the global network creates standards, policies, tools, and programs for business, and we certify companies — known as B Corps — who are leading the way. To date, 8,000 B Corps across 95 countries and 161 industries employ over 750,000 workers, and more than 280,000 companies manage their impact with the B Impact Assessment and the SDG Action Manager. B Lab has created and led efforts to pass over 50 corporate statutes globally that enable stakeholder governance: www.bcorporation.net

REGISTRATION

Registration
  • Early bird registration close: 5pm, Wednesday, September 4 KST
  • Registration fee includes lunch at the venue.

 

[Early Bird - Group (5 or more people from a company)]

  • SEMI Members: KRW 275,000
  • Non members: KRW 330,000

[Early bird]

  • SEMI Members: KRW 308,000
  • Non members: KRW 363,000

[Onsite]

  • SEMI Members: KRW 385,000
  • Non members: KRW 385,000
Registration
South Korea APS 썸네일.png Business Technical

OVERVIEW

  • Date: September 11(Wed), 2024  
  • Time: 09:00 - 17:30  
  • Venue: Convention Hall 3, 3F, Suwon Convention Center  
  • Language: Korean / English (Simultaneous interpretation will be provided)
  • Organizer: SEMI Korea 

 

SPONSORS

 

NOTICE

  • The agenda will be subject to change without notice.
  • Presentation files agreed by speakers will be provided to attendees.

 

CONTACT

Convention Hall 3, 3F, Suwon Convention Center
South Korea

9:00 am - 9:30 am
김대우
Dae-Woo Kim
Samsung Electronics

The Journey of Semiconductor Industry and the Innovation of Advanced Packaging

Competition in the semiconductor industry is becoming fiercer and advanced package technology has become important for achieving low-power and high performance computing. As the Moore’s law reach the limitation, Si fabrication process need extremely high cost solutions such as multiple patterning and EUV (Extreme Ultra-Violet) lithography. In spite of high cost Si fabrication process, chip size is increased over the reticle size limit by adding more and more functional blocks for high performance computing. In particular, with the continuous demand for higher performance and capacity in memory products, the amount of data created, processed, stored and transferred is increasing tremendously. In order to overcome these challenges, advanced package based on RDL (Re-Distribution Layer), flip chip bonding, and TSV (Through Silicon Via) have been actively used for heterogeneous integration in electronic packages since the past decade. The heterogeneous integration and chiplet has been attracting a lot of attention since it enables higher bandwidth with low power consumption at reduced cost. 2.5D Si interposer architecture has been widely used for horizontal interconnection between logic to logic and logic to high bandwidth memory integration. 3D stacking architecture is for vertical interconnections enabling small form factor, increasing signal speed, reducing power consumption and power dissipation. In this talk, recent advanced package technology and key roadmap in Samsung Electronics will be shared for mobile and AI/HPC product.

※ Biography

9:30 am - 10:00 am
David Harame
David Harame
NYCREATES/AIM Photonics

Co-Process and Co-Development to Address Challenges in Co-Packaged Optics (CPO)

Co-Packaged Optics is the combination of photonic integrated circuits and electronic circuits at a system packaging level. The essential need is to get light in and out of the system, usually from optical fibers, with the least losses and ease of manufacturing. Photonic integrated circuits (PICs) are fabricated in CMOS semiconductor fabrication facilities, which allows manufacturers to take advantage of the large installed base of tools and processes. However, electronic packaging is currently not equipped to handle the challenges associated with packaging advanced photonic devices. In this presentation we explore some of these challenges for optical coupling such as sub-micron alignment tolerances, sensitivity to temperature variations, optical losses, and a lack of standards. The end objective is to have optical coupling look like electronic coupling. At NYCREATES/AIM Photonics, we have learned that the best results are obtained when the PIC manufacturing and packaging processes are co-designed to better achieve low-loss coupling, particularly between photonic integrated circuits and other elements in the system. A complete “end-to-end” approach includes customizing the PIC process, wafer manufacturing including interposers and heterogeneous integration, electronic photonic design automation, and electronic-photonic test, assembly and packaging capabilities. A complete approach will lead to reliable and affordable solutions that will ensure the manufacturing-readiness of this critical technology for decades to come.

※ Biography

10:00 am - 10:30 am
손호영
Ho-Young Son
SK hynix

Advanced Packaging Technology for HBM and 2.5D SiP

Rapid growth of generative AI at this moment has never been experienced for a few decades and it makes surprising impact to human experience and semiconductor industry as well. High bandwidth memory (HBM) which started from memory solution for high-end graphic applications has being emerged as a key driver accelerating the growth of AI industry due to remarkable advantages on the smaller latency between memory and GPU.

SK hynix has been the pioneer of HBM in all of history and firstly wrote a new record by the world-first development of HBM package in 2013. More remarkable footprint in the HBM history was the world-first adoption of the mass reflow bonding and molded underfill (MR-MUF) technology to the HBM 4Hi and 8Hi in 201, which nobody has never tried due to its notorious difficulties of process and material technologies. In this effort, SK hynix is providing a state-of-the-art of HBM products with highest memory bandwidth and memory capacity, highest power efficiency, and superior thermal dissipation ability and its package technology is a core competency leading the memory renaissance in the post-pandemic era.

In align with HBM technology innovation, there are continuous changes in 2.5D system-in-package (SiP) in order to improve the memory bandwidth and accommodate higher memory capacity. There has been many different types of proxy package structure to assure the HBM quality and reliability but it is obviously not certain whether HBM package can guarantee all the possible quality and reliability risks due to many possible changes of HBM and SiP packages in the future. In this paper, we would like to introduce several ways to evaluate the thermal and electrical characteristics of HBM and its package reliability.

※ Biography

10:30 am - 11:00 am
전진영
Jinyoung Jeon
ASMPT

Enabling the AI Era

The AI era has arrived and to enable and perpetuate it, the semiconductor advanced packaging (AP) industry needs to innovate in a torrid pace to keep in tandem the exponential growth of the Gen AI computing power.
Rising to the challenge, ASMPT has been leveraging its first mover market position in advanced packaging to continue innovating its end-to-end solutions to scale with the latest packaging architecture with the most demanding chiplet interconnects and heterogeneous integration formats.
Going forward, the AP industry shall undergo a “Power of N” transformation where interconnect pitch shall shrink rapidly along with thinner and bigger package formats, demanding new technologies in materials, process and equipment signaling a need for a complete and robust ecosystem to evolve for Gen AI to continue scaling.

※ Biography

11:00 am - 11:20 am

Break

11:20 am - 12:30 pm
All speakers

Panel Discussion

2:00 pm - 2:30 pm
SungSoon Park
SungSoon Park
Intel

The Role of Advanced Packaging Technology for AI

As artificial intelligence (AI) continues to advance, the demand for high-performance computing has never been greater. Advanced packaging technologies play a pivotal role in meeting these demands by enhancing the performance, power efficiency, and integration density. This presentation explores the impact of various advanced packaging solutions, including 2.5D with Si interposers, 2.3D with RDL interposers, and 3D packaging technologies, on the development and optimization of AI systems.
We will delve into the specifics of 2.5D packaging, where Si interposers enable the integration of heterogeneous dies side by side, allowing for high-bandwidth communication and reduced latency. The presentation will also cover 2.3D packaging with RDL interposers, which offer a cost-effective alternative by utilizing advanced RDL processes to achieve similar benefits as 2.5D, but with potentially lower manufacturing complexity and cost.
Furthermore, we will examine 3D advanced packaging technology, which stacks dies vertically to further enhance integration density and performance. This approach not only maximizes space efficiency but also minimizes interconnect lengths, leading to significant improvements in speed and power consumption which are critical factors for AI applications.
Through a comprehensive analysis, this presentation will highlight how these advanced packaging technologies contribute to the acceleration of AI innovation, enabling more powerful, efficient, and compact AI packaging solutions.

※ Biography

2:30 pm - 3:00 pm
Mooseong Kim
Mooseong Kim
LG Innotek

FCBGA Substrate Technologies for AI/ HPC

Big data, artificial intelligence (AI), and high-performance computing (HPC) underscore the critical importance of advanced packaging technologies. Over the past decade, significant progress in 2.5D and 3D heterogeneous integration has led to notable improvements in I/O capacity, performance, cost efficiency, power consumption, and signal speeds for large-scale data processing. 

In particular, 2.5D semiconductor packaging technologies such as EMIB and CoWoS are crucial for increasing I/O connections while reducing the interconnect length between logic and memory components, thereby enhancing performance and reducing latency. 

However, FCBGA substrates used in AI/HPC packaging face considerable technical challenges. These substrates often need to be larger than 100mm x 100mm and consist of more than 20 layers. Furthermore, incorporating advanced technologies like silicon capacitor embedding and bridge integration into large-body FCBGA substrates presents additional hurdles as the industry moves towards next-generation packaging solutions. 

This presentation thoroughly explores the latest technology trends in FCBGA substrates. 

※ Biography

3:00 pm - 3:30 pm
황태경
TaeKyeong Hwang
Amkor Technology Korea

Advanced Packages for Chiplet

3:30 pm - 4:00 pm
Bongyoung Yoo
Prof. Bongyoung Yoo
Hanyang University

Glass Substrates: Present and Future Potential

As the demand for higher performance, greater miniaturization, and improved thermal management continues to grow in the electronics industry, advanced packaging technologies are becoming increasingly critical. Glass substrates are emerging as a key material in this domain, offering unique advantages over conventional organic and silicon-based substrates. This talk explores the present and future potential of glass substrates in advanced packaging, focusing on their electrical, thermal, and mechanical properties that make them suitable for next-generation semiconductor devices.
It will also highlight recent innovations in glass substrate manufacturing, such as through-glass vias (TGVs) and surface modification techniques, which enhance the performance and reliability of electronic components.

※ Biography

4:00 pm - 4:20 pm

Break

4:20 pm - 5:30 pm
All Speakers

Panel Discussion

Semiconductor Integration & Packaging: Powering AI and HPC
The Advanced Packaging Summit is a conference dedicated to exploring the latest advancements in packaging technology for high-performance computing (HPC) and AI. The summit brings together leading experts, researchers, and industry professionals to share their insights and experiences on advanced packaging solutions that enable powering AI and HPC systems. Topics covered at the summit include 2.5D packaging, Chiplet packaging, CPO, FCBGA substrate technology and more. Attendees will gain valuable insights and have the opportunity to network with experts in the industry.

 

9:00 am - 5:30 pm Off Add to Calendar 2024-09-11 09:00:00 2024-09-11 17:30:00 Advanced Packaging Summit 2024 Semiconductor Integration & Packaging: Powering AI and HPCThe Advanced Packaging Summit is a conference dedicated to exploring the latest advancements in packaging technology for high-performance computing (HPC) and AI. The summit brings together leading experts, researchers, and industry professionals to share their insights and experiences on advanced packaging solutions that enable powering AI and HPC systems. Topics covered at the summit include 2.5D packaging, Chiplet packaging, CPO, FCBGA substrate technology and more. Attendees will gain valuable insights and have the opportunity to network with experts in the industry.  Convention Hall 3, 3F, Suwon Convention Center South Korea SEMI.org [email protected] America/Los_Angeles public Discover APS 2025
Event format
Promote in calendar
Off

Verific Design Automation today affirmed its position as the leading provider of front-end platforms powering an emerging electronic design automation (EDA) space by collaborating with a group of well-funded artificial intelligence (AI) EDA startups.

These new AI EDA companies use Verific’s unsurpassed language support for fast, accurate large language model (LLM) development, speeding time to market for products that range from functional verification, chip design to code development.

AI EDA providers PrimisAI and Silimate, founded by former chip designers, will be in the Verific booth (#1414) AI showcase at the 61st Design Automation Conference (DAC) June 24-26 at Moscone West in San Francisco.

“This new and exciting market segment is about to change the entire makeup of the EDA industry,” says Rick Carlson, vice president of Verific. “We are about to see a variety of tools, technologies and methodologies destined to change the way chip design and verification is done.”

Introducing the EDA Startups Ushering in the Era of AI EDA
PrimisAI and Silimate will be showcased in the Verific DAC booth and present their unique use of AI technology to eliminate error-prone repetitive tasks for efficient and more productive chip design.

PrimisAI offers a generative AI solution for chip design with advanced language-to-code and language-to-verification capabilities through its interactive AI assistant to address complex hardware challenges across the entire design stack from concept to bitstream/GDSII. RapidGPT, unveiled earlier this year, lets engineers interact with their design and the entire EDA ecosystem with a natural language interface, boosting productivity and accelerating time-to-market. Founded by serial entrepreneur Naveed Sherwani who serves as chairman and CEO, PrimisAI is backed by two early-stage investors.

“Verific’s front-end platform lived up to its well-earned status of industry standard as we implemented it in RapidGPT,” remarks Pierre-Emmanuel Gaillardon, CSO of PrimisAI. “The robustness and quality of the Verific front-end platform ensured we would deliver a tool that would give engineers a seamless and efficient workflow.”

Silimate, backed by Y Combinator, is building the co-pilot for chip designers to help build better chips faster. Silimate finds functional bugs, predicts power, performance and area (PPA) issues, and recommends real and accurate fixes in real time, and is already being used by chip teams building complex IP and SoCs. Co-founders Ann Wu and Akash Levy previously built chips and EDA tools at Apple, Stanford, NVIDIA, and Synopsys.

“Verific consistently produces quality products and offers exceptional quality support,” comments Wu. “Their parsers are fantastic and result in very quick tool bring-up times for our customers.”

Metalware co-founded by Ryan Chow and Andrew Nedea is another Verific front-end platform user. It was started with initial funding from Y Combinator with the mission to accelerate embedded development using AI technology after personally experiencing repeated bottlenecks in embedded software at SpaceX. The Metalware AI EDA tools help designers rapidly write HDL and embedded C/C++ by combining insights from manuals, datasheets and code, offering 10x faster development by automating low-level programming.

“Verific embodies our stated goals to reduce the time it takes to design chips and systems,” affirms Chow. “Verific and its team of experienced EDA engineers have shown repeatedly that its front-end platforms enable a project that would normally take days to be completed in hours.”

Another AI EDA startup in stealth mode is also a new Verific user. Details will be announced shortly.

DAC AI Showcase
Verific will demonstrate its SystemVerilog, Verilog, VHDL and UPF front-end platforms, while PrimisAI and Silimate will be in the Verific DAC Booth #1414 at various times of the day to give 10-minute presentations.

DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

To arrange a demonstration or private meeting, send email to [email protected]

DAC registration is open.

About Verific Design Automation
Verific Design Automation is the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effective worldwide. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry since it was founded in 1999.

Engage with Verific at:
Email: [email protected]
Website: www.verific.com
LinkedIn: https://www.linkedin.com/company/verific-design-automation-inc/
Facebook: https://www.facebook.com/Verific-Design-Automation-100448363329771/

Primarius Technologies will demonstrate its entire portfolio of EDA toolchain and one-stop design enablement solutions that integrate advanced parallelization technologies with industry-proven modeling and simulation engines at the 61st Design Automation Conference (DAC) June 24-26 at Moscone West in San Francisco.

Also announced today: Primarius acquired Magwel N.V., provider of 3D solver- and simulation-based layout analysis and design solutions for digital, analog/mixed-signal, power management, automotive and RF ICs, and launched ESDiTM, a chip-level human body model (HBM) analysis platform and power device design, and PTMTM, a layout verification tool family.

Demonstrations will highlight Primarius’ fast, accurate device modeling and cell library characterization and circuit simulation solutions based on its continuous innovation and R&D expertise, including:

• SDEPTM, the spec-driven extraction platform that builds auto model extraction flows for fast SPICE model extraction, a key engine enabling efficient Design-Technology Co-Optimization (DTCO), and an extended capability on top of the de facto golden-standard SPICE modeling platform, BSIMProPlusTM.
• NanoSpice XTM, the latest high-performance SPICE simulator addressing simulation capacity and accuracy challenges of big post-layout designs at advanced process nodes.
• NanoSpice Pro XTM, the latest FastSPICE simulator with simulation performance and accuracy needs tailored for SRAM, DRAM, Flash and big analog-on-top designs in high-performance computing, mobile, AI and other advanced applications.
• NanoCellTM, the latest standard cell library characterization solution employs advanced distributed parallel architecture technology and cell circuit analysis extraction algorithms embedded with a high-precision SPICE simulator, making it a fast, accurate and easy-to-use alternative to other commercial solutions.
• ESDi, state-of-the art HBM analysis, simulation and verification tool for on-chip ESD protection.

The Primarius Product Portfolio
IC company challenges designing and manufacturing high-end chips have increased sharply. Foundries and IDMs need to provide their design customers with more comprehensive and accurate SPICE models, more reliable and complete PDKs, and more coverage of standard cell library within shorter development cycles. Chip designers also require stronger COT capabilities to work with device engineers to customize process and devices, develop customized SPICE models, and perform re-characterization of cell libraries based on actual applications.

Primarius provides complete EDA toolchain and a one-stop design enablement technical development solutions. Innovations like these can shorten the SPICE model development cycle from several months to a few weeks or even hours for quick iteration addressing the efficiency bottleneck of DTCO. The advanced simulation technologies speed-up challenging circuit simulation by several times, and the latest cell library characterization solution provides the best throughput with near-linear scaling on thousands of x86 or ARM CPU cores on a computer farm or public cloud.

It aims to enable faster turnaround from technology development to advanced chip designs. Solutions include advanced analysis capabilities for high-sigma yield, aging, EM/IR, ESD, signal integrity and more targeting optimum yield and power, performance and area (PPA).

Primarius also provides the 9812 series, an industry-golden low frequency noise testing system used by most industry-leading semiconductor companies worldwide. Its latest release, 9812AC, is the only commercial low-frequency noise system under AC excitation and designed for the most advanced process development and chip designs.

Magwel N.V. Acquisition
Primarius acquired Belgian-based Magwel N.V. driven by broad market demand and technological evolution, integrating its chip-level HBM ESD analysis platform, the power device design and layout verification tool suite and other technologies into the Primarius portfolio.

“Primarius and Magwel share a common goal of enhancing the market competitiveness of overall analog and power semiconductor solutions,” states Dr. Lianfeng Yang, President of Primarius. “Magwel's integration will further advance our strategy to optimize DTCO, enhance our technology portfolio, expand our product coverage and further strengthen and consolidate our market competitiveness.”

Availability and Pricing
Primarius Technologies. Pricing is available upon request.

For more information, visit the Primarius website or send email to [email protected].

Primarius Technologies at 61st DAC
Primarius Technologies will be in DAC booth #1415 Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

To arrange a private meeting or demonstration of the Primarius Technologies product portfolio, send email to: [email protected].

DAC registration is open.

About Primarius
Primarius Technologies (688206.SH) is a global electronic design automation (EDA) company providing innovative DTCO-enabled EDA solutions for advanced technology development, and complex full custom designs including analog, mixed-signal and memory circuits. Primarius provides the industry’s de facto golden SPICE modeling solution adopted by most of the leading semiconductor companies for more than a decade, and leading SPICE/FastSPICE technologies proven by leading memory and SoC design companies worldwide. Its design enablement EDA solutions enable a full coverage of fab technology development and fabless COT flow development including device testing systems, SPICE modeling and PDK development solutions, and standard cell library characterization solutions. Built around an innovative SPICE/FastSPICE dual engine, Primarius provides a complete circuit simulation and analysis solution with comprehensive high-sigma yield and signal integrity analysis, aging and EM/IR, ESD simulation and advanced circuit checking capabilities. Primarius also provides a complete full custom design environment with advanced circuit design and optimization, layout automation and physical verification functions, and hierarchy design planning and timing analysis solutions for advanced SoC designs. Visit Primarius Technologies for more information.

Sunnyvale, USA - Meylan, FRANCE – May 29, 2024 Numem - a leader in high-performance Memory IP Cores and Memory Chip/Chiplet based on its patented NuRAM (MRAM) and SmartMem technologies, and IC’ALPS - a leader in ASIC/SoC design and supply chain management, have pooled their expertise to meet the challenge of developing an ambitious integrated circuit with RISC-V processors, 2MBytes of NuRAM and a DSP/AI Custom Datapath Accelerator. The Custom SoC was developed in an advanced technology node.

This SoC has been designed and implemented to highlight the Numem high-performance, low power Memory subsystem with a RISC V Processor and AI Accelerator for ultra-low power applications. It has been developed through a close collaboration between Numem and IC’ALPS.

The physical implementation of this integrated circuit was made in a secure space (isolated location, network, and servers, encrypted exchanges, etc.) to meet with the stringent protection of sensitive data required by this program.

“We were very pleased with the collaboration and quality of service provided by IC’ALPS which made this on-time tape out possible and first time functional silicon,” said Jack Guedj, CEO of Numem. NuRAM with SmartMem is a high-performance memory subsystem which is 2-3x smaller and boast significant power reduction over SRAM,” he added.

Lucille Engels, COO of IC’ALPS indicated: “The challenges were numerous including: architecture, power domains, protection of the sensitive data, run times pushing improvement of EDA flow and the pressure of the tape out deadline.”

Numem and IC’Alps intend to extend their partnership to serve new customers SoC projects – feel free to contact us.

NUMEM/IC'ALPS with ultra-low-power SoC for Sensor and AI

About NUMEM
Numem, headquartered in Sunnyvale, California, is the leading provider of Memory Subsystem Chip/Chiplet and IP based on proven foundry MRAM process. Numem’s patented NuRAM technology enables best in class power/performance and reliability with 2.5x smaller area and 85x lower leakage power than traditional SRAM. Numem’s SmartMem subsystem technology significantly improves performance and endurance as well as ease-of-use and reliability for high-volume deployment and enables to reach ultra-high bandwidth.
Visit our website at https://www.numem.com or contact us at [email protected].

About IC’Alps
IC’Alps is your one-stop-shop ASIC partner. Based in France (HQ in Grenoble, two design centers in Grenoble and Toulouse), the company provides customers with a complete offering for Application Specific Integrated Circuits (ASIC) and Systems on Chip (SoC) development from circuit specification, mastering design in-house, up to the management of the entire production supply chain. Its areas of expertise include analogic, digital and mixed-signal circuits (sensor/MEMS interfaces, ultra-low power consumption, power management, high-resolution converters, high voltage, signal processing, ARM and RISC-V based multiprocessors architectures, hardware accelerators) on technologies from 0.18 µm down to 5 nm, and from multiple foundries (TSMC, Global Foundries, Tower Semiconductor, X-FAB, STMicroelectronics, etc.). The company is active worldwide in medical, industrial, automotive, IoT, IA, mil-aero and digital identity & security sectors. IC’Alps is ISO 9001:2015, ISO 13485:2016, EN 9100:2018 certified, Common Criteria on-demand, IATF16949-ready, member of TSMC Design Center Alliance (DCA), ARM Approved Design Partner and X-FAB’s partner network. More information on www.icalps.com and follow us on https://www.linkedin.com/company/ic-alps

South Korea standards
Highlighted content

Seoul
South Korea

Standards

FPD Metrology Korea TC Chapter 

Date: Thursday, June 13, 2024

Time: 14:00-17:00 KST

via Hybrid

 

(subject to change) 

Last updated: May 13, 2024

 

NOTE: 

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend. 

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today! 

Questions? Contact your local staff coordinator: Click here 

Off Add to Calendar 2024-06-13 00:00:00 2024-06-13 00:00:00 FPD Metrology Korea TC Chapter Meeting FPD Metrology Korea TC Chapter Date: Thursday, June 13, 2024Time: 14:00-17:00 KSTvia Hybrid AGENDA (subject to change) Last updated: May 13, 2024 NOTE: Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend. If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today! Questions? Contact your local staff coordinator: Click here  Seoul South Korea SEMI.org [email protected] America/Los_Angeles public