REGISTRATION
- Early bird registration close: 5pm, Wednesday, September 4 KST
- Registration fee includes lunch at the venue.
[Early Bird - Group (5 or more people from a company)]
- SEMI Members: KRW 275,000
- Non members: KRW 330,000
[Early bird]
- SEMI Members: KRW 308,000
- Non members: KRW 363,000
[Onsite]
- SEMI Members: KRW 385,000
- Non members: KRW 385,000
OVERVIEW
- Date: September 11(Wed), 2024
- Time: 09:00 - 17:30
- Venue: Convention Hall 3, 3F, Suwon Convention Center
- Language: Korean / English (Simultaneous interpretation will be provided)
- Organizer: SEMI Korea
SPONSORS
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NOTICE
- The agenda will be subject to change without notice.
- Presentation files agreed by speakers will be provided to attendees.
CONTACT
- SEMI Korea Program Team ([email protected])
Convention Hall 3, 3F, Suwon Convention Center
South Korea
The Journey of Semiconductor Industry and the Innovation of Advanced Packaging
Competition in the semiconductor industry is becoming fiercer and advanced package technology has become important for achieving low-power and high performance computing. As the Moore’s law reach the limitation, Si fabrication process need extremely high cost solutions such as multiple patterning and EUV (Extreme Ultra-Violet) lithography. In spite of high cost Si fabrication process, chip size is increased over the reticle size limit by adding more and more functional blocks for high performance computing. In particular, with the continuous demand for higher performance and capacity in memory products, the amount of data created, processed, stored and transferred is increasing tremendously. In order to overcome these challenges, advanced package based on RDL (Re-Distribution Layer), flip chip bonding, and TSV (Through Silicon Via) have been actively used for heterogeneous integration in electronic packages since the past decade. The heterogeneous integration and chiplet has been attracting a lot of attention since it enables higher bandwidth with low power consumption at reduced cost. 2.5D Si interposer architecture has been widely used for horizontal interconnection between logic to logic and logic to high bandwidth memory integration. 3D stacking architecture is for vertical interconnections enabling small form factor, increasing signal speed, reducing power consumption and power dissipation. In this talk, recent advanced package technology and key roadmap in Samsung Electronics will be shared for mobile and AI/HPC product.
Co-Process and Co-Development to Address Challenges in Co-Packaged Optics (CPO)
Co-Packaged Optics is the combination of photonic integrated circuits and electronic circuits at a system packaging level. The essential need is to get light in and out of the system, usually from optical fibers, with the least losses and ease of manufacturing. Photonic integrated circuits (PICs) are fabricated in CMOS semiconductor fabrication facilities, which allows manufacturers to take advantage of the large installed base of tools and processes. However, electronic packaging is currently not equipped to handle the challenges associated with packaging advanced photonic devices. In this presentation we explore some of these challenges for optical coupling such as sub-micron alignment tolerances, sensitivity to temperature variations, optical losses, and a lack of standards. The end objective is to have optical coupling look like electronic coupling. At NYCREATES/AIM Photonics, we have learned that the best results are obtained when the PIC manufacturing and packaging processes are co-designed to better achieve low-loss coupling, particularly between photonic integrated circuits and other elements in the system. A complete “end-to-end” approach includes customizing the PIC process, wafer manufacturing including interposers and heterogeneous integration, electronic photonic design automation, and electronic-photonic test, assembly and packaging capabilities. A complete approach will lead to reliable and affordable solutions that will ensure the manufacturing-readiness of this critical technology for decades to come.
Advanced Packaging Technology for HBM and 2.5D SiP
Rapid growth of generative AI at this moment has never been experienced for a few decades and it makes surprising impact to human experience and semiconductor industry as well. High bandwidth memory (HBM) which started from memory solution for high-end graphic applications has being emerged as a key driver accelerating the growth of AI industry due to remarkable advantages on the smaller latency between memory and GPU.
SK hynix has been the pioneer of HBM in all of history and firstly wrote a new record by the world-first development of HBM package in 2013. More remarkable footprint in the HBM history was the world-first adoption of the mass reflow bonding and molded underfill (MR-MUF) technology to the HBM 4Hi and 8Hi in 201, which nobody has never tried due to its notorious difficulties of process and material technologies. In this effort, SK hynix is providing a state-of-the-art of HBM products with highest memory bandwidth and memory capacity, highest power efficiency, and superior thermal dissipation ability and its package technology is a core competency leading the memory renaissance in the post-pandemic era.
In align with HBM technology innovation, there are continuous changes in 2.5D system-in-package (SiP) in order to improve the memory bandwidth and accommodate higher memory capacity. There has been many different types of proxy package structure to assure the HBM quality and reliability but it is obviously not certain whether HBM package can guarantee all the possible quality and reliability risks due to many possible changes of HBM and SiP packages in the future. In this paper, we would like to introduce several ways to evaluate the thermal and electrical characteristics of HBM and its package reliability.
Enabling the AI Era
The AI era has arrived and to enable and perpetuate it, the semiconductor advanced packaging (AP) industry needs to innovate in a torrid pace to keep in tandem the exponential growth of the Gen AI computing power.
Rising to the challenge, ASMPT has been leveraging its first mover market position in advanced packaging to continue innovating its end-to-end solutions to scale with the latest packaging architecture with the most demanding chiplet interconnects and heterogeneous integration formats.
Going forward, the AP industry shall undergo a “Power of N” transformation where interconnect pitch shall shrink rapidly along with thinner and bigger package formats, demanding new technologies in materials, process and equipment signaling a need for a complete and robust ecosystem to evolve for Gen AI to continue scaling.
Break
Panel Discussion
The Role of Advanced Packaging Technology for AI
As artificial intelligence (AI) continues to advance, the demand for high-performance computing has never been greater. Advanced packaging technologies play a pivotal role in meeting these demands by enhancing the performance, power efficiency, and integration density. This presentation explores the impact of various advanced packaging solutions, including 2.5D with Si interposers, 2.3D with RDL interposers, and 3D packaging technologies, on the development and optimization of AI systems.
We will delve into the specifics of 2.5D packaging, where Si interposers enable the integration of heterogeneous dies side by side, allowing for high-bandwidth communication and reduced latency. The presentation will also cover 2.3D packaging with RDL interposers, which offer a cost-effective alternative by utilizing advanced RDL processes to achieve similar benefits as 2.5D, but with potentially lower manufacturing complexity and cost.
Furthermore, we will examine 3D advanced packaging technology, which stacks dies vertically to further enhance integration density and performance. This approach not only maximizes space efficiency but also minimizes interconnect lengths, leading to significant improvements in speed and power consumption which are critical factors for AI applications.
Through a comprehensive analysis, this presentation will highlight how these advanced packaging technologies contribute to the acceleration of AI innovation, enabling more powerful, efficient, and compact AI packaging solutions.
FCBGA Substrate Technologies for AI/ HPC
Big data, artificial intelligence (AI), and high-performance computing (HPC) underscore the critical importance of advanced packaging technologies. Over the past decade, significant progress in 2.5D and 3D heterogeneous integration has led to notable improvements in I/O capacity, performance, cost efficiency, power consumption, and signal speeds for large-scale data processing.
In particular, 2.5D semiconductor packaging technologies such as EMIB and CoWoS are crucial for increasing I/O connections while reducing the interconnect length between logic and memory components, thereby enhancing performance and reducing latency.
However, FCBGA substrates used in AI/HPC packaging face considerable technical challenges. These substrates often need to be larger than 100mm x 100mm and consist of more than 20 layers. Furthermore, incorporating advanced technologies like silicon capacitor embedding and bridge integration into large-body FCBGA substrates presents additional hurdles as the industry moves towards next-generation packaging solutions.
This presentation thoroughly explores the latest technology trends in FCBGA substrates.
Glass Substrates: Present and Future Potential
As the demand for higher performance, greater miniaturization, and improved thermal management continues to grow in the electronics industry, advanced packaging technologies are becoming increasingly critical. Glass substrates are emerging as a key material in this domain, offering unique advantages over conventional organic and silicon-based substrates. This talk explores the present and future potential of glass substrates in advanced packaging, focusing on their electrical, thermal, and mechanical properties that make them suitable for next-generation semiconductor devices.
It will also highlight recent innovations in glass substrate manufacturing, such as through-glass vias (TGVs) and surface modification techniques, which enhance the performance and reliability of electronic components.
Break
Panel Discussion
Semiconductor Integration & Packaging: Powering AI and HPC
The Advanced Packaging Summit is a conference dedicated to exploring the latest advancements in packaging technology for high-performance computing (HPC) and AI. The summit brings together leading experts, researchers, and industry professionals to share their insights and experiences on advanced packaging solutions that enable powering AI and HPC systems. Topics covered at the summit include 2.5D packaging, Chiplet packaging, CPO, FCBGA substrate technology and more. Attendees will gain valuable insights and have the opportunity to network with experts in the industry.
