downloadGroupGroupnoun_press release_995423_000000 copyGroupnoun_Feed_96767_000000Group 19noun_pictures_1817522_000000Member company iconResource item iconStore item iconGroup 19Group 19noun_Photo_2085192_000000 Copynoun_presentation_2096081_000000Group 19Group Copy 7noun_webinar_692730_000000Path
Default Banner Image

South Korea

Previous Page
South Korea

Espoo, Finland, July 14, 2025 – Beneq, a global leader in Atomic Layer Deposition (ALD) technology, is proud to announce significant progress in the microLED display market, underscored by repeat orders from industry-leading technology innovators. MicroLED technology is revolutionizing the future of displays across sectors including consumer electronics, augmented and virtual reality (AR/VR), and the automotive industry. With unparalleled brightness, contrast, energy efficiency, and durability, microLED represents a paradigm shift in how displays are designed and manufactured – enabling ultra-fine pixel resolution, seamless scalability, and longer device lifetimes. As demand for next-generation display solutions accelerates, microLED is poised to become the backbone of future visual interfaces.

According to Yole Group, global microLED display shipments are projected to grow at a compound annual growth rate (CAGR) of 180.6% from 2022, reaching 42.4 million units by 2029. Despite its promise, microLED development presents formidable challenges, particularly in scaling down pixel sizes to below 10 micrometers while maintaining uniformity, stability, and manufacturability. As pixels shrink, precise material control and surface passivation become critical to device performance. Atomic Layer Deposition offers a unique solution, enabling ultra-thin, conformal coatings with atomic-level precision. ALD addresses key barriers in microLED production, such as surface defect passivation, sidewall protection, transparent conductive oxides and final passivation, thereby improving both device efficiency and long-term reliability.

“Our top-tier customers rely on ALD technology to advance monolithic integration of microLEDs and driver electronics on a single chip. This integration paves the way for a new class of smaller, more powerful display products – delivering faster data transfer, lower power consumption, and a significantly more compact footprint,” says Mikko Söderlund, Head of Semiconductor ALD Sales.

“These repeat orders validate Beneq’s solution and demonstrate the company’s commitment to support customers through both the demanding development phase and the critical transition to volume manufacturing.”

Beneq’s Transform® ALD cluster platform stands at the forefront of this technological evolution. Designed for high-throughput production and advanced technology development, the Beneq Transform combines modularity, flexibility, and productivity, making it an ideal tool for microLED manufacturers. Its multi-chamber architecture supports a wide range of materials and processes, enabling customers to fine-tune optical and electrical properties while seamlessly scaling from lab to fab. By equipping microLED pioneers with the tools needed to overcome manufacturing barriers, the Beneq Transform is helping accelerate the commercialization of microLED displays – paving the way for brighter, smarter, and more sustainable electronic experiences.

About Beneq

Beneq pioneered industrial Atomic Layer Deposition (ALD) with the introduction of the first commercial ALD equipment in 1984. Today, Beneq advances ALD technology adoption and validation with a portfolio that includes Transform®, Transform® 300, and Prodigy™ for specialty semiconductor device fabrication; TFS 200 and TFS 500 for R&D; innovative spatial ALD platforms such as the C2R™, and Genesis for roll-to-roll processing. Beneq’s products support process innovation from lab to fab, enabling integration of ALD in high volume manufacturing. Headquartered in Espoo, Finland, Beneq operates globally to help customers scale ALD solutions for the future of semiconductors, optics, and functional coatings.

Press Contact

Charlotte Bärlund
Event and Communications Lead
[email protected]

Lie Luo
Head of Marketing
[email protected]

Martinez, CA—EUV Tech (EUVT), a global leader in designing and manufacturing at-wavelength EUV metrology equipment, is excited to announce the release of the FALCON Photoresist Flood Exposure Tool. As our next-generation EUV resist characterization and diagnostics tool, FALCON allows photoresist manufacturers to rapidly and accurately test EUV resist sensitivity, as well as providing patterning materials developers critical insights into exposure mechanisms.

Built upon EUV Tech’s proven resist tool technology, FALCON is a fully automated tool that supports high-throughput contrast curves on EUV-patterning materials and radiation chemistry diagnostics by integrating a wide variety of optional add-on analysis and processing modules.

Enhancing FALCON’s platform is an array of in-situ analysis and process modules, including Fourier Transform Infrared (FTIR) Spectroscopy, Atomic Mass Spectrometry, Total Electron Yield (TEY), Photo-Electron Spectroscopy (PES), environmental and vacuum bake module with additional diagnostics, and a scanner-environment exposure module.

Key to FALCON’s effectiveness is its highly uniform exposure spot size of 6 mm, supporting high-sensitivity chemical analysis and over 1,000 exposures for a 300 mm wafer in a single recipe run. Built-in data visualization tools make it possible to analyze this rich data. Combining uniformity, high configurability, and deep data collection and analysis makes FALCON a highly efficient, cost-effective tool for advanced photoresist development.

For more information on the enhanced FALCON Flood Exposure Tool or any of EUV Tech’s at-wavelength metrology tools, please visit euvtech.com.

About EUV Tech
EUV Tech enables technology advancement in the frontiers of semiconductor manufacturing and material science through the development of world-leading EUV and soft-x-ray instrumentation and techniques.

For further information, contact:
EUV Tech, Inc.
[email protected]
+1 (925) 229-4388

CEA LID World Summit, Grenoble, France, June 17, 2025 – Agileo Automation, a leading provider of control and connectivity solutions for global semiconductor manufacturing equipment, today announced the future expansion of its A²ECF-SEMI automation framework to include SEMI’s EDA (Equipment Data Acquisition) standards suite. This integration that already includes Agil’GEM and Agil’GEM300 will empower OEMs to deliver structured, high-bandwidth data to manufacturing facilities and drive process improvements with artificial intelligence (AI) by leveraging large amounts of reliable, actionable data. EDA standards, built on the legacy of SECS/GEM and GEM300, are transforming equipment communication and enabling high-speed, data-driven manufacturing. As semiconductor fabs become more connected and automated, the ability of OEM equipment to integrate seamlessly and deliver high-quality, structured data has become a competitive differentiator. 

Agileo Automation has carried out EDA Freeze 2 client and server tests with equipment manufacturers already supporting EDA and is working with these early adopters on the integration on their equipment using A²ECF-SEMI, Agil'GEM, and Agil'GEM300. The company will soon be providing a comprehensive offer for OEMs in need of EDA Freeze 2 or 3. EDA is increasingly required in RFQs that equipment manufacturers must address.

“EDA is going to enable fabs to realize superior yields, faster innovation cycles, and a sustainable competitive advantage in an ever-accelerating market,” explains Marc Engel, CEO of Agileo Automation. “Agileo is proud to be a major contributor to this global effort and pleased to support OEMs in all market segments with a complete and scalable product suite.”

About Agileo Automation

Since its inception in 2010 in Poitiers, France, Agileo Automation has empowered global semiconductor equipment manufacturers to optimize their production machines with control, communication, data acquisition, and testing solutions, enabling their deployment in large-scale fabs worldwide. At the heart of Industry 4.0, Agileo’s A²ECF-SEMI framework provides a robust foundation for developing equipment controller software, leveraging the SEMI SECS/GEM and GEM300 standard suites. As a member of SEMI and the OPC Foundation, Agileo Automation is a key contributor to the development and integration of industry standards such as SEMI standards and OPC Unified Architecture (OPC UA). For more information, please visit our web site or follow us on LinkedIn.

Nordson Electronics Solutions, a global leader in reliable electronics manufacturing technologies, has developed several solutions for panel-level packaging (PLP) during semiconductor manufacturing. In one particular case, Nordson’s customer, Powertech Technology, Inc. (PTI) saw underfill yields improve to greater than 99% as they plan to transition from wafers to panels in their manufacturing operations. For details about this solution developed in late 2024 and 2025, download the case study here: Customer Success: Powertech Technology Inc. (PTI) Advances Panel Level Packaging with Nordson.

PTI, one of the world’s top OSAT (Outsourced Semiconductor Assembly and Test) companies, worked with the Nordson applications team to set up a comprehensive PLP demonstration that achieved high-quality, void-free underfill results at scale, using the industry-leading ASYMTEK Vantage® Series fluid dispensing system, equipped with the ASYMTEK IntelliJet® Jetting system. Nordson’s precision technology mitigated warpage and optimized fluid flow while decreasing cycle time by almost 30%.

PLP offers a path to managing the complexity of larger die sizes and higher-density designs while maintaining manufacturability and cost efficiency as the semiconductor industry transitions from 300-mm wafers to panels. PTI is enabling PLP applications that are designed to meet the semiconductor industry’s growing demands to serve AI, high-performance computing (HPC), and chiplet-based architectures.

Underfill has been pivotal in semiconductor packaging since the adoption of flip-chips in the 1990s. As applications have become more demanding, particularly in high-performance CPUs, GPUs, and advanced architectures like flip-chip and 2.5D/3D ICs, the importance of underfilling to enhance mechanical reliability and thermal performance has grown. Since the beginning, Nordson developed innovations for underfill processes as the industry evolved from PC board, substrate, wafer, and now panel applications.

Nordson’s distributor, Jetinn Global Equipment Ltd., supported the advancements discussed in this case study by investing in demonstration equipment and providing expert technical support.

WATCH ON-DEMAND

Watch Now
Belgium France Germany Ireland Italy Japan Singapore South Korea Taiwan United States EMG Webinar 2025_1 Business Executive Technical
M Merck

Are We There Yet? Metrology and Inspection for Angstrom-Level Manufacturing ​

In the semiconductor industry where we routinely pattern sub-wavelength structures and require atomic-layer precision in our manufacturing processes, it’s easy to assume that we can simply measure everything we’re doing and all the structures we create. In reality, though, metrology and inspection have the challenging task of not just keeping up with device technology but staying far enough ahead that we can actually “see” our results and confirm the progress we’re making.

In this webinar, co-hosted with the Electronics business of Merck KGaA, Darmstadt, Germany; we will explore the metrology and inspection space to learn more about technological advances driving this vital segment of semiconductor manufacturing.

The webinar will feature presentations by Eric Beyne, PhD, Senior Fellow, VP R&D and Director of 3D System Integration Program for imec, and Dario Alliata, PhD, Senior Application Director for Metrology & Inspection at the Electronics business of Merck KGaA, Darmstadt, Germany.

Following the presentations, an interactive Q&A segment will allow attendees a chance to deepen their understanding of how materials innovation and advanced metrology intersect at the leading edge of manufacturing.

Join us to engage with peers and pioneers working at the forefront of materials science and semiconductor innovation!

 

United States

Dario Alliata
Dario Alliata, PhD
Senior Director of Applications
The Electronics business of Merck KGaA, Darmstadt, Germany

The Role & the Challenge of Metrology and Inspection in Advanced Packaging of AI Chips

The massive adoption of social networking and artificial intelligence has pushed the semiconductor industry to develop devices capable of supporting the required infrastructures. Increasingly powerful computer process units (CPU) are used to allow data centers to process trillions of information exchanges, while faster graphic process units (GPU) enable virtual and assisted reality.
Cost leveraging is now reachable with the integration of multiple dies in the same package, each one fabricated to handle specific functionalities with the most cost-effective technology node, which is a form of heterogeneous integration. This session highlights some examples of metrology and inspection solutions aimed at securing the manufacturability of devices for High Computing Power fundamental for AI applications. More in detail, it explores the challenge of the fabrication of chip-to-chip interconnections that are key for the heterogeneous integration of active components with vertical stacking like DRAM for High Bandwidth memories, where process tolerances are increasingly narrow and conditions to measure more and more extremes.

Biography
Dr. Dario Alliata joined Unity-SC, now part of the Electronics business of Merck KGaA, Darmstadt, Germany in the U.S. and Canada. In 2016 as product manager and is now Sr. Director of Applications with focus on Advanced packaging and Specialty substrates & devices.
He worked in the semiconductor industry for more than 25 years, initially in R&D centers and later in equipment makers. He spent his entire career developing process control solutions for securing the manufacturing chain in the semiconductor industry.
He received a MD in Physics from the University of Milan (Italy) and hold a Ph.D. in Physics & Chemistry from the University of Berne (Switzerland).

EB
Eric Beyne, PhD
VP R&D / Program Director 3D System Integration Program / Senior Fellow
imec

Sub-Micron Pitch Scaling of Hybrid Bond Interconnects: Metrology Challenges

Advanced 3D integration technology will increasingly rely on hybrid bonding technology for both wafer-to-wafer and die-to-wafer bonding. This allows for micrometer and sub-micrometer pitch interconnects, resulting in very high 3D interconnect densities, compatible with the back-end-of -line interconnect layers of active logic and memory die. The results are “seamlessly” interconnected die. Off-chip interconnects become equivalent (or better) than on-chip interconnects.
These great system-level benefits however come at some challenges. Small overlay errors or surface imperfections can prevent defects, resulting in yield loss. Critical process, steps, such as CMP, wafer dicing and surface cleaning steps, need to be monitored with higher accuracy to maintain a good process. New parameters, such as wafer shape, distortion, surface profile slopes, and copper pad recess levels need to be measured and continuously monitored. This poses significant challenges to metrology related to hybrid bonding. The presentation will highlight these needs and show some practical solutions.

Biography
Eric Beyne obtained a degree in electrical engineering in 1983 and the Ph.D. in Applied Sciences in 1990, both from the Katholieke Universiteit Leuven, Belgium. Since 1986 he has been with IMEC in Leuven, Belgium where he has worked on advanced packaging and interconnect technologies. Currently, he is imec senior fellow, VP R&D and program director of imec’s 3D System Integration program.

Michael Weigand
Michael Weigand
Senior Application Manager
Brewer Science

Moderator

Biography
I'm a seasoned Senior Application Manager at Brewer Science with over two decades of experience in Semiconductor industry. I lead application teams at Brewer Science Inc, focusing on advanced materials for the semiconductor industry. With a background in Material Science, I enjoy tackling technical challenges, from optimizing critical processes to finding creative ways to characterize materials.

EMG

Sponsored by the Electronics business of Merck KGaA, Darmstadt, Germany 

10:00 am - 11:00 am Off Add to Calendar 2025-09-17 10:00:00 2025-09-17 11:00:00 Are We There Yet? Metrology and Inspection for Angstrom-Level Manufacturing ​ Sponsored by the Electronics business of Merck KGaA, Darmstadt, Germany  United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles WATCH NOW
Event format
Promote in calendar
Off
Register for On-demand
Belgium China France Germany India Ireland Italy Japan Malaysia Russia Singapore South Korea Taiwan United States Vietnam Webinar-Critical Minerals-v1_360x317_Event_Calendar_CM Business Executive Technical
Highlighted content

As world leaders act to secure access to these minerals, companies come under pressure to follow due diligence guidelines to promote ethical sourcing of these materials for their supply chains.  Regulations such as the US Dodd-Frank Wall Street Reform and Consumer Protection Act (Section 1502), EU Regulation 2017/821 and the EU Corporate Sustainability Due Diligence Directive require companies to trace materials through their supply chains and report to the public about their use of conflict minerals. 

Several industry associations, including the Responsible Business Alliance’s Responsible Minerals Initiative, were created to help companies with their due diligence efforts. Reports such as those issued by the US Government Accountability Office on Conflict Minerals offer insights into the efficacy of these regulations and suggest improved approaches for industry engagement. 

The SEMI Responsible Supply Chain (RSC) working group was recently formed to host discussions on these topics. This webinar will provide insights from speakers Jennifer Peyser, Responsible Business Alliance Senior Vice President of Responsible Sourcing, and Kimberly Gianopoulos, Managing Director for the International Affairs and Trade team at the U.S. Government Accountability Office (GAO).

United States

8:00 am - 8:05 am
Kim Harrison
Dr. Kimberly Harrison, Ph.D
Senior MEMS Engineer
AMFitzgerald & Associates

Welcome and Introductions of RSC working group

Dr. Harrison is a MEMS Engineer with AMFitzgerald & Associates, a design firm located in the Bay Area California. She has a doctoral degree in mechanical engineering from Stanford University, and has worked as a designer and process engineer in the semiconductor industry for 10 years. She was nominated as a 2022 MEMS & Sensors Industry Group Emerging Leader. As a founding member and leader of the SEMI Responsible Supply Chain Working Group, she hopes to bring SEMI members together to discuss solutions to human rights issues in the semiconductor supply chain.

Conflict Minerals Supply Chain Overview

8:05 am - 8:35 am
Kimberly Gianopoulos
Kimberly Gianopoulos
Managing Director for the International Affairs and Trade
U.S. Government Accountability Office (GAO)

Report Review

Director Gianopoulos oversees a 140-person team that reviews a wide variety of federal government oversight issues, including International Security Assistance, Bilateral and Multilateral Foreign Assistance, International Trade and Finance, and U.S. Diplomatic Presence and Management. She serves as a facilitator in GAO’s Learning Center and participates in recruiting activities. Ms. Gianopoulos has received several awards, including a Distinguished Service Award, a Meritorious Service Award, a Client Service Award, and several Results Through Teamwork awards. Ms. Gianopoulos earned a Bachelor’s degree in Mathematics and a Master’s degree in Public Analysis and Administration from the State University of New York at Binghamton. She is a Certified Government Financial Manager and a member of Pi Alpha Alpha, the Global Honor Society for Public Affairs and Administration.

Jen Peyser
Jennifer Peyser
Executive Director
Responsible Minerals Initiative

RMI Activity Overview

“The RMI supports over 500 downstream, midstream, and upstream member companies with a suite of due diligence standards and tools, data, guidance, training, and other resources for global responsible sourcing and regulatory compliance. Our facility and supply chain due diligence standards are rooted in longstanding international norms while reflecting emerging corporate and stakeholder priorities for regulatory compliance, managing sustainability risks and impacts, and fostering responsible mineral supply chains.”

8:35 am - 8:55 am

Q&A

8:55 am - 9:00 am

Summary and Closing Remarks

SCM 8:00 am - 9:00 am Off Add to Calendar 2025-07-09 08:00:00 2025-07-09 09:00:00 Critical Minerals, Due Diligence and the Semiconductor Supply Chain United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register for On-demand
Event format
Promote in calendar
Off
South Korea standards-500w.jpg Technical
Highlighted content

Seoul
South Korea

Standards

EHS Korea TC Chapter 

Summer Meetings 2025 

Date: Friday, July 11, 2025 

Time: 10:00-12:00 (KST) 

via Hybrid

 

AGENDA 

(subject to change) 

Last updated: June 9, 2025

 

NOTE: 

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend. 

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today! 

Questions? Contact your local staff coordinator: Click here 

10:00 am - 12:00 pm Off Add to Calendar 2025-07-11 10:00:00 2025-07-11 12:00:00 EHS Korea TC Chapter Meeting EHS Korea TC Chapter Summer Meetings 2025 Date: Friday, July 11, 2025 Time: 10:00-12:00 (KST) via Hybrid AGENDA (subject to change) Last updated: June 9, 2025 NOTE: Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend. If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today! Questions? Contact your local staff coordinator: Click here  Seoul South Korea SEMI.org [email protected] Asia/Seoul public Asia/Seoul
Event format
Promote in calendar
Off

REGISTRATION

Registration
  • Early-Bird Registration Deadline: Wed, July 9, 5PM (KST)
  • Group Registration Deadline: Fri, July 4, 5PM (KST)
  • Registration fee includes a boxed lunch provided at the venue.  

 

[Group]

  • SEMI Member : KRW 275,000
  • Non Member: KRW 330,000
    * Group registration fee applies to groups of five or more from the same company.
    * For group registration inquiries, please contact SEMI Korea Program Team([email protected]).

[Early Bird]

  • SEMI Member: KRW 308,000
  • Non Member: KRW 363,000

[On site]

  • SEMI Member: KRW 385,000
  • Non Member: KRW 385,000
REGISTER NOW
Registration
South Korea APS2025_banner Business Technical

OVERVIEW

  • Date: July 16(Wed), 2025
  • Time: 09:00 - 17:00
  • Venue: Convention Hall 2, 3F, Suwon Convention Center
  • Language: Korean (Simultaneous interpretation will NOT be provided.)
  • Organizer: SEMI Korea  

 

SPONSORS

 

 

NOTICE

  • The agenda is subject to change at the discretion of the speakers.
  • Presentation files agreed by speakers will be provided to attendees after the event through SEMI registration website.

 

CONTACT

  • SEMI Korea Program Team ([email protected])
  • Simultaneous interpretation will NOT be provided.

Convention Hall 2, 3F, Suwon Convention Center
South Korea

9:00 am - 9:30 am
Choon Lee
Choon Lee
Intel

System Level Advanced Packaging

Rapidly evolving progress of AI and HPC has significantly increased computational and memory needs such as higher performance, lower power consumption, and wider memory bandwidth with reduced latency. An end application of AI/HPC comes down to Datacenter construction. Meeting the challenge of delivering this processing power in the datacenter requires systematic innovation from the device to the datacenter level. It starts with integrating highly optimized, domain-specific accelerators which should be integrated into advanced 2.5D and 3.5D packaging that minimize losses and power for high-speed communication while taking advantage of workload power management. AI computing introduces significant challenges for energy consumption and thermal management. Power delivery network is crucial for CPU, GPU and NPU power and performance of which solution can be DTC, IVR, mtal-insulator-metal (MIM) capacitor and thin film inductor, backside power rail, etc..  While Moore’s law has continued to yield transistor scaling necessary for these applications, the ever growing demand from models for AI training and inference pushes Si scaling in conjunction with the advent of advanced interconnects via disaggregation and reaggregation of chips in advanced packaging.  
We will discuss with examples and the challenges of utilizing packaging elements to their full potential and discuss how co-optimization is crucial to achieving the best results for any given set of system requirements and constraints.  

※Biography

9:30 am - 10:00 am
TaeKyeong Hwangv
TaeKyeong Hwang
Amkor Technology Korea

Advanced Packages for AI/HPC

※Biography

10:00 am - 10:30 am
신상훈
SangHoon Shin
Assistant Professor,
Hanyang University

Advanced Packaging and Reliability: Technologies Shaping the Next Generation

Advanced semiconductor packaging is now central to enabling continued performance scaling as conventional transistor scaling slows. This seminar introduces cutting-edge trends in advanced packaging, including 2.5D and 3D integration, fan-out wafer-level packaging, chiplet-based architectures, and glass interposers for optical I/O in AI and HPC systems. These technologies offer enhanced performance, form factor reduction, and system-level integration capabilities critical for future computing platforms.
Leveraging prior industry experience, this talk highlights real-world applications and challenges in designing and qualifying advanced SoC packages. Examples include CoWoS-based AI chip packaging, hybrid bonding techniques, and thermal design optimization for high-power systems.
As packaging structures become increasingly complex, reliability emerges as a critical bottleneck. The seminar explores major failure mechanisms such as thermal-mechanical fatigue, electromigration, interfacial delamination, and Through Glass Via (TGV) degradation. Reliability analysis methods including FEA-based stress modeling, time-to-failure prediction, and advanced failure diagnostics will be introduced.
By combining packaging innovation with reliability engineering, the talk aims to provide a comprehensive perspective on the technological and practical issues that must be addressed to enable robust, high-performance semiconductor systems in the AI and data-driven era.

※ 연사정보

10:30 am - 11:00 am
Sang Hyun Han
Sang Hyun Han
NOVA

Pushing the Boundaries: Challenges and Opportunities in Panel-Level Packaging Technology

As the AI era progresses, semiconductor devices are increasingly adopting 3D architectures to boost performance and power efficiency. At the same time, system technology co-optimization (STCO) is advancing through the use of chiplets and advanced wafer-level packaging. As the industry integrates more chips into chiplets, the size of interposers continues to grow. However, wafer-level packaging faces limitations in accommodating large interposers due to the constraints of 300mm wafer shapes and temporary carriers.
This trend is driving a shift toward panel-level packaging (PLP) to support higher packaging unit counts. Despite its potential, PLP still faces significant challenges—particularly in terms of process development and process control.
This paper explores the technical trends in panel-level packaging, focusing on the current challenges and potential solutions related to process control.

※ Biography

11:00 am - 11:20 am

Break

11:20 am - 12:30 pm
All speakers

Panel Discussion

1:30 pm - 2:00 pm
Jinho_An
Jinho An
Senior Director/ Technologist,
Applied Materials

Presentation New Innovations Enabling Fine Pitch D2W Hybrid Bonding

Heterogenous integration and advanced packaging is behind the technology that is enabling today’s AI and high-performance computing. This is done through complex architecture that utilizes platforms including microbumps, through silicon vias (TSV), high density fanout and hybrid bonding (HB). The integration of chiplets using any combination of these technologies is allowing the industry to extend the Moore’s law and overcome limitations of the Von Neumann architecture. Hybrid bonding is an especially appealing technology that helps improve power and performance (higher I/O density), as well as thermal management. Sub-10 ㎛pitch die-to-wafer (D2W) HB is already in production1) for 3DIC and the industry working on HB technology for High Bandwidth Memory as well2). However, there are continuous challenges for D2W that require new innovation in both processing and metrology & inspection (M&I), and also unique challenges for both logic and memory applications specific to its integration. The presentation will discuss how logic and memory HB technologies are different and what process and M&I technologies are needed to facilitate HVM of the HB technology across different applications. Process challenges including low temperature bonding, die warpage management and dicing will be discussed, while M&I challenges include the transition to e-beam technology for HB enablement.

1) R. Agarwal et al., “3D Packaging for Heterogeneous Integration”, IEEE ECTC, July 2022
2) Lee et al., “A Study on D2W Cu Bonding Technology for HBM Multi-die Stacking”, IEEE ECTC, May 2024

※Biography

2:00 pm - 2:30 pm
Taehong Min
Taehong Min
Samsung Electro-mechanics

Trend and Technology of Glass Package Substrate

2:30 pm - 3:00 pm
이동환
Dong Hwan Lee
Samsung SDI

Design and Development of High Thermal Conductive Molding Compounds for Advanced Packaging Applications

The ongoing miniaturization and increased integration density in electronic circuit systems, particularly in advanced technologies such as DRAMs for Through-Silicon Via (TSV) and High Bandwidth Memory (HBM), have elevated thermal management to a critical challenge in microelectronic packaging. The functional performance, operational lifespan, and reliability of electronic devices fundamentally depend on efficient thermal dissipation. As power densities escalate, enhancing the thermal conductivity of EMCs has become imperative for effective heat removal from increasingly complex electronic components. Consequently, research efforts focused on developing epoxy resins with superior thermal conductivity and identifying appropriate high-conductivity fillers represent the most viable approaches to addressing thermal management challenges in contemporary microelectronic systems.
Recently, we have successfully developed a high-performance epoxy molding compound (EMC) that solves critical thermal management challenges in advanced microelectronic packaging applications. Not only do these compounds provide extremely safe protection of integrated circuits from moisture, mobile ion contaminants and adverse environmental conditions, including temperature fluctuations, humidity and mechanical stress, but the enhanced thermal and mechanical properties of EMC formulations address the heat dissipation requirements of advanced technologies such as small electronic circuit systems, especially TSV and HBM applications.

3:00 pm - 3:30 pm
Prof. Yunhyeok Im
Prof. Yunhyeok Im
Georgia Institute of Technology

Next-Generation Thermal Strategies: The Liquid Cooling Revolution for AI Chips

※Biography

3:30 pm - 3:50 pm

Break

3:50 pm - 5:00 pm
All Speakers

Panel Discussion

Next-generation semiconductor packaging technologies are advancing rapidly in response to the explosive growth of high-performance semiconductor markets, including AI chips and HBM. At the Advanced Packaging Summit 2025, industry leaders from top global companies will share the latest developments and insights in advanced packaging technologies. The morning session will spotlight core technologies such as SLP and PLP, while the afternoon session will feature in-depth presentations on essential next-generation packaging technologies including hybrid bonding, glass substrates, materials for heat control, and liquid cooling solutions. Each session will also include panel discussions to encourage broad and practical exchanges of technical experiences, offering valuable opportunities for networking. We invite you to explore the future direction of next-generation semiconductor packaging with global industry experts and expand both your insights and business horizons at this premier event.

9:00 am - 5:30 pm Off Add to Calendar 2025-07-16 09:00:00 2025-07-16 17:30:00 Advanced Packaging Summit 2025 Next-generation semiconductor packaging technologies are advancing rapidly in response to the explosive growth of high-performance semiconductor markets, including AI chips and HBM. At the Advanced Packaging Summit 2025, industry leaders from top global companies will share the latest developments and insights in advanced packaging technologies. The morning session will spotlight core technologies such as SLP and PLP, while the afternoon session will feature in-depth presentations on essential next-generation packaging technologies including hybrid bonding, glass substrates, materials for heat control, and liquid cooling solutions. Each session will also include panel discussions to encourage broad and practical exchanges of technical experiences, offering valuable opportunities for networking. We invite you to explore the future direction of next-generation semiconductor packaging with global industry experts and expand both your insights and business horizons at this premier event. Convention Hall 2, 3F, Suwon Convention Center South Korea SEMI.org [email protected] Asia/Seoul public Asia/Seoul
Event format
Promote in calendar
Off

Registration

For questions, please contact [email protected]

Register for US/EU session (8:00-8:30am PT) Register for Asia session (5:00-5:30pm PT)
Belgium France Germany Ireland Italy Japan Malaysia Singapore South Korea Taiwan United States Vietnam Image Business Training Featured Speakers

Leverage SEMI U learning offerings to wrap up your 2025 professional development journey! Our pledge remains unwavering: providing comprehensive, technical education to equip you with the skills needed for a prosperous journey in the semiconductor sector.

Are you ready to take your semiconductor industry knowledge to the next level? We're thrilled to invite you to our upcoming webinar titled "SEMI University - 2025 and beyond." This webinar promises to be an informative session where you'll gain insights into the latest updates, exciting live trainings at SEMICON West and virtually the remainder of this year and beyond. 

During this webinar, you can expect to:  

  • Discover the latest updates and enhancements to SEMI U's course catalog.  
  • Learn about the exciting live, in-person training courses scheduled for SEMICON West.
  • Review upcoming virtual instructor-led trainings.
  • Gain access to a special 10% discount on ALL on-demand courses.  

 

United States

Headshot of Naresh Naik
Naresh Naik
Director, SEMI University
SEMI
SEMI U Workforce Development

Join us to discover our current course offerings, upcoming in-person and virtual trainings, and more. Engage in a Q&A session. Plus, by attending this free webinar, you'll receive a 10% discount code for all on-demand courses and will be entered into a raffle to win a FREE course bundle ($100 value). 

Choose your session:

8:00 am - 8:30 am Off Add to Calendar 2025-09-25 08:00:00 2025-09-25 08:30:00 SEMI University - 2025 & Beyond Join us to discover our current course offerings, upcoming in-person and virtual trainings, and more. Engage in a Q&A session. Plus, by attending this free webinar, you'll receive a 10% discount code for all on-demand courses and will be entered into a raffle to win a FREE course bundle ($100 value). Choose your session:US/EU: 8:00 AM – 8:30 AM PT [Register Now]Asia/US: 5:00 PM – 5:30 PM PT [Register Now] United States SEMI.org [email protected] America/Los_Angeles public Register Now
Event format
Promote in calendar
Off

Nijmegen, The Netherlands, 14 May 2025 — Trymax Semiconductor Equipment (Trymax), a leading provider of plasma- and UV-based solutions for semiconductor manufacturing, announces the installation of its 500th process chamber in Asia. This milestone reflects continued momentum across key regional markets—including China, Taiwan, South Korea, Malaysia, and the Philippines—and signals strong progress toward the company’s goal of 1,000 global installations by the end of 2025.

“Reaching 500 installations in Asia is a significant milestone for Trymax,” said Peter Dijkstra, Chief Commercial Officer at Trymax Semiconductor Equipment. “It reflects our team’s dedication to delivering practical, high-performance solutions with the speed and reliability that our customers need in order to stay competitive.”

Responsiveness as a Competitive Edge

In an industry where uptime, productivity, and reliability are critical, Trymax has earned a reputation for being highly responsive—from the inquiry stage to post-installation support. The company’s nimble structure allows it to take action quickly and decisively, enabling customers to manufacture with confidence. Many partners have cited the ease of communication with Trymax, and the timely support received, as reasons for early and continued engagement.

Supporting Asia’s Semiconductor Surge

Asia continues to lead global semiconductor growth, driven by accelerated adoption in high-demand sectors. Customers across the region are pushing forward with innovation and scale, particularly in:

• Automotive: The transition from internal combustion engine (ICE) vehicles to electric vehicles (EVs) is reshaping the industry. EVs require significantly more semiconductors—often up to 3,000 chips per vehicle—due to greater electrification, power management, and onboard computing systems. This shift is fueling demand for reliable, high-throughput semiconductor processing solutions.

• Artificial Intelligence (AI): The rise of AI and machine learning applications—from data centers to edge devices—is creating a surge in demand for advanced microprocessors and high-density memory. Backend processes play a critical role in ensuring the performance and yield of these complex chips, making equipment reliability and process control essential.

• 5G & Connectivity: Asia’s rapid deployment of 5G networks, combined with its mobile-first population and high-volume data consumption, is pushing the limits of semiconductor performance. This growth requires advanced packaging technologies, faster interconnects, and increased wafer-level precision—all of which depend on stable, repeatable backend processing steps.

Trymax’s plasma and UV curing technologies are designed to meet these demands, delivering proven results in ashing, descum, surface cleaning and activation, and isotropic etching. With a strong footprint across the region, the company continues to support customers at the forefront of innovation.

Forward Plans and Strategic Vision

To support its continued growth in Asia and globally, Trymax is advancing several strategic initiatives. The company is exploring plans to establish local manufacturing in China, a move aimed at strengthening supply chain resilience and improving responsiveness to regional customer needs.

As part of its 2025–2030 roadmap, Trymax is also deepening its collaborations with leading semiconductor manufacturers. By taking on selective, non-core process steps—particularly those related to backend wafer processing—Trymax helps larger players free up internal resources and maintain operational focus where it matters most.

In parallel, Trymax is expanding its role in advanced packaging. As integrated circuit (IC) designs evolve toward increasingly complex multi-layered stacks—sometimes comprising up to 16 layers—ensuring pristine, activated surfaces between each layer is critical. Trymax’s plasma solutions are engineered to meet these exacting standards, enabling customers to maintain high yield and reliability in next-generation device architectures.

Meet Trymax at SEMICON Southeast Asia 2025

Trymax will be showcasing its latest plasma-based innovations at SEMICON Southeast Asia 2025, from 20–22 May at the Sands Expo and Convention Centre, Marina Bay Sands, Singapore. Attendees are invited to meet the Trymax team at Booth #B1633 to learn more about the company’s technology roadmap and expansion plans.

###

About Trymax Semiconductor Equipment

Trymax’s core business is to support semiconductor manufacturers through the world with innovative plasma-based solutions for photoresist removal, surface cleaning, isotropic etch, as well as UV curing and charge erase applications, that are used in the fabrication of integrated circuits and other semiconductor devices. Trymax is a privately held company headquartered in Nijmegen, The Netherlands. Trymax operates regional sales and service offices in Europe, UA, China, Southeast Asia, Taiwan, and Japan.

Learn more at www.trymax-semiconductor.com.

Results per page
Select
Results per page
Subscribe to South Korea