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From Concept to Reality: Advancing Digital Twins in Semiconductor Manufacturing
Following up on the SEMI Digital Workshop 2023, this workshop will delve into the practical aspects of implementing digital twin technology in semiconductor manufacturing. The aim is to bridge the gap between theoretical concepts and real-world applications, providing participants with actionable insights and strategies to successfully develop and integrate digital twins into their operations. Further the workshop aims to address some of the future upcoming challenges in the areas of integration of multi-modal real time data sources, security, process complexity, scalability, and standards.
SEMI HQ
673 S Milpitas Blvd.
Milpitas, CA 95035
United States
Morning, Day 1: December 4, 2024
Registration & Breakfast
Session #1 - Data Needs for Digital Twins - Data Sources, Integration & Interoperability
This session will explore the critical data requirements for creating and maintaining digital twins. Integrating multi-modal data sources (sensors, enterprise systems, equipment, etc.) that feed into digital twins, ensuring that they accurately reflect their physical counterparts is a minimum necessity. This session will also cover data integration techniques (from various factory systems), and interoperability to support dynamic digital twins.
Welcome Remarks
Keynote - Enabling Autonomous Operations Through Integrated Digital Twins
Semantic Models for Microelectronic Manufacturing & Development
Journey to Twins: A toolkit for Capabilities & Data to Digital Twins
Coffee Break - Sponsored by INFICON
Overcoming Data Interoperability Challenges for Effective Digital Twins
Building Process & Supply Chain Digital Twins through Integrated Data Assets and Secure Data Sharing
Special Session - SmartUSA – Semiconductor Digital Twin Manufacturing USA Institute
Lunch
Afternoon, Day 1: December 4, 2024
Session #2 - Data Standards for Digital Twins: Managing Unclean Factory Data
This session will focus on the importance of data standards for digital twins in semiconductor manufacturing, particularly in the context of dealing with unclean factory data. It will explore the challenges associated with unclean data and discuss strategies for cleaning and standardizing to ensure seamless ingestion into digital twins at various levels. Best practices for data validation, transformation, and integration as well as how to implement robust data standards to enhance reliability and accuracy of digital twins.
Sponsored by - Seeq
Keynote - Addressing Future Challenges in the Stochastics Era of Patterning with EUV Dry Resist
New patterning technologies will be needed to advance the device roadmap to 2 nm and beyond. Minimum pitch scaling will be exceptionally difficult to achieve at these advanced nodes, even with EUV patterning. Stochastic effects using wet resists during EUV patterning become problematic at the nanoscale, and can lead to line collapse, bridging, unacceptable line edge roughness (LER) and line width roughness (LWR). These stochastic effects present challenges when optimizing the tradeoffs between EUV resist resolution, dose, sensitivity, line edge / line width roughness, defectivity and cost.
In this talk, we will review the basics of dry resist technology, including dry resist equipment requirements, process flows and process integration modeling. In addition, we will present data that documents the advantages of dry resist technology over wet resist technology, demonstrating superior image quality, scaling and yield. We will conclude the talk by demonstrating a digital twin of the process integration and usage of optimization to achieve improved LER/LWR characteristics.
Charting the Digital Twin Standardization Path: An Iterative Implementation and Abstraction Process
Coffee Break - Sponsored by INFICON
Feature Engineering as the bridge to Semantic Factory Data
Control Software Integration with Digital Twins: How Virtual Data Aligns with Physical Reality
Panel: Harmonizing Standards for Semiconductor Digital Twins
Networking Reception - Sponsored by Sentient Cloud
Morning, Day 2: December 5, 2024
Registration & Breakfast
Session #3 - Modeling High Complexity Semiconductor Processes
This session will explore the integration of digital twin technology in modeling high complexity semiconductor processes. As the semiconductor industry advances, the need for precise and efficient modeling techniques becomes crucial. Digital Twins offer a transformative approach to simulate and optimizes these processes, though challenges exist. Cases studies and future innovations will also be covered in this session.
Welcome Remarks
Keynote: Key Enablers for Semiconductor Equipment and Process Digital Twins: Accelerated Computing (AC), Artificial Intelligence (AI) and Physics Modeling
AI Driven Digital Twins for Semiconductor Manufacturing
AI and Physics-based Models for Technological Development with High Complexity Semiconductor Processes
Coffee Break - Sponsored by PhysicsX
Digital Twin Flow Using AI/ML Applied to Ferroelectric Memory
Leveraging Virtual Twins and AI for Enhanced Fabrication Technology Co-Optimization in Semiconductor Manufacturing
Panel Discussion
Lunch - Sponsored by Dassault Systemes
Afternoon, Day 2: December 5, 2024
Session #4 - GenAI & AI/ML Role in the Development of Digital Twins - Implementation Strategies for DT
Integrating AI/GenAI & Digital Twins - Explore the cutting-edge integration of Generative AI (GenAI) and Artificial Intelligence/Machine Learning (AI/ML) in the creation and evolution of digital twins. This session will delve into how GenAI & AI/ML technologies are revolutionizing the simulation, prediction, and real-time replication of physical assets in semiconductors through case studies and practical applications.
Keynote - Accelerating Digital Twins with Gen AI
The rise of sophisticated AI tools, including generative AI, is revolutionizing the semiconductor industry by enabling the analysis of vast datasets to generate valuable insights. Executives in the sector see generative AI as a transformative force rather than just another tool. They believe it can deliver significant value, particularly in manufacturing, operations, and maintenance, its potential for process and equipment analysis, Predictive maintenance and smart diagnostics.
As fabs adopt smart manufacturing and virtual modeling it is pertinent for digital twins to leverage technologies like generative AI for data generation, Data Synthesis/Augmentation, Real Time Analysis, Model Optimization (AI enhanced physics models) , Rapid Prototyping and Accelerated Design and Development with data-driven model-based learning.
About Cross-Fertilization between Digital Twins and AI Techniques for Capacity Planning and WIP Flow Optimisation in Semiconductor Fabs
Developing Explainable Digital Twins for the Semiconductor Industry Using GenAI, Knowledge Graphs, and ML Techniques
Coffee Break - Sponsored by PhysicsX
Real-Time Digital Twins for Semiconductor Manufacturing: Accelerating Multi-Physics Optimization with Physics-Based AI
Advancing Industrial Data Architectures & Models for AI in Process Digital Twins
Panel - Rewiring organizations for AI / Digital twin: a business-backed view of successful implementation and challenges in adoption of Digital twins in the semiconductor industry
Following up on the SEMI Digital Workshop 2023, this workshop will delve into the practical aspects of implementing digital twin technology in semiconductor manufacturing. The aim is to bridge the gap between theoretical concepts and real-world applications, providing participants with actionable insights and strategies to successfully develop and integrate digital twins into their operations. Further the workshop aims to address some of the future upcoming challenges in the areas of integration of multi-modal real time data sources, security, process complexity, scalability, and standards.
Given the exclusivity and richness of discussions, please note that seats are capped at 80 attendees. Don’t wait to secure your spot.
