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As AI systems push requirements for higher bandwidth, lower power, and increased integration density, 3D integrated circuits (3DIC) are moving rapidly from development to production. However, scaling 3DIC introduces complex application challenges across the manufacturing flow, where process interactions and control become critical.
This talk examines key 3DIC applications and process challenges, including high aspect ratio TSV etch, void free TSV fill, and dielectric deposition, required for reliable wafer and die level stacking. Emerging applications such as inter die gap fill for advanced chiplets integration and plasma dicing for improved yield, edge quality, and die strength further increase integration complexity and productivity demands.
The presentation highlights Lam Research innovations across etch, deposition and clean processes that enable tighter process windows, improved uniformity, and higher throughput. In addition, equipment intelligence and data driven control are increasingly essential to enhance yield learning and manufacturing productivity. Together, these advances are enabling scalable, high volume 3DIC manufacturing for next generation AI systems.

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The future of compute will not be defined by silicon alone. As AI reshapes industries and economies, advanced packaging has become the foundation of the next era of innovation, enabling unprecedented gains in performance, efficiency, and scale. During his keynote, Yin Chang will explore how breakthroughs in heterogeneous integration, chiplets, and advanced manufacturing are transforming bold AI ambitions into deployable systems, and why AI leadership will depend not only on compute power, but on the ability to integrate and manufacture at scale.

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The rapid electrification of automotive and industrial systems is placing increasingly stringent demands on power semiconductor devices in terms of voltage capability, thermal performance, reliability, and system integration. This presentation reviews recent trends in power devices and power module packaging technologies aimed at improving performance while addressing cost and manufacturability constraints.
First, the fundamental differences between digital and power devices are outlined, followed by an overview of power device applications based on silicon (Si), silicon carbide (SiC), and gallium nitride (GaN) technologies, together with Amkor’s product portfolio.
Next, power module packaging technologies are discussed with a focus on key electrical and thermal challenges. Representative solutions, including advanced interconnects, cooling architectures, and embedded power modules, are introduced, along with a brief overview of Amkor’s technology roadmap.
Finally, the role of the Amkor Technology Japan R&D Center in supporting open innovation and global collaboration is briefly discussed.

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The presentation explores advanced packaging technologies designed to meet the escalating performance and power efficiency demands of AI and High-Performance Computing (HPC). To overcome the limitations of traditional semiconductor architectures, System Technology Co-Optimization (STCO) is introduced as a critical framework for managing thermal crosstalk and enhancing heterogeneous integration. The discussion highlights key innovations, including Customized HBM (cHBM) for optimized base-die performance and Samsung's 2.xD packaging portfolio, which encompasses Cube S, Cube E, and Cube R. Specifically, the 2.3D Cube E leverages panel level packaging to enable larger interposers and increased HBM integration, significantly improving productivity and reducing silicon fab burdens. The technical achievements in PLP—such as precise warpage control and the realization of fine RDL patterns (2/2μm)—are detailed to demonstrate their viability for large-scale AI chips. Furthermore, the roadmap extends toward 3D integration and Co-Packaged Optics (CPO) to maximize bandwidth and energy efficiency. Finally, the importance of an ecosystem-wide collaboration is emphasized as the driver for future innovation in "More than Moore" technology. These advancements collectively provide a scalable path toward the next generation of AI hardware acceleration.

※ Biography

Glass core substrates exhibit low CTE and significantly higher rigidity than conventional organic substrates and are therefore regarded as promising core materials for next-generation build-up packages. However, a major challenge lies in the occurrence of SeWaRe defects (delamination in glass), which arise from thermal stresses induced by the mismatch in the coefficients of thermal expansion (CTE) between the glass material and the build-up resin.
To mitigate this issue, we proposed a structure in which the corner regions of each individual piece are formed from resin. However, considering the thermal history during chip mounting, it became evident that the suppression effect was insufficient. Therefore, an edge‑protection material was applied to relieve the stress concentrated at the edges of each individual piece. As a result, it was confirmed that SeWaRe defects could be effectively suppressed even under thermal loading.
Through these efforts, we successfully developed a glass core build-up package substrate incorporating 11 layers of single‑sided copper wiring (22 layers in total).

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AI and data-intensive workloads are outpacing what conventional semiconductor technology can deliver. Two innovations are stepping in to close the gap: Silicon Photonics, which brings optical-speed, low-power data transmission into the data center, and Advanced Packaging, which uses chiplets and 2.5D/3D integration to maximize performance and efficiency at the chip level.
This talk examines how these complementary technologies are reshaping HPC architecture—covering their current state, how they work in tandem, and the key technical and commercial barriers to large-scale adoption.

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Co-packaged optics (CPO) is emerging as a key enabler for scaling bandwidth while containing power and cost in next-generation AI and cloud infrastructure. By moving optical engines closer to the switch ASIC and shortening high-speed electrical reaches, CPO can reduce SerDes power, ease signal-integrity constraints, and increase overall front-panel bandwidth density. However, delivering these benefits at volume requires new approaches across package architecture, manufacturing, and system integration.
This presentation reviews the main packaging challenges that must be solved to industrialize CPO, including thermal management and heat spreading near high-power silicon, fiber attach and optical alignment tolerances, photonics/laser integration choices, high-density optical and electrical I/O, substrate and interposer selection, and reliability risks such as warpage, CTE mismatch, and contamination control. Test and rework strategy, yield learning, and supply-chain readiness (materials, assembly, and metrology) are highlighted as practical barriers to adoption.
The talk also outlines opportunities created by CPO packaging innovations—such as modular optical tiles, standardized fiber interfaces, advanced lid/heat-sink concepts, and co-design of electrical, mechanical, and optical domains—to unlock higher radix switches and lower system power. Attendees will leave with a structured view of technology tradeoffs, a roadmap of near-term versus long-term packaging options, and actionable considerations for bringing CPO from prototypes to deployable products.

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AI is fueling unprecedented growth and accelerating demand for advanced devices. Its requirements for performance, power, and area scaling are driving memory and logic devices toward 3D architectures.
At the heart of this 3D transformation, processing steps must enable taller, perpendicular structures as well as smaller features. Meeting these requirements calls for new deposition and etch capabilities that did not exist before, leading to breakthroughs needed in areas such as atomic-level deposition and etch (ALD and ALE), high-aspect-ratio processing, dry resist EUV patterning, and the adoption of new materials like molybdenum (Mo). As a result, the transition to 3D devices will drive increased intensity of deposition and etch processing.
This presentation will explore how deposition and etch are critical to unlocking the future of 3D devices, with increasing velocity required to meet the demands of AI-driven innovation.

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As the semiconductor industry navigates the challenges of dimensional and functional scaling in the artificial intelligence (AI) era, advanced materials science has emerged as a critical enabler for performance enhancement. Modern AI-centric architectures demand the integration of increasingly complex system-on-chip (SoC) designs with non-traditional material systems.
This work details a high-throughput methodology for the rapid down-selection and optimization of multi-element thin films, ensuring alignment with both physical and electrical key performance indicators (KPIs). Utilizing combinatorial physical vapor deposition (PVD) in conjunction with unit-cell electrical test vehicles, we systematically screen an expansive elemental compositional space to identify optimal candidates. Advanced machine learning (ML) algorithms are integrated into each phase of the development lifecycle—spanning precursor synthesis, process optimization, and heterogeneous integration—to satisfy the rigorous specifications of emerging device applications. The synergy between integrated materials engineering and AI-driven informatics significantly reduces the temporal gap between material discovery and device-level implementation.

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Chemical and materials research faces increasing demands for data-driven automation and autonomous research systems due to vast exploration spaces and complex decision-making processes. In this talk, we introduce EXAONE Discovery as a Chemical Agentic AI system and present an integrated research framework designed to accelerate scientific discovery.
EXAONE Discovery is an agent-based system that tightly integrates property prediction, molecular generation, synthesis prediction, and literature/data extraction. Based on given research objectives, the system accumulates relevant data, generates candidate molecules using model-driven approaches, evaluates their properties, and derives feasible synthetic routes—automating the end-to-end discovery pipeline. Furthermore, it is designed to enable a closed-loop research paradigm by interfacing with autonomous laboratories, connecting design–prediction–synthesis–validation cycles. This allows hypotheses proposed by AI to be experimentally validated, with results continuously fed back into the system for iterative model improvement and optimization.
In this talk, we will demonstrate how this integrated approach enhances research productivity across various industrial use cases in materials discovery and optimization, and discuss future directions of Chemical Agentic AI.

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The rising technical demands for advanced semiconductor device manufacturing, and the industry’s ambitious net-zero commitments necessitate the development of novel etch chemistries that deliver both technical excellence and environmental sustainability. This talk will present an overview of the emerging etching chemistries developed by Air Liquide for variety-targeted applications. These innovative chemistries focus on delivering improved performance with unique technical merits to address current industry challenges. Exemplified by a novel low Global Warming Potential (GWP) designed for general dielectric etch, its synergistic integration with advanced abatement solutions, and a simplified Life Cycle Analysis (LCA) - from raw material extraction through processing, manufacturing, distribution, and use, this presentation aims to provide insights into a pathway towards more sustainable semiconductor manufacturing processes.

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As device architectures scale toward the angstrom era, metallization has emerged as one of the most critical bottlenecks to continued improvements in power and performance. Shrinking feature dimensions increase resistance, heighten reliability risks, and add complexity in interconnects and contacts. At these scales, traditional approaches which uniformly affect all wafer surfaces are increasingly ineffective. They rely heavily on lithography to define placement, and struggle to address tighter geometries and growing sensitivity to interfaces. Selective deposition is a solution which enables atomicscale control of where metals grow, placing material only where it is needed, without relying on patterning. It also enables monocrystalline metal growth, eliminating grain boundaries to minimize contact resistance.

This presentation will highlight how Applied Materials’ integrated materials solutions are enabling multiple inflections through area selective metallization. Selective Cobalt Capping technology encapsulates copper interconnects, improving adhesion, suppressing electromigration, and extending copper reliability to advanced nodes. Applied’s Selective Barrier eliminates a highly resistive interface at the interface of interconnect wiring. For contact fill, Applied developed Selective Tungsten (W) as a liner-less gap-fill solution that eliminates traditional liner/barrier layers and enables bottomup, seamfree metal fill. Finally, we introduce Selective Molybdenum (Mo) deposition that carries lowresistivity contact scaling forward as dimensions approach the fundamental scaling limits of W. Applied’s state-of-the-art atomic layer deposition tool for molybdenum delivers bottom-up, single-crystal Mo growth, enabling the next generation of contact scaling.

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Cleaning processes originally relied on wet etch based patterning. However, dry etching now performs the majority of the patterning work, so wet etching is no longer needed for most pattern creation steps. Consequently, the focus of cleaning has shifted from patterning to the removal of contaminants. To obtain a clean surface, we must eliminate unwanted contaminants without any side effects such as pattern damage, collapse, material loss, or corrosion.
However, in the current era of 3 D structured devices such as V NAND, GAA, and 3 D DRAM, lateral wet etching is essential for patterning 3 D devices, and the proportion of wet etching in cleaning processes is increasing. Additionally, different kinds of selectivity such as concentration selectivity and area selectivity, have become important, in addition to conventional material selectivity. Sometimes we have to remove a film uniformly even though there are seams and voids. In addition, pattern loading has become a critical factor in lateral removal processes. We must solve these loading issues to achieve better performance and yield.
From time to time we must use more flexible, multi step processes; therefore, premixed chemistry is not enough to meet our purpose. Due to the flexibility of dry (gas phase) cleaning, the portion of dry cleaning has been increasing sharply. Area selectivity has also become another challenge. We must etch without corner rounding or climbing, and we want to perform anisotropic etching.
Conversely, based on the generic clean roadmap, high aspect ratio cleaning and low consumption cleaning will remain continuous challenges. Super critical CO2 drying is a solution for pattern collapse in HAR patterns, yet a dryer that is milder than CO2 but better than conventional IPA dryer technology is still required. In terms of chemical reduction, the puddle process may be a solution, but some side effects related to temperature consistency and cleanliness differences due to fluid dynamics must be resolved before implementation.

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본 강의는 반도체 분야의 기초 이해를 목표로 하며, 크게 세 가지 핵심 주제로 구성되어 있다.

1) 반도체 기술 및 산업의 발전 과정을 살펴보고, 이를 바탕으로 현재 반도체 산업의 동향과 중요성을 이해하는 것을 목표로 한다.
2) 반도체 재료의 특성과 반도체 소자의 기본적인 동작 원리를 정성적인 관점에서 이해하는 것을 목표로 한다.
3) 반도체 소자 및 IC 칩 제작에 필요한 주요 단위공정기술 및 집적공정기술의 기초에 대해 이해하는 것을 목표로 한다.

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본 강의는 최신 반도체 제조 기술 중 하나인 3나노미터(3nm)급 공정을 기반으로 한 GAA(Gate-All-Around) MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor) 소자에 대한 구조와 동작 이해를 중점으로 다룹니다. 최근 발표된 연구 기술과 논문을 기반으로 반도체 소자의 연구 동향과 기술적인 이슈를 탐구합니다.

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본 강의에서는 Silicon ingot을 성장시키는 growing process와 Wafer의 형상 제어를 목적으로 하는 shaping process, Wafer 표면의 경면을 목적으로 평탄도를 제어하는 Polishing proces, 마지막으로 청정도 제어 목적의 Cleaning process를 포함하는 wafering process 설명을 통해 전반적인 wafer 제조 process에 대한 이해를 높일 예정이다.
또한 Silicon wafer의 metrology 를 Crystal, Surface, Electrical, Contamination 관점에서 설명함으로써 분석 방법 및 영역에 대한 포괄적 이해를 돕고자 한다.

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반도체 소자의 고속화 및 고집적화에 따라 다층배선구조에 있어서 배선층수의 증가와 패턴의 미세화에 대한 요구가 여전히 높다. CMP (Chemical Mechanical Planarization)는 미세패턴을 형성하기 위한 노광장치의 Depth of focus가 작아지면서 광역평탄화를 실현하기 위해 도입되었는데, 현재는 STI, Cu damascene 등 패턴형성 및 TSV 같은 packaging 쪽에도 사용되고 있어 그 중요성이 나날이 커지고 있다. Cleaning은 Particle, Metal, Polymer, Organic contamination, Native Oxide 및 Damaged Layer 등과 같은 Wafer 상의 원하지 않는 물질들을 제거하여, Device Yield를 감소시키는 노광 불량, Gate Oxide 불량, 전기적 접촉저항 불량 및 배선의 단락 등과 같은 결함을 제어하는 모든 공정을 의미한다. 패턴 미세화에 따라 난이 도가 급격히 증대되어 패턴손상 없는 새로운 세정공정개발의 필요성이 커지고 있다. 본 강 의에서는 CMP 및 cleaning의 기본 개념과 필수 구성요소를 장비와 재료 측면에서 살펴보고, 차세대 CMP 및 cleaning의 방향에 대해서 다루고자 한다.

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리소그래피(Lithography, 노광 공정)는 반도체 공정에서 회로의 ‘밑그림’을 웨이퍼에 정밀하게 그려 넣는 핵심 단계이다. 설계된 회로 패턴은 스캐너 등의 노광 장비를 통해 웨이퍼 표면에 도포된 감광제(포토레지스트) 위에 빛으로 전사되며, 이 과정의 반복을 통해 실제 반도체 회로를 형성한다. 본 강의에서는 리소그래피 공정의 기본 원리와 역사적 발전, 광원 및 렌즈 시스템, 포토레지스트의 종류와 특성, 노광 장비의 구성과 작동 원리, 그리고 해상도 향상을 위한 최신 기술까지 단계별로 설명한다. 이를 통해 리소그래피 공정의 핵심 개념을 이해하고, 미래 반도체 기술 발전에 필요한 기초 역량을 갖추는 데 기여할 수 있다.

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Doping 및 Diffusion 공정 (Implantation, Annealing, Oxidation, Nitridation, Deposition)은 지난 50 년간 핵심 반도체 제조 기술로서 고성능 소자 제작을 위해 사용되어 왔으며, 현재도 새로운 기술로서 진화하고 있다. 본 중급 과정에서는 각 공정에 대한 기초, 심화, 응용에서부터 차세대 공정까지 폭넓게 다룰 예정이다. Ion implantation 에서는 목적, 장단점, Hardware 구성, Process 응용, Doping profile, Channeling, Defect, TED, 신기술에 대해 소개한다. Annealing 에서는 목적, 종류 (sRTA, fRTP, LSA), Activation, Junction 조절, 장비 종류 및 Hardware 구성에 대해 소개한다. Oxidation 에서는 산화 Kinetics, 산화막 물성, Defect/Charge, 다양한 산화 방식(Dry, Wet, Plasma, Radical)과 장비에 대한 소개가 이루어진다. Nitridation 에서는 방식(Thermal, Plasma)에 따른 N profile, 소자 특성, 장비에 대해 다룬다. Deposition (LPCVD, ALD) 에서는 증착 Kinetics, 분류 방식, 다양한 박막 종류 (Poly Si, SiO2, Si3N4, SiON, Metal) 및 공정 응용에 대해 소개할 예정이다.

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최근 반도체 집적도가 증가하면서 Patterning 공정에 대한 난이도 역시 급격히 증가하고 있다. 특히 2D 및 3D Patterning을 모두 담당하는 Etching 공정의 중요성은 그 어느 때 보다도 높아진 상황이다. 본 강의에서는 Etching process를 구현하는데 필수적인 Plasma physics 및 engineering을 소개하고, 기본적인 Etching mechanism 및 주요 물질 별 Etching chemistry, 차세대 Etching 기술 트렌드 등을 조망하고자 한다.

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최근 반도체 산업은 초고속, 저전력, 고집적 등 메모리 소자의 성능을 향상시키기 위한 방향으로 연구 개발을 활발하게 추진하고 있습니다. 반도체 소자를 실제로 구현하고 제품으로 만들어내는 반도체 제조 공정은 이를 위해 새로운 기술 및 소재의 개발과 함께 기존 소자의 구조를 개선하는 등의 다양한 연구를 병행하고 있습니다.
본 강의는 Thin Film 공정의 기본 개념 및 용어와 함께 해당 공정의 증착 방법, 각 증착 물질의 특징과 장단점에 대해 이해하고 이를 바탕으로 특히, Dielectric, Metal 물질 별 응용 사례를 파악하여 Thin Film 공정에 대한 이해도를 높이는 과정입니다.

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반도체 회로 패턴이 점점 미세화 되면서 반도체 소자를 형성하기 위한 공정 진행 방법 또한 점점 어려워지고 복잡해지고 있다. 특히 반도체 제품의 Pattern Shrinkage, SPT/DPT 공정의 확대, 구조변화 등에 따라 다양한 형태의 불량들이 발생할 뿐만 아니라 불량 Size 또한 더욱더 작아지고 있어 제조 공정 과정에서 발생되는 문제점을 빠르고 정확하게 확인할 수 있는 In-line 계측 기술에 대한 요구가 높아지고 있다. 본 강의에서는 반도체 제조 공정 과정에서 사용되는 Metrology & Inspection 분야의 중요 장치들의 기본적인 작동 원리와 종류를 알아보고, 각 장비들의 활용 사례를 통하여 공정상의 문제점 파악과 해결 방법들을 살펴보고, 향후 신제품 대응에 필요한 차세대 Metrology & Inspection Tools의 개발 Trend에 대해서 다루고자 한다.

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반도체 패키지란 일반적으로 전공정에서 실리콘에 형성된 회로를 외부로 연결해주고 보호해줄 수 있도록 하는 후공정 단계이다. 반도체가 발전 할수록 더욱 빠르게 동작하고, 다양한 분야에 활용함으로 인해 열방출에 대한 성능과 고 신뢰성을 요구하게 되었다. 최근 AI의 성장을 위해서는 패키지의 발전도 같이 이루어져야 한다는 목소리가 커지고 있다. 이제는 패키지가 외부로 전기적, 기계적 연결하고 열방출, 반도체의 보호에 대한 역할 뿐만 아니라 반도체 회로 소형화의 한계로 패키지에 고속화, 다기능화, 저전력 등의 기능을 요구 하고 있다. 이에 발맞추어 실리콘 관통 적극을 이용하여 HBM(High Band width) 메모리가 등장하고 있으며 이종 칩을 연결하여 새로운 시스템 인 패키지가 만들어지고 있기도 하다. 점점 패키지의 역할이 중요해지고 있는 시점에 맞추어 본 강의에서는 반도체 패키지가 어떤 역할을 하는지 앞으로의 Trend를 소개하고, Substrate를 이용한 일반적인 반도체 패키지 공정과 새로운 시장을 위해 적용되고 있는 flip chip 및 웨이퍼 레벨 패키지 기술 실리콘 관통 전극(TSV)를 이용한 3D 적층 패키지 기술과 이종 칩 연결 기술에 대해 소개하고자 한다.

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