AI is fueling unprecedented growth and accelerating demand for advanced devices. Its requirements for performance, power, and area scaling are driving memory and logic devices toward 3D architectures.
At the heart of this 3D transformation, processing steps must enable taller, perpendicular structures as well as smaller features. Meeting these requirements calls for new deposition and etch capabilities that did not exist before, leading to breakthroughs needed in areas such as atomic-level deposition and etch (ALD and ALE), high-aspect-ratio processing, dry resist EUV patterning, and the adoption of new materials like molybdenum (Mo). As a result, the transition to 3D devices will drive increased intensity of deposition and etch processing.
This presentation will explore how deposition and etch are critical to unlocking the future of 3D devices, with increasing velocity required to meet the demands of AI-driven innovation.

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As the semiconductor industry navigates the challenges of dimensional and functional scaling in the artificial intelligence (AI) era, advanced materials science has emerged as a critical enabler for performance enhancement. Modern AI-centric architectures demand the integration of increasingly complex system-on-chip (SoC) designs with non-traditional material systems.
This work details a high-throughput methodology for the rapid down-selection and optimization of multi-element thin films, ensuring alignment with both physical and electrical key performance indicators (KPIs). Utilizing combinatorial physical vapor deposition (PVD) in conjunction with unit-cell electrical test vehicles, we systematically screen an expansive elemental compositional space to identify optimal candidates. Advanced machine learning (ML) algorithms are integrated into each phase of the development lifecycle—spanning precursor synthesis, process optimization, and heterogeneous integration—to satisfy the rigorous specifications of emerging device applications. The synergy between integrated materials engineering and AI-driven informatics significantly reduces the temporal gap between material discovery and device-level implementation.

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Chemical and materials research faces increasing demands for data-driven automation and autonomous research systems due to vast exploration spaces and complex decision-making processes. In this talk, we introduce EXAONE Discovery as a Chemical Agentic AI system and present an integrated research framework designed to accelerate scientific discovery.
EXAONE Discovery is an agent-based system that tightly integrates property prediction, molecular generation, synthesis prediction, and literature/data extraction. Based on given research objectives, the system accumulates relevant data, generates candidate molecules using model-driven approaches, evaluates their properties, and derives feasible synthetic routes—automating the end-to-end discovery pipeline. Furthermore, it is designed to enable a closed-loop research paradigm by interfacing with autonomous laboratories, connecting design–prediction–synthesis–validation cycles. This allows hypotheses proposed by AI to be experimentally validated, with results continuously fed back into the system for iterative model improvement and optimization.
In this talk, we will demonstrate how this integrated approach enhances research productivity across various industrial use cases in materials discovery and optimization, and discuss future directions of Chemical Agentic AI.

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The rising technical demands for advanced semiconductor device manufacturing, and the industry’s ambitious net-zero commitments necessitate the development of novel etch chemistries that deliver both technical excellence and environmental sustainability. This talk will present an overview of the emerging etching chemistries developed by Air Liquide for variety-targeted applications. These innovative chemistries focus on delivering improved performance with unique technical merits to address current industry challenges. Exemplified by a novel low Global Warming Potential (GWP) designed for general dielectric etch, its synergistic integration with advanced abatement solutions, and a simplified Life Cycle Analysis (LCA) - from raw material extraction through processing, manufacturing, distribution, and use, this presentation aims to provide insights into a pathway towards more sustainable semiconductor manufacturing processes.

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As device architectures scale toward the angstrom era, metallization has emerged as one of the most critical bottlenecks to continued improvements in power and performance. Shrinking feature dimensions increase resistance, heighten reliability risks, and add complexity in interconnects and contacts. At these scales, traditional approaches which uniformly affect all wafer surfaces are increasingly ineffective. They rely heavily on lithography to define placement, and struggle to address tighter geometries and growing sensitivity to interfaces. Selective deposition is a solution which enables atomicscale control of where metals grow, placing material only where it is needed, without relying on patterning. It also enables monocrystalline metal growth, eliminating grain boundaries to minimize contact resistance.

This presentation will highlight how Applied Materials’ integrated materials solutions are enabling multiple inflections through area selective metallization. Selective Cobalt Capping technology encapsulates copper interconnects, improving adhesion, suppressing electromigration, and extending copper reliability to advanced nodes. Applied’s Selective Barrier eliminates a highly resistive interface at the interface of interconnect wiring. For contact fill, Applied developed Selective Tungsten (W) as a liner-less gap-fill solution that eliminates traditional liner/barrier layers and enables bottomup, seamfree metal fill. Finally, we introduce Selective Molybdenum (Mo) deposition that carries lowresistivity contact scaling forward as dimensions approach the fundamental scaling limits of W. Applied’s state-of-the-art atomic layer deposition tool for molybdenum delivers bottom-up, single-crystal Mo growth, enabling the next generation of contact scaling.

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Cleaning processes originally relied on wet etch based patterning. However, dry etching now performs the majority of the patterning work, so wet etching is no longer needed for most pattern creation steps. Consequently, the focus of cleaning has shifted from patterning to the removal of contaminants. To obtain a clean surface, we must eliminate unwanted contaminants without any side effects such as pattern damage, collapse, material loss, or corrosion.
However, in the current era of 3 D structured devices such as V NAND, GAA, and 3 D DRAM, lateral wet etching is essential for patterning 3 D devices, and the proportion of wet etching in cleaning processes is increasing. Additionally, different kinds of selectivity such as concentration selectivity and area selectivity, have become important, in addition to conventional material selectivity. Sometimes we have to remove a film uniformly even though there are seams and voids. In addition, pattern loading has become a critical factor in lateral removal processes. We must solve these loading issues to achieve better performance and yield.
From time to time we must use more flexible, multi step processes; therefore, premixed chemistry is not enough to meet our purpose. Due to the flexibility of dry (gas phase) cleaning, the portion of dry cleaning has been increasing sharply. Area selectivity has also become another challenge. We must etch without corner rounding or climbing, and we want to perform anisotropic etching.
Conversely, based on the generic clean roadmap, high aspect ratio cleaning and low consumption cleaning will remain continuous challenges. Super critical CO2 drying is a solution for pattern collapse in HAR patterns, yet a dryer that is milder than CO2 but better than conventional IPA dryer technology is still required. In terms of chemical reduction, the puddle process may be a solution, but some side effects related to temperature consistency and cleanliness differences due to fluid dynamics must be resolved before implementation.

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As the era of lateral shrink is coming to a cliff, the need for looking at the remaining axis is uprising - the Z-axis. For DRAM, the introduction of vertical channel is very near, and even the introduction of a full 3D-DRAM is not far away. Fortunately, we have experience of VNAND, which could tell us many things about the difficulties following the 3D stacking structures. Starting from the change in the material we've gone through regarding the conversion of planar to vertical NAND, prospection of the material innovation for 3D-DRAM will be shared. The introduction of materials for the construction of deep holes and lengthy lines will be addressed. Also, needs for innovative sacrificial and auxiliary materials will be presented.

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As DRAM scaling approaches fundamental limits, advanced architectures such as 3D DRAM and 4F² DRAM have emerged as promising solutions. The industry initially anticipated the adoption of these technologies around the 1d to 0a nm nodes; however, they remain in development, with mass production likely postponed until the 0b node. For instance, current 3D DRAM samples feature 8–12 layers, while the target is approximately 90 layers. Recent advancements include 3D DRAM with vertical bit-line architecture, demonstrating improved on-current performance and gate control through 5-layered cell stacks utilizing Si/SiGe sacrificial layers and hybrid bonding. Meanwhile, novel 4F² DRAM transistor structures exhibit enhanced operational margins and mitigate floating body effects through dual-gate designs. Additionally, a 3D stackable DRAM architecture with horizontally stacked transistors has been proposed to address challenges such as gate-induced drain leakage (GIDL) and row hammer effects, supported by both experimental and simulation results. Collectively, these innovations underscore the potential of 3D and 4F² DRAM as next-generation solutions to overcome scaling bottlenecks and meet the growing demand for high-density, low-power memory.

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The development of semiconductor technology can be continuously achieved through the collaboration of materials, processes, devices, and systems, and 3D devices and 3D integration process technologies will be essential in the future. From this perspective, the structural change of semiconductor transistors is expected to evolve from the current Gate-All-Around FET (GAAFET) to a new Complementary FET (CFET) device. This structural change of semiconductor devices requires new materials and process technologies. Various technologies are required, such as Monolithic or Sequential 3D integration, Si/Si or Si/Non-Si substrates, new low-resistivity metals, CMP, Bonding, TSV, and Back-Side Power Network Delivery (BSPDN). In this presentation, we will examine the technological trends from the materials and process perspectives for the development of CFET device technology.

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For the past six decades, hazardous gas hydrides like GeH4, Si2H6, and B2H6 have been essential to the semiconductor industry. Their high reactivity, strong reducing power, and ability to grow high-quality, carbon-free layers have made them vital for applications ranging from Si and SiGe epitaxy to tungsten metallization. In recent years, new applications and integration schemes have emerged, demanding higher-performance hydride sources for low-temperature Chemical Vapor Deposition (CVD) and epitaxy. This increased global demand drives production investments, despite the challenges of handling, facilitating, and logistics constraints such as limited shelf-life, pyrophoricity, and toxicity. In this talk, we will provide an overview of the current gaseous hydrides landscape and its challenges. We will discuss how the gas industry can ensure the semiconductor industry's continued safe access to these critical materials through enhanced stewardship, optimized supply chains, packaging, and manufacturing techniques. Furthermore, we will provide insights into technology trends towards new-generation, extra-low-temperature epitaxy and high dopant sources, and their potential use in future transistor architectures.

Emergence of artificial intelligence (AI) is predicted to drive global chip sales to ~$1 trillion revenue by 2030. This surge of AI-targeted chip demand is driving ever-increasing requirement in compute speed to >109 petaFLOPS. High-bandwidth memory (HBM) architecture is well-suited to fulfill this requirement, currently offering >1TB/s bandwidth. To continue improving HBM performance, materials engineering innovations are required in critical packaging building blocks, such as TSV and Hybrid Bonding. Solutions from equipment manufacturer standpoint were presented, in relation to TSV gapfill, low-temperature (<300˚C) hybrid bonding enablement, and bond strength consideration for higher I/O count in the future. Timely solutions to the dynamic HBM integration challenges should be seen holistically and to this end, active partnerships and collaboration across the ecosystem are encouraged.

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The semiconductor industry continues to advance, propelled by growing demand for AI-driven computing and storage technologies and diverse digital applications. However, this growth is tempered by rising economic uncertainty and escalating trade tensions, particularly due to recent U.S. tariff policies, which threaten to disrupt global supply chains. The semiconductor materials sector faces multifaceted challenges, including increasing rapid technological innovation, geopolitical volatility, large-scale capacity expansions and climate change actions. While the market remains relatively stagnant in 2024 compared to 2023, a rebound is anticipated in 2025–2026, driven by long-term demand for advanced computing and storage solutions. A shifting supplier landscape is emerging, marked by the rise of regional players—notably in China—and consolidation among multinational corporations pursuing economies of scale through mergers and acquisitions. Geopolitical pressures are driving localization and dual sourcing, which raise costs, reduce efficiency, and complicate supply chains. This talk highlights the need for a delicate balance between innovation-driven growth and the escalating operational challenges in the semiconductor materials industry.

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As the commercialization of artificial intelligence (AI) and the advancement of technologies such as high-performance computing (HPC) and deep learning (DL) progress, the need to process large amounts of data quickly has emerged. Traditional DDR and GDDR memory have limited bandwidth, so HBM, which offers higher performance, has been commercialized, driving the development of new technologies.
Compared to traditional memory chips, HBM has increased chip size and higher defectivity vulnerability due to chip stacking processes. This has led to new technical approaches for wafer defectivity control across the entire material ecosystem.
This presentation reviews the latest trends in filtration/purification technologies aimed at minimizing the impact of particles and impurities in this material ecosystem. By examining current HVM devices and next-generation HBM-related technologies, we aim to contribute to wafer defect control.

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As semiconductor manufacturers continue the vertical scaling of 3D memory devices, advanced metrology and process control strategies are becoming increasingly essential for maintaining yield and reliability. The rising aspect ratios (AR > 100) of device features present significant challenges for conformal thin-film deposition via atomic layer deposition (ALD). Ultra-thin dielectric films and multilayer stacks—widely used in 3D memory channel holes—are particularly sensitive to process variations. Even minor deviations in ALD process conditions can result in non-uniform film coverage, defect formation, or electrical performance issues, all of which are difficult to detect and monitor within high-aspect-ratio structures.
To address these challenges, Chipmetrics has developed a novel method based on lateral ultra-high-aspect-ratio test structures (PillarHall®) for ALD process development, monitoring, and tool qualification. In the PillarHall® test wafers, the aspect ratio exceeds 1000, enabling practical and non-destructive measurement of film conformality. The method offers a sensitive and scalable solution for improving ALD process qualification, benchmarking tool performance, and enhancing production stability.
This presentation will highlight recent advancements in PillarHall® technology, with a focus on its application in ALD tool qualification and ALD process window control.

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There have been lots of technical advances in the fileld of semiconductor industry for the last dacades ever since DRAM and NAND were invented and commercialized. Meanwhile, form factor was changed from 8F2 to 6F2 in DRAM, and the concept of 3D stacking was adopted in NAND flash memory. Furthermore, EUV tool has been adopted and are being successfully used to make the fine pattern in logic and DRAM as well. And also, it has been very long since ALD was taken as a new advanced depostion technology to meet the need for excellent conformality. But all these new process technologies couldn’t have been possible without the advances in process materials such as advanced photo resist, precursors, functional chemicals and CMP slurries. Recently, those process materials are beginning to open the new possibilities for the innovation of process integations, resulting in cost reduction and giving an extra performance to the process tools. In this talk, the role, the current issues and future challenges will be discussed focusing on the process materials in semiconductor industry.
Starting from photo resist, thin and etch resistant resist has been cosistantly required to suppress the pattern collapse and wiggling during the patterning process. Since the EUV was adopted in DRAM and Logic, high sensitivity EUV resist is now being intensively explored to obtain low DtS as well as good CD uniformity to make the best use of the enomoursly high-priced EUV tool in a cost effective way. For the sake of that, even metal-containing resist is also being tried for high quality patterning. Additionally, thick KrF resist is also required at 3D NAND flash memory with the increase of ON stack and especially for the new platform to be. And for the future, the new concept of PR based on small sized polymer will be worth trying and dry type developer would be also necessary to keep the pattern stable without collapse or wiggling.
With regard to the wet chemicals and CMP slurries, advanced functional chemicals are getting more and more important rather than convetnional cleaning chemicals that are used after etch and CMP process. W or Mo recess chemical in 3D NAND would be that very case. Those chemicals should assure the good uniformity in terms of recess amount in the vertical direction. Most of all etch and CMP prcesses need post cleaning steps to clean the residue, but during that, some unwanted part of the surroundings is apt unavoidably to be removed deteriorating the device proformance in the end. Therefore, special clean chemical will be also needed to minimize the unwanted film loss as well as residue removal. When it comes to the slurry, the shape of the abbrasive particles consistently has been changing from sharp and pointed to the rounded one by adopting colloidal synthesis to suppress the scratch during CMP. The size of the abrasive particle tends to get smaller but slurry is required to make up the decreased removal rate by properly regulating components within slurry. With the change of material to be polished such as Mo or Carbon, new slurry for those new materials will be a new drive for CMP related materials.
Precursor and some functional gases have been contributing to the quality improvement or deposition modication of functional materials such as high-k materials in DRAM. As always, there should be more technical areas, in which precursor and gas will be able to play an important role in ASD(Areal Selective Deposition) or ALE(Atomic Layer Etching) process.
Since process materials needs to be considered from the operation of FAB line unlike the process tools, it must be managed well from the aspect of consistent quality control and risk management of supply chain and safety. In the past, process material used to play a simple and supporting role in the process and tools as well. But now, it is becoming a time for the process materials to play a more active role in cost reduction and risk management as well as providing technology for semiconductor industry. Especially, new process materials are also required to meet the needs for low carbon emission during the process and safety issues from the using PFAS containg materials that are hazardous to human body. Way of doing work needs to be also changed in a way that R&D activities have to be shifted to the earlier engagement. And plus, the collaboration between device maker and process material supplier shoud be much closer and earlier than before so that the developed materials can be successfully adopted at a targeted process and a tool for it. As the material supply chain has been becoming very unstable since corona pandemic and US-China trade conflict, it needs to be managed with a good predictability and balance as well in order for consistent and stable supply in case of unexpected issues at a supply chain.

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The rapid growth of AI, big data, IoT, and 5/6G communication necessitates the sophisticated computing power and efficiency of semiconductor devices, driving demand for various components such as HPC, GPU, ASIC, FPGA, and HBM. Semiconductor device and equipment industries are also challenging various new technologies to accommodate such diversifying applications and proceed with sustainable development in the era of AI and ICT.
According to the roadmap over the next 10 years, semiconductor technologies are expected to develop into the scaling technologies to further extend the existing Moore's Law and hybrid device technologies that integrate legacy nodes and advanced nodes into one. Therefore, in this presentation, we will look at the latest logic technology roadmap and introduce new process technologies to implement it.

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Materials innovation within the Semiconductor industry has been a driving force since the planar 2D MOSFET to the current 3D gate-all-around (GAA) transistor architectures and will continue its criticality as we embark on 500-layer flash memory designs and Angstrom level critical interconnect dimensions. To achieve these once incomprehensible levels of lateral and vertical scaling, device design engineers and manufacturers are increasingly relying on disruptive materials innovation to enable the density and performance gains required at each successive technology node. As the performance requirements for the most advanced devices become more challenging, materials have shown to have an increased contribution to device performance over scaling and design. This has led to a greater portion of the periodic table being incorporated into semiconductor processing.

The integration of new materials, such as novel photoresists, interconnect metals & alloys, ultra-pure polymers, chemically modified polymer membranes, and formulated chemicals, into the chip fabrication increases process complexity and makes yield ramps more challenging. With more process steps in the overall device build, speed to yield and process integrity are more critical than ever to achieve technology qualification schedules. This presentation will focus on Entegris’ approach to materials innovation, the integration of these novel materials coupled with co-optimized solutions enabling industry technology roadmaps and yield requirements while preserving integrity of delivery and process control.

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Resonac has started Packaging Solution Center as new R&D center to propose one-stop solution for customers in 2018 and established the co-creative packaging evaluation platform “JOINT2” with leading companies to accelerate the development of advanced materials, equipment and substrates for 2.xD and 3D package in October, 2021.

2.xD and 3D packages require to connect chips and components in high density, therefore, both wiring pitch and vertical interconnect dimension must be finer and finer. At the same time, in order to achieve better performance, more and more chips are integrated together and thus the package size is increasing. To meet these requirement, we are developing fine vertical/lateral interconnect technology and the study of fabrication and reliability for the extremely large 2.5D advanced package.

The presentation will cover the significance and strengths of JOINT2, and updates on research and development.

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EUV lithography infrastructure has become the critical element of semiconductor industry to enable the device scaling down. It consists of not only light source, optical system but also masks, photoresist. The EUV stochastic effects present challenges to optimizing EUV resist resolution, line edge roughness, and sensitivity simultaneously. To overcome these challenges, Lam introduced the new dry resist combined with the new dry development technology.

Lam’s EUV dry resist, coupled with ASML’s EUV scanners and Lam’s holistic patterning solutions, will extend the patterning roadmap (Moore’s Law) for the next 10 years and beyond by offering a high-resolution, high-fidelity, defectivity-free, and greener solution for ≤32nm pitch L/S, and ≤40nm pitch pillar and contact hole EUV patterning in the fab. EUV dry resist technology also has been validated demonstrating superior dose-to-defectivity for <32nm pitch L/S, well suited for logic applications. Lam’s EUV dry resist is uniquely suited for future HiNA EUV patterning thanks to robust resist thickness scaling while maintaining high etch selectivity and high contrast.

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As demand for chips surge, the semiconductor industry is struggling to reduce its environmental footprint. While the environmental impacts of semiconductor (and electronic products that depend on them) have mostly been liked to ‘manufacturing’ and ‘use’ phases of products which consume a significant amount of water and energy, the attention is shifting to the 'material extraction’ and ‘end-of-use’ phases of products following concerns over the e-waste issue. In this presentation, I will focus on the latest findings of the global e-waste challenge, what this means from the materials perspective, and its implications to product design and manufacturing. I will also introduce SK hynix's strategy and targets towards improving the circularity of products, and our partnership with customers/vendors to achieve a common goal.

Fluorine compounds exhibit exceptional physical properties that set them apart from other organic materials. Consequently, they have been utilized as core materials to enhance the functionality, performance, and value of products across various key industries including electrical and electronics, semiconductors, displays, and automobiles.
However, on March 22nd of last year, the European Chemicals Agency (ECHA) issued a report imposing restrictions on the usage of over 10,000 types of per- and polyfluoroalkyl substances (PFASs) across all industries, sparking significant upheaval within the sector.
In this presentation, we will learn in detail about the definition of PFAS, and the content, progress, and schedule of PFAS regulations in Europe and the United States, and contemplate the direction of future technology development.

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As semiconductors become more advanced and the fabrication processing conditions more extreme, the essentiality of a sustainable and secure fluorinated material supply chain plays a vital role in the future of semiconductor manufacturing. The principles of developing this supply chain are directly aligned to support the sustainability and emission roadmaps of the semiconductor industry. Syensqo will introduce the following content:
1) Priorities when Specifying Materials for a Sustainable Supply Chain
2) The Key to Sustainability - Application Segmentation
3) Case Studies

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Growing scientific evidences suggest that certain per- and polyfluoroalkyl substances (PFAS) pose global environmental and health risks. In response, global governments are contemplating measures to limit the use of these chemicals in various industries. However, specific types of PFAS are indispensable and no substitutes are currently available for most chip manufacturing applications in the semiconductor industry. Aligned with the objective of Safer and Sustainable by Design, DuPont has launched a comprehensive program to reduce PFAS usage in photoresist and associated lithography materials. In this presentation, we will provide an overview of DuPont's innovative initiatives and technical challenges encountered in this endeavor.

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Solvents are used extensively in the semiconductor manufacturing process. Solvents are estimated to be responsible for around 7% of the Scope 3 emissions of the semiconductor industry. The typical solvents that are used are produced from fossil resources and with that not in line with net zero ambitions. For more than 20 years Corbion has been supplying biobased ethyl lactate to the semiconductor industry under it’s brand name PURASOLV® ELECT, meeting the stringent requirements of the industry. Typical applications are photoresist for i/g-line / KrF / ArF / EUV, RRC, Edge bead removal and as thinner. Biobased ethyl lactate is sustainable and safe by design: it is produced from renewable resources, non-toxic and safe to workers, biodegradable and offers a significant carbon footprint reduction compared to incumbent solvents. Switching to biobased ethyl lactate thus enables more sustainable semiconductor manufacturing.

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The technological advancement of semiconductor materials is a key factor along with the technological advancement of the process. And recently, the importance of Advanced PKG is increasing, and SK Hynix has achieved the result of improving product performance by developing MR-MUF materials. This proves the importance of materials. In the future, there are more packaging challenges for high-speed memory products such as HBM, and I plan to announce Need for material development to satisfy them.

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The number of transistors in semiconductor chip has been increased twice every two years for more than 50 years, following the famous Moore’s Law and somehow, it was taken to be granted. In reality, it was a big accomplishment with an unimaginable amount of efforts and collaborations, including the development of new materials.

New material has been developed and introduced to improve the performance and capacity of electronic devices through smaller design rules. New Photo Resists (PR) for higher resolution with smaller defects and higher uniformity were developed. And Precursors were also developed to meet the process challenges for the smaller design rules, such as higher aspect ratios. High etch selective Etchant and CMP Slurry with low scratch were requested. And the requirements in new materials are getting tougher and stronger with the evolution of AI, which needs more computing power than ever. Even materials that has never been expected in industry and has been studied only in academia are being actively considered.

Even the worse, the surrounding situation for material development and manufacturing is getting tougher. Environmental regulations are getting tighter. Gases with high global warming potential were begun to be replaced. Recently, EU announced banning PFAS materials in near future and US raised bars for PFAS materials. And carbon zero policy is coming to us slowly but firmly.

In this talk, we will discuss the current status and future direction of material research. We will discuss the development directions to improve the performance of devices and to consider environmental regulations. And we will discuss the virtue of working together as a big one-team to overcome all the obstacles mentioned above in the world of extreme technology.

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