10:00 am -10:50 am 반도체 산업 현황
10:50 am - 11:05 am Break
11:05 am - 12:15 am 반도체 소자 구조 및 동작 원리
12:15 am - 2:00 pm Lunch
2:00 pm - 3:10 pm 실리콘 칩 제작 공정
3:10 pm - 3:25 pm Break
3:25 pm - 4:35 pm 실리콘 칩 제작 공정

※ 연사정보

최근 반도체 산업은 초고속, 저전력, 고집적 등 메모리 소자의 성능을 향상시키기 위한 방향으로 연구 개발을 활발하게 추진하고 있습니다. 반도체 소자를 실제로 구현하고 제품으로 만들어 내는 반도체 제조 공정은 웨이퍼 제조부터 패키징까지의 모든 단계를 포함하며 기술 혁신을 통한 반도체 칩 성능의 극대화를 위해 새로운 소재 도입 및 장비 개발과 함께 기존 소자의 구조를 개선하는 등의 다양한 방면으로 연구를 병행하고 있습니다.
본 강의는 먼저 반도체 산업의 특징 및 글로벌 반도체 산업 생태계 동향 파악과 함께 웨이퍼 위에 회로를 새기는 과정인 전공정 (Front-end Process), 완성된 칩을 보호하고 테스트하는 과정인 후공정 (Back-end Process) 을 포함한 반도체 제조 공정의 전반적인 내용에 대해 간단하게 살펴보고 이후 Thin Film 공정의 기본 개념 및 용어와 함께 해당 공정의 증착 방법, 각 증착 물질의 특징과 장단점에 대해 이해하고 이를 바탕으로 특히, Dielectric, Metal 물질별 응용 사례를 파악하여 Thin Film 공정에 대한 이해도를 높이는 과정입니다.

※ 연사정보

최근 반도체 집적도가 증가하면서 Patterning 공정에 대한 난이도 역시 급격히 증가하고 있다. 특히 2D 및 3D Patterning을 모두 담당하는 Etching 공정의 중요성은 그 어느 때 보다도 높아진 상황이다.
본 강의에서는 Etching process를 구현하는데 필수적인 Plasma physics 및 engineering을 소개하고, Etching mechanism 및 주요 물질 별 Etching chemistry, 차세대 Etching 기술 트렌드 등을 조망하고자 한다.

※ 연사정보

Rapidly evolving progress of AI and HPC has significantly increased computational and memory needs such as higher performance, lower power consumption, and wider memory bandwidth with reduced latency. An end application of AI/HPC comes down to Datacenter construction. Meeting the challenge of delivering this processing power in the datacenter requires systematic innovation from the device to the datacenter level. It starts with integrating highly optimized, domain-specific accelerators which should be integrated into advanced 2.5D and 3.5D packaging that minimize losses and power for high-speed communication while taking advantage of workload power management. AI computing introduces significant challenges for energy consumption and thermal management. Power delivery network is crucial for CPU, GPU and NPU power and performance of which solution can be DTC, IVR, mtal-insulator-metal (MIM) capacitor and thin film inductor, backside power rail, etc..  While Moore’s law has continued to yield transistor scaling necessary for these applications, the ever growing demand from models for AI training and inference pushes Si scaling in conjunction with the advent of advanced interconnects via disaggregation and reaggregation of chips in advanced packaging.  
We will discuss with examples and the challenges of utilizing packaging elements to their full potential and discuss how co-optimization is crucial to achieving the best results for any given set of system requirements and constraints.

※ 연사정보

※ 연사정보

Advanced semiconductor packaging is now central to enabling continued performance scaling as conventional transistor scaling slows. This seminar introduces cutting-edge trends in advanced packaging, including 2.5D and 3D integration, fan-out wafer-level packaging, chiplet-based architectures, and glass interposers for optical I/O in AI and HPC systems. These technologies offer enhanced performance, form factor reduction, and system-level integration capabilities critical for future computing platforms.
Leveraging prior industry experience, this talk highlights real-world applications and challenges in designing and qualifying advanced SoC packages. Examples include CoWoS-based AI chip packaging, hybrid bonding techniques, and thermal design optimization for high-power systems.
As packaging structures become increasingly complex, reliability emerges as a critical bottleneck. The seminar explores major failure mechanisms such as thermal-mechanical fatigue, electromigration, interfacial delamination, and Through Glass Via (TGV) degradation. Reliability analysis methods including FEA-based stress modeling, time-to-failure prediction, and advanced failure diagnostics will be introduced.
By combining packaging innovation with reliability engineering, the talk aims to provide a comprehensive perspective on the technological and practical issues that must be addressed to enable robust, high-performance semiconductor systems in the AI and data-driven era.

※ 연사정보

As the AI era progresses, semiconductor devices are increasingly adopting 3D architectures to boost performance and power efficiency. At the same time, system technology co-optimization (STCO) is advancing through the use of chiplets and advanced wafer-level packaging. As the industry integrates more chips into chiplets, the size of interposers continues to grow. However, wafer-level packaging faces limitations in accommodating large interposers due to the constraints of 300mm wafer shapes and temporary carriers.
This trend is driving a shift toward panel-level packaging (PLP) to support higher packaging unit counts. Despite its potential, PLP still faces significant challenges—particularly in terms of process development and process control.
This paper explores the technical trends in panel-level packaging, focusing on the current challenges and potential solutions related to process control.

※ 연사정보

Abstract - Heterogenous integration and advanced packaging is behind the technology that is enabling today’s AI and high-performance computing. This is done through complex architecture that utilizes platforms including microbumps, through silicon vias (TSV), high density fanout and hybrid bonding (HB). The integration of chiplets using any combination of these technologies is allowing the industry to extend the Moore’s law and overcome limitations of the Von Neumann architecture. Hybrid bonding is an especially appealing technology that helps improve power and performance (higher I/O density), as well as thermal management. Sub-10 ㎛pitch die-to-wafer (D2W) HB is already in production1) for 3DIC and the industry working on HB technology for High Bandwidth Memory as well2). However, there are continuous challenges for D2W that require new innovation in both processing and metrology & inspection (M&I), and also unique challenges for both logic and memory applications specific to its integration. The presentation will discuss how logic and memory HB technologies are different and what process and M&I technologies are needed to facilitate HVM of the HB technology across different applications. Process challenges including low temperature bonding, die warpage management and dicing will be discussed, while M&I challenges include the transition to e-beam technology for HB enablement.

1) R. Agarwal et al., “3D Packaging for Heterogeneous Integration”, IEEE ECTC, July 2022
2) Lee et al., “A Study on D2W Cu Bonding Technology for HBM Multi-die Stacking”, IEEE ECTC, May 2024

※연사정보

The ongoing miniaturization and increased integration density in electronic circuit systems, particularly in advanced technologies such as DRAMs for Through-Silicon Via (TSV) and High Bandwidth Memory (HBM), have elevated thermal management to a critical challenge in microelectronic packaging. The functional performance, operational lifespan, and reliability of electronic devices fundamentally depend on efficient thermal dissipation. As power densities escalate, enhancing the thermal conductivity of EMCs has become imperative for effective heat removal from increasingly complex electronic components. Consequently, research efforts focused on developing epoxy resins with superior thermal conductivity and identifying appropriate high-conductivity fillers represent the most viable approaches to addressing thermal management challenges in contemporary microelectronic systems.
Recently, we have successfully developed a high-performance epoxy molding compound (EMC) that solves critical thermal management challenges in advanced microelectronic packaging applications. Not only do these compounds provide extremely safe protection of integrated circuits from moisture, mobile ion contaminants and adverse environmental conditions, including temperature fluctuations, humidity and mechanical stress, but the enhanced thermal and mechanical properties of EMC formulations address the heat dissipation requirements of advanced technologies such as small electronic circuit systems, especially TSV and HBM applications.

※ 연사정보