Namsung Kim is a Senior Director in the Integrated Module Solutions (IMS) Group at Applied Materials. He is currently responsible for managing customer engagement programs, driving business growth, and leading cross-functional teams (various Business Units) to deliver the integrated materials/modules-base product solutions across leading-edge CMOS Logic and Memory technologies. Prior to this role, he has successfully led & accomplished the definition of CMOS Logic technology roadmap, its inflections of future technology nodes and delivered multiple product development paths by validating innovative pathway solutions.

He joined Applied Materials, Inc., USA in 2015, bringing over 20 years of semiconductor device/process integration experiences (various engineering/management positions) from both CMOS Logic (GlobalFoundries/IBM alliance in USA and SSMC in Singapore) and Memory (SK-Hynix, previously LG Semi., in Korea) industries. He earned a MS in electrical and computer engineering from the National University of Singapore. He has authored and co-authored more than 50 technical publications and holds over 40 patents in the field of advanced logic (FinFETs and GAA devices) and memory technologies.

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Dr. Jeongdong Choe is a Senior Technical Fellow at TechInsights. He has over 30 years of experience in the semiconductor industry, R&D, and reverse engineering on DRAM, NAND/NOR FLASH, SRAM/Logic, and Emerging Memory. He worked for SK Hynix and Samsung Electronics for over 20 years. He joined TechInsights and has been focusing on technology analysis of semiconductor processes, materials, devices, and architecture. He has written many articles on memory technology including roadmaps, technology trends, and detailed comparisons.

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Jean-Marc Girard Ph.D. is CTO and Sr. VP of Manufacturing Technologies at Air Liquide Advanced Materials (ALAM), and an Air Liquid Group Fellow. He has 25 years of experience of R&D and product development management in the field of semiconductor materials and process technology in Europe, Japan and the US, and is one of the founders and was the global director of ALOHA™ from 2005 to 2010 (Air Liquide’s original CVD/ALD materials product line).
Within ALAM, Jean-Marc globally manages the Research and Development for deposition & advanced dry etching materials, oversees strategic engagements and collaborations with leading customers and equipment companies, and supervises the Intellectual Property generation and portfolio management. Since 2021, Jean-Marc’s role has expanded to leading packaging and manufacturing technology developments efforts.

“Byunghee Kim” has been Sr. Technologist in Lam Research since 2017.

Prior to joining Lam Research, “Kim” was director position for Samsung Electronics. During his 23 years at Samsung Electronics, “Kim” spent time doing module development, including gate, contact and BEOL.

“Kim” received a bachelor’s degree in chemistry from Yonsei Univ., Seoul, Korea and a master’s degree in MSE from Seoul Nat’l Univ., Seoul, Korea.

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Jeongsik Kim, received a MS degree in Organic Synthetic Chemistry from Sogang University(Korean) in 2006 and then joined Dongjin Semichem. He had developed the patterning process materials such as bottom antireflective coating(BARC), spin on hardmask(SOH), photoresist materials in Semiconductor Materials Business Division since 2006. In 2013, he had joined the advanced lithography program of IMEC(Belgium) as Dongjin Semichem assignee and researched the ArF immersion patterning and defectivity for two years. Currently, he is in charge of developing EUV photoresist at Dongjin Semichem.

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Sung Ho Kim is the Head of Specialty Gases Marketing, Clean & Etch platform, Merck KGaA, Darmstadt, Germany where he drives the execution of product marketing strategy to meet with industry’s dry etch and chamber clean gas technical and commercial needs, and leads product life cycle management and NPI (New product introduction) initiatives to help customers to advance its dry etch and chamber clean process performance. He is a proven business leader with more than 20 years of experience in the semiconductor materials industry, with a wide range of leadership experience in product marketing, product management, and technical/engineering expertise. He is based in Pangyo, Korea. Sung-Ho received a bachelor's degree in Chemical Engineering from Seoul National University.

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Won-Seob Cho, Ph.D. presently serves as the Head of the BASF Electronics Materials R&D Center in Suwon, Korea. In this esteemed position, he is responsible for leading research teams dedicated to the development of advanced wet chemical solutions, such as advanced cleaning and electroplating methods. He boasts over 20 years of research and development experience, particularly in the formulation and electrochemical screening of solutions.

Prior to joining BASF a decade ago, He served as a Principal Researcher at Samsung SDI and Samsung Fine Chemicals, where he specialized in developing planarization and electroplating solutions. Notably, his research interests have recently expanded to encompass the Advanced Package field.

Won-Seob Cho holds a distinguished Ph.D. in Chemistry from the University of Texas at Austin and has also served as a postdoctoral fellow in Supramolecular Chemistry at the University of California at Los Angeles, further solidifying his scientific expertise.

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Dr. Nam, Sang Uk is conducting various studies on the ICT (semiconductor, display) industry based on economics at the KIET (Korea Institute of Industrial Research), a national research institute.

Since joining the KIET in 2018, he has participated in various studies on ICT industry policies such as Japanese export regulations, development strategy of material, parts and equipment, global value chain, and digital transformation.

In the field of carbon neutrality, he participated in major reports such as the semiconductor and display industry's carbon neutral promotion strategy and policy tasks, and the impact of RE100 on Korea's major export industries.

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Mark Thirsk is Managing Partner of Linx Consulting, a leading management and strategic consulting company for electronic materials.

Mark Thirsk has experience spanning many materials and processes in wafer fabrication, combined with economic and business forecasting, strategic planning, technical marketing and M&A experience. Mark has worked in materials and equipment development, marketing, applications support, and production, as well as having expertise in business incubation, strategic development, and M&A. Mark is well placed to bring clarity and insight to market analysis from both a technical and commercial perspective. Additionally, Mark has been active in SEMI since 1999, volunteering in industry advocacy, education, and recruiting.

Mark has worked in the UK, Germany, Belgium, and the USA. Mark holds an Honours B.Sc. in Metallurgy and Materials Science from Birmingham University and an MBA

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E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer. She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, the Sidney J. Stein International Award in 2019, and she is an IMAPS Fellow. She is a member of MEPTEC, SMTA, and SEMI. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.

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Sam-Jong Choi, Ph.D. has been working as a material expert at Samsung Electronics Semiconductor for over 30 years. He joined the company in 1991 and has been responsible as a material engineer and expert for Memory Manufacturing Technology Center in Samsung Electronics by now. He obtained a Ph.D in Electronic, Computer, and Telecommunication Engineering from Hanyang University in 2020.
In 2019, he was promoted to Group Leader for Memory Material Technology Group, where he oversaw the development of new materials and quality management for Samsung Electronics. In 2020, Samjong Choi was appointed as an Corporate VP at Samsung Electronics, where he continues to play a key role in the field of semiconductor material.
As an experienced engineer and leader, he brings a wealth of knowledge and expertise to his current role, making Samsung Electronics stay at the forefront of technological innovation in the global semiconductor material industry.

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[AI가 이끄는 사회 변화와 반도체 산업 MI기술의 방향성]
본 강의는 1부와 2부로 구성되었고, 1부에서는 AI가 이끄는 사회변화를 다양한 관점에서 살펴보고, 이 변화속에서 반도체 기술이 갖는 의미와 중요성을 함께 고민해보고자 합니다. 이후에 2부에서는 반도체 연구 및 제조 분야에서 Metrology & Inspection(MI) 기술의 역할과 기술 개발 방향성에 대한 종합적인 이해 돕고자 합니다. 마무리로, 제조현장의 엔지니어가 갖추어야 할 역량에 대해서 강사의 사견을 표하고 강의를 마무리하고자 합니다.

1부
• 사회변화 : 인공지능 출현 후 사회변화
• AI 기술혁명을 이끄는 반도체

2부
• 반도체Metrology & Inspection 기술 역할
• 반도체 산업 MI기술의 방향성

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본 Tutorial 강의에서는 반도체 제조 공정에서의 계측(Metrology) 기본 원리와 활용 방법을 체계적으로 설명합니다. 광학, e-Beam(CD-SEM, HV-SEM) 등 주요 계측 장비의 측정 원리와 특성, 선택 기준을 다룹니다. 또한 Pattern Profile 분석, Overlay 분석 등 주요 계측 응용 사례를 소개하여, 전반적인 반도체 계측 공정에 대한 이해도를 높입니다. 또한, 차세대 반도체 공정에서 준비해야 할 차세대 미래 계측 과제와 대응 전략을 해설합니다.

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본 강의에서는 반도체 제조 공정 중 발생하는 주요 불량을 제어하는 검사(Inspection) 기술의 기초 개념과 핵심 원리를 소개합니다. 광학 및 전자빔(e-Beam) 검사의 기본 메커니즘과 개발 환경에서의 적용 사례를 중심으로 결함 검출의 기초를 알기 쉽게 설명합니다. 또한 기존 기술의 발전 흐름과 현재 소자 개발 단계에서 마주한 기술적 과제를 짚어보며, 검사 공정의 전반적인 맥락을 이해하도록 돕습니다. 나아가 차세대 공정으로의 진화에 따른 미래 검사 기술의 방향성을 조망하며, 반도체 검사 분야의 기본기를 다지는 입문 계기를 제공합니다.

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최근 소재 개발과 EUV 리소그래피 기술의 비약적인 발전에 따라 고집적 메모리 양산용 소자 기술은 현저한 발전을 이루어 왔다. 그럼에도 불구하고 박막 내 물리적·화학적 결함, 소재의 본질적 물성, 그리고 박막 간 계면 특성은 아직 충분히 규명되지 않았다. 본 과정에서는 박막의 물리적 특성과 더불어 계면 특성에 대한 심층적 고찰의 필요성을 제시한다. 더 나아가 다양한 소자 통합 및 메모리 제조 공정 전반에서 전기적·물리적 결함을 민감하게 분석할 수 있는 신규 특성 평가 기법을 소개하고자 한다.

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• Semiconductor History and Market
• Integrated Circuit Design and TEST
• ATE Test System Architecture
• AI Semiconductor Trend and Challenges of Test

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LED driver, PMIC, BMIC, IGBT, Silicon Carbide등 Mobile, Automotive향 Power application의 전반적인 구조 및 동작을 설명하고 test에 필요한 기본적인 요소를 이해하도록 한다. 또한 이를 측정하기 위한 ATE hardware및 device의 신뢰도를 최대화할 test 방법 및 환경에 대해 설명한다.

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반도체 검사 공정의 핵심 설비중의 하나인 TESTER 성능을 손실 없이 사용하기 위해서는 Test Socket, DIB(Device Interface Board), Probe Card 등의 interface 제품의 올바른 선택과 사용은 대단히 중요하며 특히 underkill일 때의 품질 issue 또는 overkill일 때의 양품 손실 등 품질과 비용측면에서 매우 큰 영향을 끼치는 핵심 구성품이라 할 수 있다. 기초적인 기능과 동작을 이해하고 사용자 입장에서의 올바른 제품의 선택을 위해 고려해야 할 사항들과 개발자 입장에서 설계와 개발 시 우선하여 관심을 가져야 할 부분을 살펴본다.

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- Test Introduction
- Wafer Test Process Overview
- Package Test Process Overview
- Memory Test Hardware System Introduction

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5G, 자율주행, 클라우드 컴퓨팅 등 때문에 반도체에 대해 고속, 고용량, 저전력 특성의 요구가 더욱 더 커지고 있다. 지금까지는 이러한 요구를 반도체 공정의 스케일 다운을 통해서 만족시킬 수 있었지만, 최근 Chat GPT 등 인공 지능의 활용이 늘어나면서 데이터의 사용량은 급증하게 됨에 따라 반도체의 스케일 다운만으로는 이러한 요구 사항을 만족시키기 어렵고, 적층, 이종 접합 등의 첨단 반도체 패키지 기술이 필요하게 되었다. 본 과정에서는 웨이퍼 레벨 패키지(WLP, wafer level package), 적층(stack) 패키지, 시스템 인 패키지(SiP, System in Package) 등의 첨단 패키지 기술 트렌드에 대해서 심도 있게 고찰하려 한다. 특히 TSV 적층 기술과 웨이퍼 레벨 패키지 기술을 이용한 HBM(High Bandwidth Memory)의 의미와 공정을 이야기하고, HBM을 이용한 시스템 인 패키지기술을 설명하려 한다. 그리고, 칩릿(Chiplet)을 이용한 시스템 인 패키지 기술의 필요성과 이를 위한 핵심 기술에 대해서도 정리하려 한다.

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AI 시대의 도래와 함께 LLM과 같은 초거대 AI 모델의 학습 및 추론을 위한 High Performance Computing(HPC)의 중요성이 빠르게 증가하고 있다. 그러나 기존의 미세공정 scaling만으로는 연산 성능 향상에 한계가 발생하고 있으며, 메모리 대역폭, 전력 효율, 칩 간 데이터 전송과 같은 문제가 핵심 과제로 부상하고 있다. 이러한 한계를 극복하기 위한 핵심 기술 중 하나가 바로 Advanced Packaging 기술이다. 본 강의에서는 AI 시대 HPC 시스템이 요구하는 성능 특성과 시스템 구조를 먼저 이해하고, 이를 가능하게 하는 다양한 Advanced Packaging 기술들을 체계적으로 설명하고자 한다. 먼저 2.5D/3D 패키징 기술과 TSV, silicon interposer, hybrid bonding과 같은 핵심 요소 기술을 살펴보고, GPU와 HBM을 초고속으로 연결하기 위한 최신 패키지 구조를 분석한다. 이어서 Chiplet architecture, CoWoS, Foveros, SoIC, Fan-Out Packaging(FOPLP/FOWLP)과 같은 산업 적용 사례를 소개하며, 고대역폭·저전력 구현을 위한 패키지 기술 방향을 설명하고자 한다.

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The rapid expansion of AI is fundamentally reshaping the semiconductor industry, driving unprecedented investment in AI data centers, accelerating technological transitions, and redefining competitive dynamics across the ecosystem. At the same time, growing debates around the sustainability of AI-related investments and the potential risks of an AI bubble are creating new uncertainties for industry players.

Changwook Kim, Managing Director and Partner at BCG and leader of the semiconductor practice in Korea, will present on the “AI-Driven Restructuring of the Semiconductor Industry and the Opportunities it creates.” The session will cover AI data center investment trends and outlook, the impact of AI on the memory semiconductor market, recent changes across the semiconductor ecosystem including fabless, foundry, packaging, and memory technologies, and the strategic implications and opportunities for semiconductor companies.

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AI is moving from large-scale model training toward inference and agent-based services. GPUs, HBM, and 2.5D interconnects have powered the first wave of AI acceleration, but the future is diversifying—bringing AI accelerators, CPUs, general-purpose memory, and on-die AI semiconductors into play. From a memory-centric view, the demand for massive capacity, ultra-fast speed, and wide I/O bandwidth is clear. Yet the most urgent challenge is low power. This talk will explore the current limits of DRAM core die technology in HBM and highlight new device structures designed to break through these bottlenecks. We will look at the shift beyond the traditional 1T1C DRAM cell toward oxide-semiconductor-based 2T0C architectures, advances in bonding methods, and the potential of glass substrates. We will also examine strategies for achieving low-power operation—from smarter architectures to heterogeneous integration of processors and memory—and discuss how these innovations open opportunities across devices, materials, equipment, and packaging. By framing these breakthroughs within a broader AI semiconductor technology framework, the session will provide a clear view of both the technical challenges and the strategic directions shaping the next era of global semiconductor innovation.

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AI is reshaping the semiconductor industry from both the demand side and the infrastructure side. While AI accelerators, HBM, advanced logic, and data-center infrastructure continue to drive strong growth, the broader market remains uneven, with consumer-driven segments recovering more gradually and macro uncertainty still shaping investment decisions. This presentation will review the key market forces behind the current semiconductor cycle and examine how AI demand is translating into fab investment, capacity expansion, and equipment spending.
The discussion will highlight SEMI’s latest view of global fab investment, capacity growth, and regional expansion. It will also address why the next phase of growth depends not only on headline demand, but also on qualified capacity, technology migration, packaging and test readiness. With Korea’s leadership in memory and manufacturing execution, the presentation will place Korea’s role within the broader global infrastructure buildout supporting the AI era.

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As monolithic scaling approaches the physical and economic limits of Moore’s Law, Advanced Semiconductor Packaging (ASP) has transitioned from a routine backend process to the primary driver of microelectronic innovation. Driven by an unprecedented surge in demand for Artificial Intelligence (AI), high-performance computing (HPC), and 5G infrastructure, ASP has emerged as the new strategic layer in the global technology ecosystem, reshaping hardware architecture and market competition.
Through heterogeneous integration, advanced packaging techniques—such as 2.5D/3D stacking and fan-out wafer-level packaging—bypass single-die fabrication constraints. By combining disparate, optimized chiplets into a unified system, ASP fulfills the skyrocketing commercial need for massive interconnect densities, ultra-low latencies, and extreme thermal efficiencies.
Ultimately, semiconductor leadership is no longer defined solely by front-end lithography nodes, but by the ability to architect complex, multi-die systems. Packaging has effectively become the critical differentiator, supply chain constraint, and the ultimate bottleneck for future technological supremacy.

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