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Registration Details

During Registration, you will have the option to also register for MEMS & Sensors Technical Congress (April 26-27) and the Positing, Navigation & Timing Gap Analysis Workshop (April 25).  3 Great Opportunities to Network, Learn, Share and Connect in 1 week.

CANCELLATION POLICY:

  • Substitution available anytime with written note from original registrant.
  • 75% Refund is cancelled before April 15, 2022. 
  • 50% Refund if cancelled between April 16 and date of workshop.
  • No refunds after April 28.
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Speaker Bios

Mahesh Chowdhary, Ph.D. is a Fellow and Director of Strategic Platforms & IoT Excellence Center at STMicroelectronics based in Santa Clara CA. He leads effort on development of solutions and reference designs for mobile phones, consumer electronic devices, automotive and industrial applications that utilize MEMS sensors, computing and connectivity products. His area of expertise includes AI/ML, MEMS sensors, IoT, digital transformation, and location technologies. He has been awarded 30 patents. He has spoken extensively internationally about Machine Learning, Smart Sensors, and IoT. Mahesh received PhD in Applied Science (Particle Accelerators) from the College of William & Mary in Virginia. He is also an Adjunct Professor at IIT, Delhi.

Mahaveer Jain - Mahaveer Jain is Application Principal Engineer at STMicroelectronics(Santa Clara, CA) and specializing in MEMS sensors, Algorithm, DSP, and Machine Learning . Over the course of his career, Mahaveer worked on indoor navigation, hybrid positioning , sensor calibration, and sensor fusion. His most recent work has been developing extremely low power machine learning models to run on sensors. Mahaveer received a Bachelor of Technology in Physics from IIT Delhi.

Denis Ciocca - Denis is Staff Applications Engineer at STMicroelectronics specializing in Linux OS, Linux device drivers, Android OS, and Smart sensors. He has developed a variety of solutions with MEMS sensors, a computational platform of STM32 microcontrollers and wireless connectivity solutions. Denis has received his Master’s degree in Computer Science and Engineering from the University of Pavia, Italy.

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Course Abstract:

This class will explain and demonstrate how AI/ML logic can be implemented on Edge devices such as Smart sensors. Power efficiency, latency, and bandwidth considerations are important for AI/ML implementation on Edge devices. Computing can be distributed between Edge devices and Cloud. The latest trends and applications of smart sensors in consumer electronics, automotive, and industrial use cases will be discussed.

Course Outline:

  1. AI / ML on Edge devices
    1. Why AI / ML on Edge devices?
      1. Power efficiency, latency and bandwidth considerations when executing AI / ML logic on Edge devices.
    2. Computing distribution between Edge device, gateway and Cloud.
    3. Assignment: Finite State Machine and Decision Tree applications
  2. Introduction to Inertial Sensors with AI / ML capabilities
    1. Background on inertial sensors including applications
    2. Typical performance characteristics of inertial sensors
    3. Lab: SensorTile.Box and use of custom sensors to change sensor sampling rate, filters, and other configuration. 
  3. Machine Learning Core (MLC) in Smart Sensor
    1. An introduction ML at Edge of the Edge, Smart Sensors: Latest trends Applications of Smart sensors applications in consume electronics, automotive, industrial use cases. Next generation of smart sensors.
    2. AI on the Edge and requirements of distributed intelligence system.
    3. Introduction to MLC framework
      1. Input data
      2. Filters and Feature selection
      3. Optimization
      4. Tools
    4. Rapid Prototyping with MLC: current consumption under 10 uA
    5. Lab: Motion Intensity detection using MLC. Lab conducted using AlgoBuilder tool.  
  4. Finite State Machines (FSM) in Smart Sensor
    1. Introduction to FSM
      1. Input data
      2. FSM definition and structure
      3. Conditions list
      4. Tools
    2. Rapid Prototyping using FSM:
    3. Lab: Gesture recognition using FSM. Lab conducted using AlgoBuilder Tool.

SEMI
673 South Milpitas Avenue
Milpitas, CA 95035
United States

Mahesh Chowdhary
Mahesh Chowdhary, Ph.D.
Fellow & Director of Strategic Platforms & IoT Excellence Center
STMicroelectronics
Mahaveer Jain
Mahaveer Jain
Applications Principal Engineer
STMicroelectronics
Dennis Cioccca
Denis Ciocca
Staff Applications Engineer
STMicroelectronics
MSIG

Earn CEUs and IEEE PDHs from this hands-on SEMI MSIG Master Class & Lab, where instructors will explain and demonstrate how AI/ML logic can be implemented on edge devices such as smart sensors. Attendees will build and operate their own edge device with AlgoBuilder tools in 2 lab sections of the course.

This course is designed for applications engineers wanting to learn how to add sensors to an existing or new product. Instructors are experienced STMicroelectronics engineers with many sensor design and implementations.

The course covers many topics including the importance of power efficiency, latency, and bandwidth considerations for AI/ML implementation on edge devices. Learn how computing can be distributed between the edge devices and the cloud. The latest trends and applications of smart sensors in consumer electronics, automotive, and industrial use cases will also be discussed.

Join us in person at SEMI HQ, for this hands-on learning experience. 

This course is underwritten by STMicroelectronics.

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8:30 am - 5:30 pm Off Add to Calendar Disabled America/Los_Angeles

REGISTRATION

Sold Out—Thank You for Your Interest!

 

CANCELLATION POLICY: 

Cancellations received on or before April 6, 2026 are fully refunded. After this date, only substitutions will be accepted.

Please contact Karen Popp at [email protected] for any questions. 

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Become a Sponsor

Sponsorships are tailored to meet your branding and marketing objectives. To learn about please contact: 
Shane Poblete | 1.202.847.5983 | [email protected]

View Sponsorship Opportunities for the 2026 Arizona Golf Classic

TEE IT HIGH & LET IT FLY

Perched on a mountain slope with panoramic views of the surrounding valley and Phoenix skyline, Raven Golf Club's upscale amenities rival those of America's finest private country clubs. The club boasts a beautiful clubhouse featuring a full-service golf shop with its Gary Panks/David Graham-designed championship layout as the centerpiece. 

Check the Raven Golf Club for additional course details.
 

SEMI ARIZONA CHAPTER STEM SCHOLARSHIPPURCHASE A MULLIGAN + RAFFLE TICKETS

PURCHASE MULLIGAN(s) and Raffle Tickets—SUPPORT THE SEMI ARIZONA CHAPTER STEM SCHOLARSHIP

The scholarship is awarded to a deserving University in the Arizona Region.
Raffle tickets and mulligans are $5 each, available for purchase electronically in advance or onsite. Proceeds from the sales directly fund the scholarship.
Players and non-players are welcome to support the scholarship.

To donate a raffle prize separately, please contact—Karen Popp | [email protected]


PLAYER AWARDS                                                                   

  • Closest to Pin
  • Longest Drive
  • Putting Contest
  • Best Foursome
  • Needs Most Improvement


DRESS CODE

  • Proper golf attire must be worn at all times. All players are required to wear collared shirts. Slacks, shorts, or skirts must be hemmed and in good condition. Recommended short/skirt length is mid-thigh. Tank tops, swimwear, cutoffs, gym shorts, and the like are not acceptable.
  • Raven Golf Course is a spikeless facility. Metal Spikes are not allowed on the golf course. 


HOTELS

If you are traveling from out of town, the following hotels are a short drive from the Raven Golf Course:

Raven Golf Course
3636 E Baseline Road
Phoenix, AZ 85042
United States

Thursday, May 7, 2026 | Mountain Time

6:30 am

Registration | Grab & Go Breakfast

Breakfast Sponsored by Sundt

Sundt
7:30 am

Shotgun Start

1:00 pm

Networking Lunch | Awards Presentation

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Sold Out—Thank You for Your Interest!

5th Annual SEMI Arizona Golf Classic

Join us for a morning of golf, fun, and networking at the beautiful Raven Golf Course in Phoenix, Arizona. Whether you're a beginner or a pro—enjoy friendly competition and camaraderie with your colleagues and customers. 

6:30 am - 3:00 pm Off Add to Calendar Disabled America/Phoenix
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Place your business front and center at the SEMI Northeast & Pacific Northwest Forum Webinars. 

For more information please contact:
 Lin Tso | [email protected]

U.S. Semiconductor Industry Incentive Proposals

The CHIPS Act and FABS Act propose significant new incentives for semiconductor manufacturing in the United States. Both have advanced in Congress, but the legislative process remains unfinished while other countries are pursuing and implementing additional incentives. These incentives are essential to put the U.S. on a strong footing to compete for the next wave of new semiconductor manufacturing capacity, strengthen the supply chain in the U.S. and address shortages that have impacted countless downstream industries. It is also clear that the microelectronics industry doesn't only have a supply chain problem, but a significant workforce shortfall.  Diversifying and growing the talent pipeline will be critical to meet the growing demands of the industry.

Join leaders in Congress and industry experts to discuss:

  • CHIPS Act funding – where it stands and what it means for industry  
  • The FABS Act and federal tax incentives for U.S. semiconductor manufacturing
  • Supply Chain Challenges & Opportunities
  • Critical need and initiatives for diversifying and building a robust workforce

United States

WEDNESDAY, APRIL 20, 2022 | PACIFIC TIME

9:00 am
Anne Hao
GSM Technical Strategy, SEMI Pacific Northwest Co-Chair, Intel Corporation
Intel Corporation

Welcome & Introduction

9:05 am
Kimberly Ekmark
Director, Public Policy & Advocacy
SEMI

9:10 am
Charles E.Schumer, US Senator of NY
Charles E. Schumer (Video)
U.S. Senate Majority Leader
U.S. Senator of New York

KEYNOTE 1

9:15 am
Jon Cardinal, Director of Economic Development for U.S. Senate Democratic Leader Charles E. Schumer
Jon Cardinal
Director of Economic Development
for U.S. Senate Democratic Leader Charles E. Schumer
9:40 am
U.S. Senator Ron Wyden of Oregon
Ron Wyden (Video)
U.S. Senator of Oregon

KEYNOTE 2

9:50 am
Bobby Andres, Senior Policy Adviser, U.S. Senate Finance Committee, Majority Staff
Bobby Andres
Senior Policy Adviser, U.S. Senate Finance Committee
Ron Wyden Staff
10:15 am
Joe Pasetti, SEMI
Joe Pasetti
VP Global Public Policy & Advocacy
SEMI

Introductions—Panel Moderator

Industry Panelists from TSMC, Samsung, and Intel

10:20 am
Claire Sanderson, TSMC
Claire Sanderson
Senior Director, Global Government Affairs
TSMC
10:25 am
Holly Pataki
Head of Government Relations
Samsung Semiconductor

10:30 am
Erin Adrian, Intel
Erin Adrian
Head of Competition and Economic Affairs and Global Tax Policy
Intel Corporation
10:35 am

Industry Panelists Q&A (TSMC, Samsung, Intel) - Moderated by Joe Pasetti

10:50 am
Shari Liss, SEMI Foundation
Shari Liss
Executive Director
SEMI Foundation
11:05 am
Jeff Hanan
SEMI Northeast Chair, Principle Member of the Technical Staff
Globalfoundries

Closing Remarks

Presented by
The SEMI Northeast & Pacific Northwest Chapters

 

9:00 am - 11:00 am Off Add to Calendar Disabled America/Los_Angeles 1
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Verific Design Automation, the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms, today announced Rapid Silicon, a provider of AI-enabled application-specific FPGAs based on open-source technology, is the newest licensee of its Parser Platform.
Rapid Silicon is quickly building a reputation as the leader of domain-specific, power-, performance- and area-optimized FPGAs for diverse target applications using an open-source methodology and proprietary AI technology to enable a fast and seamless design-to-silicon experience. It will use the Verific Parser Platform including SystemVerilog, VHDL and elaborators for both to serve as the front end to Rapid Silicon’s integrated design environment.

“Verific’s parser platform has the well-earned status of industry standard,” says Pierre-Emmanuel Gaillardon, CTO of Rapid Silicon. “All of the accolades about Verific are valid, a result of its robust, quality software through years of development and user experience and exceptional customer support. It’s a pleasure to work with Verific.”

“Rapid Silicon’s aims to set the standard for FPGAs and FPGA SoCs by building the largest independent AI-enabled FPGA company,” adds Michiel Ligthart, Verific’s president and COO. “We take pride in playing a role in helping to enable a fast and seamless design-to-silicon experience.”

Verific’s SystemVerilog, VHDL and universal power format (UPF) Parser Platforms are in production and development flows at semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Applications range from analysis, simulation, formal verification and synthesis to hardware emulation and virtual prototyping, in-circuit debug and design for test. Verific distributes its Parser Platforms as C++ source code and compiles on all 32- and 64-bit Unix, Linux, Mac OS and Windows operating systems.

About Verific Design Automation
Verific Design Automation is the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effective worldwide. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry since it was founded in 1999.

Engage with Verific at:
Email: [email protected]
Website: www.verific.com
LinkedIn: https://www.linkedin.com/company/verific-design-automation-inc/
Facebook: https://www.facebook.com/Verific-Design-Automation-100448363329771/

ESPOO, Finland, 17th of February 2022 – Fraunhofer Institute for Silicon Technology (ISIT) has taken PICOSUN® P-300B ALD system into use as their powder MEMS technology platform.

Fraunhofer ISIT PowderMEMS is a new innovative technology for creating three-dimensional microstructures from a multitude of materials on wafer level. The technology is based on bonding together µm-sized powder particles in a cavity with Atomic Layer Deposition (ALD). It has many advantages compared to other manufacturing techniques as it allows using much lower process temperatures compared to a traditional sintering process. The bonded porous structures are thermally and chemically resistant thus enabling their extensive post-processing in a clean room.

"The technology can be used for various applications, such as microelectronics, MEMS sensors, MEMS actuators and microfluidics. For example, it enables the integration of porous and magnetic 3D microstructures on wafer level", explains Dr. Björn Gojdka, Group Leader at Fraunhofer ISIT.

“We were looking for a solution for conformal high surface area coating of powder located in trenches. Picosun solution is a perfect fit for this need as we are also looking into scaling up the technology. We are especially happy about the tool’s hot wall reactor, versatile precursor sources and its easy maintenance”, states Dr. Thomas Lisec, Chief Scientist at Fraunhofer ISIT.

“We are excited over this new technology coming to life and all the opportunities it will bring. I am especially impressed by the potential applications for the Fraunhofer ISIT PowderMEMS as they are exceptionally diverse. I’m looking forward to continuing working closely with Fraunhofer ISIT on bringing the technology up to industrial production”, says Dr. Christoph Hossbach, General Manager of Picosun Europe GmbH.

More information:
Dr. Christoph Hossbach, General Manager, Picosun Europe GmbH
Tel. +49 1522 449 49 11
Email: [email protected]
Web: www.picosun.com

About Picosun
Picosun provides the most advanced ALD (Atomic Layer Deposition) thin film coating solutions for global industries. Picosun’s ALD solutions enable technological leap into the future, with turn-key production processes and unmatched, pioneering expertise in the field – dating back to the invention of the technology itself. Today, PICOSUN® ALD equipment are in daily manufacturing use in numerous leading industries around the world. Picosun is based in Finland, with subsidiaries in Germany, USA, Singapore, Japan, South Korea, China mainland and Taiwan, offices in India and France, and a world-wide sales and support network. Visit www.picosun.com.

About Fraunhofer ISIT
Fraunhofer ISIT in Itzehoe is one of Europe's most modern research facilities for microelectronics and microsystems technology. At the heart of the institute are the clean room facilities, large enough not only to conduct research but also to manufacture the developed microchips on an industrial scale. In close cooperation with partners from industry, 160 scientists at ISIT develop power electronics components and microsystems with fine moving structures for sensor technology and actuator technology, including the necessary packaging technology. www.isit.fraunhofer.de

Registration

This meeting is open for FOA Members Only. 

If you are interested in becoming a member, please contact Karim Somani - [email protected].

 

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Hotel Information and Airport Information

Austin Marriott South

4415 South IH-35

Austin, Texas, 78744

Austin Marriott South for 219.00 USD per night - Last Day to Book: Monday, February 02, 2026

Booking link: Book your group rate for FOA Q1 Collaborative Forum

Austin-Bergstrom International Airport
3600 Presidential Blvd
Austin, TX 78719

+

Austin Marriott South
4415 South IH-35
Austin, TX 78744
United States

10:30 am - 5:00 pm

FOA Golf Event (Tee Time Start) - Onion Creek Club

Onion Creek Club

2510 Onion Creek Parkway

Austin, TX 78747

5:00 pm - 9:00 pm

Women of FOA - Evening Dinner & Social Activity

Meeting room: Sycamore A&B

Day 1 -February 25, 2026 (times are subject to change)

8:00 am - 12:00 pm

Device Maker Morning Meeting - IDM's Only

Meeting room: Lone Star Ballroom

8:00 am - 8:30 am

Registration check-in & Gathering

8:30 am - 8:40 am
Karim Somani
SEMI

Meeting Start - Introductions, Agenda Review, Sponsor Recognition, Next Meetings

8:40 am - 9:40 am
Mark da Silva
SEMI

Open Forum Topics #1

9:40 am - 9:50 am
Rick Glasmann
MAX

Welcome Reception sponsor presentation - MAX

9:50 am - 10:30 am

Coffee Break

10:30 am - 10:40 am

Social Event sponsor presentation - INFICON

10:40 am
Mark da Silva
SEMI

Open Forum Topics #2

11:40 am - 11:50 am
Sean Tropsa
SEEQ

DM Lunch sponsor presentation - SEEQ

11:50 am - 1:00 pm

DM Lunch - IDM's Only

Lunch will be in rooms: Sycamore A&B and Bluebonnet

SEEQ

Continuation Day 1 - February 25, 2026 (times are subject to change)

12:00 pm - 6:00 pm

Exhibit Opens

Exhibits will be displayed in the foyer

1:00 pm - 6:00 pm

Session 1 - General Meeting for all FOA Members

Meeting Room: Lone Star Ballroom

1:00 pm - 1:10 pm
Mark da Silva

Welcome remarks & Updates

Removing Manufacturing Bottlenecks (Case Studies)

1:10 pm - 1:35 pm
GlobalFoundries & Semilab

Next-Generation In-Line AFM Metrology for Silicon and GaN Applications

1:35 pm - 2:00 pm
Northrop Grumman & Applied Materials

Reduction of Through-Silicon Via (TSV) Sidewall Roughness through Process Optimization in Bosch Dry Etch Process: A Collaborative Study

2:00 pm - 2:30 pm
Tosca Derrick
Baker Tilly

Industry – Tariff Updates

2:30 pm - 2:55 pm
Broadcom & Fabworx Solutions

Particles vs. Productivity: Root-Cause Solutions that Unlocked Tool Performance

2:55 pm - 3:25 pm

Coffee Break #1 – Sponsored by JST

JST

Improving Fab Efficiency (Case Study)

3:25 pm - 3:50 pm
ST Microelectronics & INFICON

From Insight to Action: Elevating Employee Efficiency with Smart Detection and Targeted Data Delivery

3:50 pm - 4:20 pm
Inna Skvortsova
Market Research Manager, SEMI’s Market Intelligence
SEMI

SEMI Market Outlook - Fab Investments, Equipment and Materials Forecast

4:20 pm - 4:50 pm
Michelle Williams-Vaden
Executive Director, SEMI Foundation
SEMI

SEMI Foundation

4:50 pm - 4:55 pm

Wrap-up & directions to Welcome Networking Reception (within the hotel)

7:00 pm - 10:00 pm

Welcome Networking Reception

Room: Sycamore A&B and Bluebonnet - Sponsored by MAX Group

MAX IEG

Day 2 - February 26 2026

8:00 am - 12:00 pm

Session 2 - General Meeting

Meeting Room: Lone Star Ballroom

8:00 am - 6:00 pm

Exhibits Open

8:00 am - 8:40 am
Karim Somani

Gathering & Welcome Remarks

Improve Long-Term Plant Viability (Case Studies)

8:40 am - 9:02 am
Qorvo & camLine

Lessons from the SPACE Deployment Project: Implementation at Qorvo Wafer Fab

9:05 am - 9:30 am
FormFactor & Olsson

Transforming a Mature Semiconductor Factory to Meet FormFactor’s Advanced Manufacturing Needs

9:30 am - 9:55 am
Polar Semiconductor & Mortenson

Polar Semiconductor Expansion and Modernization Project

9:55 am - 10:05 am
ControlSoft

Break Sponsor Presentation - ControlSoft

10:05 am - 10:35 am

Coffee Break #2 – Sponsored by ControlSoft

ControlSoft
10:35 am - 11:00 am
Analog Devices & ControlSoft

Transformation in Motion: A solution for 200mm fab AMHS upgrades

Agentic AI in Manufacturing (Case Study)

11:00 am - 11:25 am
Intel & Seeq

Intel + Seeq’s Multi-Agent Architecture to "Dim the lights" in facilities Operations

11:25 am - 11:35 am
Michelle Williams-Vaden
Executive Director, SEMI Foundation
SEMI

Thursday Lunch sponsor presentation - WFOA

11:35 am - 1:30 pm

Lunch - All Members & Speakers

Lunch will be in rooms: Sycamore A&B, Bluebonnet and Wrangler

SEMI Foundation

Continuation Day 2 - February 26, 2026

1:30 pm - 6:00 pm

Session 3 - General Meeting

Meeting room: Lone Star Ballroom

1:30 pm - 1:45 pm
Mark da Silva

SEMI Technology Community Update

Improving Fab Efficiency (Case Studies)

1:45 pm - 2:10 pm
Qorvo & Siconnex

Improved Fab Productivity

2:10 pm - 2:35 pm
FOA DM & Flexciton

Solving Fab-Level Execution Gaps with Intelligent Action Prioritization and Quantified Impact Modeling

2:35 pm - 3:05 pm
Taimur Burki
Sustainability Consultant
SEMI

Sustainability - Waste Management and how to Make $$ off of your waste

3:05 pm - 3:35 pm

Coffee Break #3

3:35 pm - 4:00 pm
Analog Devices & Seertech Solutions

Driving Fab Efficiency Through Automated Workforce Qualification and MES-Integrated OJT Enforcement

4:00 pm - 4:25 pm
M.I.T. Lincoln Laboratory & Eyelit

Enhancing Semiconductor R&D Workflow Flexibility and Traceability through Eyelit’s Manufacturing Operations Management Platform

Deployment of Digital Twins (Case Study)

4:25 pm - 4:50 pm
GlobalFoundries & D-SIMLAB Technologies

Dynamic Simulation Enabled Prescriptive Analytics for the AI-Driven Autonomous Factory of the Future

4:50 pm - 5:05 pm
Peilun Sun
Consortium Manager, SCC
SEMI

From Fab Floor to Climate Impact: How SCC Supports Manufacturing Decarbonization

5:05 pm - 5:25 pm
Karim Somani

FOA – Inside the Fab (@ Northrop Grumman Jul 28 – Jul 30) & Wrap-up

7:00 pm - 10:00 pm

FOA Annual Poker Tournament: Austin Marriott South

Poker Tournament: Sycamore A&B, Bluebonnet and Wrangler

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FOA Events - February 24, 2026

- FOA Workforce Development

Join your fellow members for the FOA Annual Collaborative Forum - live and in-person - for informative new case studies, networking, dinners, and exhibits.  

This event is for FOA Members only.  To learn more about becoming an FOA member, email [email protected]Visit the FOA web pages.

8:00 am - 10:00 pm Off Add to Calendar 2026-02-24 08:00:00 2026-02-26 22:00:00 FOA Summit (Q1 Collaborative Forum) Join your fellow members for the FOA Annual Collaborative Forum - live and in-person - for informative new case studies, networking, dinners, and exhibits.  This event is for FOA Members only.  To learn more about becoming an FOA member, email [email protected]. Visit the FOA web pages. Austin Marriott South 4415 South IH-35 Austin, TX 78744 United States SEMI.org [email protected] America/Chicago public America/Chicago
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Belgium China France Germany Ireland Italy Japan South Korea Taiwan United States Register Now https://discover.semi.org/new-gdsi-dicing-process-webinar-on-demand.html MSIG WEbinar tile Business Executive Technical Featured Speakers

About the Speaker:  Rich Boardman is a 15-year veteran of the Semiconductor industry whose expertise lies in equipment sets, process technology and consumables related to wafer or substrate dicing, grinding or polishing. Rich is a Senior Sales Engineer at GDSI, located in San Jose, California.

United States

Richard Boardman GDSI
Richard Boardman
Senior Sales Engineer
GDSI

Join us for this second webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication. 

In this session, GDSI will provide an introduction of the Stealth Dicing process, highlight the applications it is most well suited to, and share design rules and process window specifications.

The Stealth laser dicing process is a water-free, particle-free wafer singulation method.  It is particularly well suited to MEMS, Quantum, bio-sensing and Silicon Photonics to name a few use cases. Secondarily, it offers great value for multi-project wafer (MPW) applications since it allows singulation of the whole wafer in a single process step, negating the need for wafer sub-dicing and remounting.

Find out if your current wafer layout is compatible with the Stealth Dicing process, and if not, what must be done to ensure initial success with this innovative dicing technology. .

8:00 am - 9:00 am Off Add to Calendar 2022-03-30 08:00:00 2022-03-30 09:00:00 MSIG Webinar GDSI Dicing Process Join us for this second webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication.  In this session, GDSI will provide an introduction of the Stealth Dicing process, highlight the applications it is most well suited to, and share design rules and process window specifications. The Stealth laser dicing process is a water-free, particle-free wafer singulation method.  It is particularly well suited to MEMS, Quantum, bio-sensing and Silicon Photonics to name a few use cases. Secondarily, it offers great value for multi-project wafer (MPW) applications since it allows singulation of the whole wafer in a single process step, negating the need for wafer sub-dicing and remounting. Find out if your current wafer layout is compatible with the Stealth Dicing process, and if not, what must be done to ensure initial success with this innovative dicing technology. . United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles
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REGISTRATION

PRICING

  • Member: $49
  • Non-Member: $99

STUDENTS

  • Must have a valid Student ID.
  • Contact Michelle Fabiano, [email protected]
    for a student registration code.
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Valqua America

Workforce Shortage—Meeting Challenges for the Semiconductor Industry

As demand for semiconductors is increasing, foundries and other makers of chips are expanding their manufacturing capacities.  With new fabs that will bring thousands of new jobs to the US, Arizona and Texas are poised to gain many of those positions. Where will we find the talent to fill the upcoming surge of engineering and technical personnel needed to support our existing infrastructure, but also support the new fabs coming in just two-four years?  ​

The SEMI Arizona and Texas Chapters will explore this topic by hearing from Arizona and Texas-based leadership on the current market conditions, trends and outlook.  We will also hear from the semiconductor industry, experts from industry, universities/colleges and military who will provide insight into preparing a new workforce to meet our current workforce needs and needs of our not-to-distant future. ​

United States

WEDNESDAY, MAY 18, 2022 | CENTRAL TIME

12:00 pm

Welcome & Opening Remarks​

12:05 pm

The Workforce Supply Chain Crunch and Need for Workforce Development

12:20 pm
Edward Latson
Ed Latson
Founder & Executive Director
ARMA-Austin Regional Manufacturers Association

Where's the Funnel?

12:35 pm

What Makes Some Colleges Better at Building Semiconductor Talent Pipelines that Scale?

12:50 pm

Powerful Partnerships—Building a Pipeline Together

1:05 pm
Lisa Pivin, Intel Corporation
Lisa Pivin
Research Scientist
Intel Corporation

Intel Overview & Technical Opportunities

1:20 pm

It’s Time to Serve Those Who Served

1:35 pm

Preparing Warriors to Fill Key Corporate Positions

1:50 pm
Stacy Gardner
Stacy Gardner
Talent Acquisition
EMD Electronics

The Winning Side in the War for Talent—An Electronics Perspective

2:05 pm

Panel Discussion

2:25 pm

Closing Remarks

2:30 pm

Adjourn

Workforce Development

The SEMI Arizona & Texas Chapters Present
WORKFORCE SHORTAGEMeeting Challenges for the Semiconductor Industry

12:00 pm - 2:30 pm Off Add to Calendar Disabled America/Chicago 2
Event format
GDSI logo

This webinar graciously underwritten by GDSI.  Registration is free to all attendees.

GDSI logo
Belgium China France Germany Ireland Italy Japan South Korea Taiwan United States Register Now https://discover.semi.org/designing-mems-with-ge-polaris-process-webinar-on-dem… 20220302 MSIG Webinar GE Business Executive Technical Featured Speakers

About the Speaker:  Robert MacDonald is a MEMS engineer at GE’s Research. His research is focused on high performance inertial sensors. He has over 20 years of experience in the MEMS and semiconductor industries. His work has covered the product life cycle of chemical, inertial and optical sensors from design through market introduction and manufacturing.

United States

Robert MacDonald, GE Research
Robert MacDonald
MEMS Engineer
GE Research
MSIG

Join us for this first webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication.

In this first in the series, GE Research will present their new MEMS process suitable for bulk silicon motion sensors. The process aims to deliver many features of complex MEMS flows, such as wafer level packaging with through silicon vias (TSVs), with a short cycle times and low mask counts. This webinar will introduce the Polaris process within the GE Research foundry and explain how to design the process, and our model for delivering new designs.

8:00 am - 9:00 am Off Add to Calendar 2022-03-02 08:00:00 2022-03-02 09:00:00 MSIG Webinar GE Polaris Process Join us for this first webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication. In this first in the series, GE Research will present their new MEMS process suitable for bulk silicon motion sensors. The process aims to deliver many features of complex MEMS flows, such as wafer level packaging with through silicon vias (TSVs), with a short cycle times and low mask counts. This webinar will introduce the Polaris process within the GE Research foundry and explain how to design the process, and our model for delivering new designs. United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles
Event format

BENEQ, PRESS RELEASE, December 6, 2021

Beneq revolutionized ALD cluster tools for More-than-Moore device makers with the highly successful Beneq Transform® family of products. Today, Beneq broadens its product portfolio further with two new distinct solutions: the Transform® 300 and ProdigyTM.

The Beneq Transform 300 and Prodigy were each created in response to specific technology requirements in the semiconductor manufacturing sector.

“The Transform 300 is designed to meet the growing demand of emerging semiconductor applications at 300 mm for devices such as CMOS image sensors, Power Devices, Micro-OLED/LED, and Advanced Packaging, which call for a high degree of versatility,” explains Patrick Rabinzohn, Vice President, Semiconductor ALD at Beneq.

“We created Prodigy to address those market segments that need a simple solution supported by high-end technology. It inherits the ALD design and processing knowhow we at Beneq have developed over the last 15 years, packing advanced features in a simpler, targeted industrial form factor,” continues Rabinzohn.

Beneq Transform® 300
Beneq Transform 300 is the only 300 mm ALD cluster tool that combines thermal ALD (batch) and plasma ALD (single wafer) technologies to provide a highly versatile platform for IDMs and foundries. It is dedicated to advanced thin-film applications in CIS, Power, Micro-OLED/LED, Advanced Packaging and other MtM applications.

Beneq Transform 300 is a highly configurable platform that caters to multiple advanced thin-film applications ranging from gate dielectric including in high aspect ratio trenches, to anti-reflection coating, final passivation or encapsulation, Chip-Scale-Packaging and beyond.

Beneq Prodigy
Beneq Prodigy is the deal manufacturing solution for compound semiconductor including RF IC’s (GaAs/GaN/InP), LED, VCSEL, Light Detectors and for MEMS manufacturers and foundries looking to enhance device performance and reliability through an affordable stand-alone ALD batch tool. Beneq Prodigy provides best-of-breed passivation and encapsulation films across multiple wafer types and sizes.

To learn more, visit:

Beneq Transform 300:  https://beneq.com/en/products/semiconductors/transform300/

Beneq Prodigy: https://beneq.com/en/products/semiconductors/prodigy/

Further information:
Lie Luo, Head of Marketing, [email protected]

About Beneq
Beneq is the home of atomic layer deposition. In 1984, we established the world’s first industrial production using ALD. Today, we lead the market with products for R&D (TFS 200, TFS 500, R2), semiconductor device fabrication (Transform®), 3D and batch production (P400A, P800, P1500), ultra-fast spatial ALD (C2R), and roll-to-roll ALD (Genesis).  Beneq’s unique Development Service simplifies customer adoption and proof-of-concept for new ALD processes, while our Coating Service cuts down time to market by outsourcing state of the art ALD production. Our team of engineers and experts is dedicated to making ALD tools accessible for researchers.