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United States Overview of Semiconductor Mfg 8/19 Training
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Course Description

This course offers a solid foundation in semiconductor manufacturing, from basic concepts to advanced techniques, providing practical insights into the tools, processes, and technologies driving the industry.

Learning Objectives

  • Gain a comprehensive understanding of the semiconductor industry and manufacturing process, design, and ecosystem of the semiconductor industry
  • Understand the jargon, tools, and materials used in the design and fabrication of an integrated chip
  • Effectively be able to communicate semiconductor manufacturing concepts with other associates and industry professionals

Course Topics

  • Basic Electronics and Microelectronics: Definitions of essential electronic terms/concepts and introduction to microelectronics and integrated circuits
  • Process Nodes: Process nodes and their impact on device performance and cost
  • Device Physics and Transistor Operation: Principles of device operation and transistor functionality
  • Crystal Growth and Wafer Preparation: Crystal growth techniques and wafer preparation processes
  • Advanced Transistor Technologies: FDSOI, FinFETs, and Gate-All-Around (GAA) transistors and their impact on device performance
  • Circuit Design and Layout: Introduction to circuit design, layout techniques, and tools
  • Wafer Processing:
    • Mask Making and Lithography: Techniques and materials used in mask making and various lithographic methods (DUV, Immersion, EUV)
    • Clean Room Environments: Importance of clean rooms in semiconductor manufacturing and contamination issues
    • Etching and Cleaning Processes: Plasma and wet etching processes
    • Ion Implantation and Diffusion Techniques: Methods for doping and controlling diffusion in semiconductor fabrication
    • Deposition Techniques: RTP, CVD, ALD, and ALE techniques and their effect on device performance
    • Electroplating and Sputtering: Metal deposition techniques used in manufacturing
    • Packaging and Testing: Techniques such as wire bonding, die stacking, flip chip, and chiplets packaging, semiconductor testing processes
    • Metrology and Measurement Tools: Tools and methods used for precision measurement in semiconductor manufacturing
  • Semiconductor Industry Ecosystem: The major players in the industry 

Who Should Attend

Anyone interested in understanding semiconductor manufacturing, including new employees, professionals in related industries, and those seeking to broaden their knowledge of the field.

Instructor

Denny Frye 

PT International, LLC

Instructor Bio
 

Important Information

Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access the course knowledge. 

Can't find the training link day of? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders about 24 hours in an advance and an hour before with the same link. Please keep these emails on hand to access the training on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.

United States

- SEMI U

Gain a comprehensive understanding of the semiconductor industry and the integrated circuit (IC) manufacturing process. This course is designed for new personnel in the field or anyone seeking a well-rounded knowledge of the tools, materials, and terminology used in semiconductor manufacturing.

Dates and Times

August 19, 2026  8:00 - 5:00PT

August 20, 2026  8:00 - 1:30 PT

Pricing

Early Bird Special! $100 off

  • Members: $995 $895
  • Non-Members: $1,095 $995


* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected]

8:00 am - 5:00 pm Off Add to Calendar 2026-08-19 08:00:00 2026-08-20 17:00:00 Overview of Semiconductor Manufacturing (Americas) Gain a comprehensive understanding of the semiconductor industry and the integrated circuit (IC) manufacturing process. This course is designed for new personnel in the field or anyone seeking a well-rounded knowledge of the tools, materials, and terminology used in semiconductor manufacturing.Dates and TimesAugust 19, 2026  8:00 - 5:00PTAugust 20, 2026  8:00 - 1:30 PTPricingEarly Bird Special! $100 offMembers: $995 $895Non-Members: $1,095 $995* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected] United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register Now
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United States Understanding Training

Course Description

The first part of the course provides a brief overview of semiconductor design and fabrication steps, encompassing IC design techniques, all wafer processing steps, assembly, and packaging. It delves into semiconductor jargon in laypeople terms, and various substrate types such as Si, SiGe, FDSOI, GaAs, SiC, GaN. Additionally, it discusses different types of transistors like pMOS, nMOS, Bipolar, BiCMOS, CMOS, FinFets, and GAA and their evolution and what applications they are used in.
 
The second part of the course focuses on semiconductor business aspects such as silicon economics, wafer processing costs, semiconductor revenue forecasts, driving forces in the industry, top semiconductor IDMs, market competitors based on market share, OEMs, foundries, top tool vendors, and Fabless companies.  Addresses the fastest-growing semiconductor markets based on geographic locations and applications, identifies semiconductor competitors/customers, and discusses major semiconductor markets like Automotive, PC, Mobile, Memory, Wireless, Cell phones, Consumer, Gaming, AI, IoT, Digital TV, Radio, Automotive, MEMS, and Emerging Technology & Impact on Industry.

Learning Objectives

  • Understand the fundamental principles and theories semiconductor technology.
  • Communicate with other associates and understand wafer processing steps.
  • Understand semiconductor business aspects such as silicon economics, wafer processing costs, semiconductor revenue forecasts, driving forces in the industry, top semiconductor IDMs, market competitors based on market share, OEMs, foundries, top tool vendors, and Fabless companies.
  • Review the semiconductor eco-system as it relates to design and fabrication of a semiconductor device.
  • Gain knowledge of major semiconductor markets like Automotive, PC, Mobile, Memory, Wireless, Cell phones, Consumer, Gaming, AI, IoT, Automotive, MEMS, and Emerging Technology & Impact on Industry.
  • Demonstrate effective communication skills through written reports, presentations, and discussions related to semiconductor subjects.
  • Collaborate effectively with peers in group projects or discussions regarding semiconductor subjects.
  • Analyze and evaluate research literature in semiconductor technology.
  • Develop critical thinking and problem-solving skills applicable to semiconductor technology.

Who Should Attend

This course is suitable for anyone seeking a better understanding of the semiconductor industry, market leaders, terminology, business, and the semiconductor ecosystem.

Instructor

Denny Frye 

PT International, LLC

Instructor Bio
 

Testimonials 

See what course participants had to say about this course!

  • "Denny Frye knows so much about the history of the semiconductor industry that he was able to tie together many different industries and technologies that I have heard about but never knew how they were connected."
  • "Great overview of the semiconductor industry & market."
  • "This was a very detailed course on many facets of the industry, would recommend!"
  • "It was a great mix of technical and overview of the key players in the market!"
  • "Good blend on technical and commercial topics."
  • "Excellent introduction to the semiconductor world."
  • "Great session on the understanding of the semiconductor industry in a nutshell."

Important Information

Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access course knowledge. 

Can't find the training link day of? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders about 24 hours in an advance and an hour before with the same link. Please keep these emails on hand to access the trainings on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support. 

United States

SEMI U

Embark on a journey through semiconductor design, manufacturing, and business in this illuminating course. Explore IC design techniques, transistor evolution, and market dynamics. Delve into substrate types and industry economics, discovering the fastest-growing markets and key players shaping the semiconductor landscape.

Pricing

Early Bird Pricing $100 off  

  • Members: $845 $745
  • Non-Members: $945 $845

* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected]

8:00 am - 5:00 pm Off Add to Calendar 2026-08-18 08:00:00 2026-08-18 17:00:00 Understanding Semiconductor Technology and Business (Americas) Embark on a journey through semiconductor design, manufacturing, and business in this illuminating course. Explore IC design techniques, transistor evolution, and market dynamics. Delve into substrate types and industry economics, discovering the fastest-growing markets and key players shaping the semiconductor landscape.PricingEarly Bird Pricing $100 off  Members: $845 $745Non-Members: $945 $845* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected] United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register Now
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Belgium China France Germany India Ireland Italy Japan Malaysia Singapore South Korea Taiwan United States Vietnam Download the white paper Cost Benefit Calc cropped for events page Business Technical Training
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SEMI
United States

9:00 am - 9:15 pm
Peilun Sun headshot
Peilun Sun
Consortium Manager
SEMI

Setting the Stage: Industry Drivers & SCC Initiative Context

• Semiconductor Industry Decarbonization Challenges
• The Need for Quantified Business Cases
• SCC Initiative Background & Development Journey
• Vision for Industry Adoption & Collaboration

9:16 am - 9:34 am
Ben Gross Headshot
Ben Gross
Director DTMS - Sustainability
Applied Materials

SCC Cost-Benefit Calculator Overview & Walkthrough

• Tool Architecture & Methodology
• Key Inputs & Assumptions
• Understanding the Outputs & Metrics
• Live Demonstration & Example Scenario
• Current Limitations & Future Development Opportunities

9:36 am - 9:50 am
Jeff Rudnik Headshot
Jeff Rudnik
Director of Environmental Sustainability & Net Zero
ASM

Industry Use Cases & Practical Applications

• Evaluating Decarbonization Projects
• Comparing Alternative Mitigation Strategies
• Supporting Internal Investment Decisions
• Lessons Learned from Early Applications
• Opportunities for Industry Collaboration

9:51 am - 10:00 am

Open Discussion & Q&A

• Audience Questions
• Feedback & Enhancement Opportunities
• Next Steps & SCC Engagement Opportunity

Smart MFG Sustainability

The semiconductor industry is under increasing pressure to decarbonize its operations, particularly with regard to Scope 1 emissions — direct greenhouse gas emissions (GHG) from owned or controlled sources. Yet many companies face a persistent challenge: how to make a clear, consistent, and financially credible case for emissions reduction investments. To help address this need, the Semiconductor Climate Consortium (SCC) has developed a Cost-Benefit Calculator — a simplified and flexible tool that offers a structured starting point for evaluating carbon emissions reduction projects. The calculator enables users to estimate the Net Present Cost (NPC) per ton of CO₂ equivalent emissions reduction, helping to translate environmental impact into business-relevant terms.

Join SEMI's Semiconductor Climate Consortium (SCC) Scope 1 Working Group and document authors for a webinar discussing their journey creating the Cost-Benefit Calculator and outlining the use cases for this tool.  The Cost-Benefit Calculator is a functional spreadsheet with built in report creation tools. For business managers who need to calculate emissions for Scope 1.

SCC members can download the Cost Benefit Calculator Report here.

9:00 am - 10:00 am Off Add to Calendar 2026-06-16 09:00:00 2026-06-16 10:00:00 SCC: Cost Benefit Calculator Webinar The semiconductor industry is under increasing pressure to decarbonize its operations, particularly with regard to Scope 1 emissions — direct greenhouse gas emissions (GHG) from owned or controlled sources. Yet many companies face a persistent challenge: how to make a clear, consistent, and financially credible case for emissions reduction investments. To help address this need, the Semiconductor Climate Consortium (SCC) has developed a Cost-Benefit Calculator — a simplified and flexible tool that offers a structured starting point for evaluating carbon emissions reduction projects. The calculator enables users to estimate the Net Present Cost (NPC) per ton of CO₂ equivalent emissions reduction, helping to translate environmental impact into business-relevant terms.Join SEMI's Semiconductor Climate Consortium (SCC) Scope 1 Working Group and document authors for a webinar discussing their journey creating the Cost-Benefit Calculator and outlining the use cases for this tool.  The Cost-Benefit Calculator is a functional spreadsheet with built in report creation tools. For business managers who need to calculate emissions for Scope 1.SCC members can download the Cost Benefit Calculator Report here. SEMI United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register Today!
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Registration

SEMI Members: $25
Use your corporate email address during log in to be recognized as a SEMI Member.

Non-Members: $50

Students: Contact Paul Cohen ([email protected]) for student pricing.

Germany Taiwan United States ESDA Savage on Security 3 360.jpg Technical
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Designing functionally correct, high-performance, and provably secure system-on-chips (SoCs) has become a strategic imperative for modern computing infrastructure. Yet traditional design and verification methodologies are increasingly strained by escalating complexity, massive design scales, heterogeneous integration, and rapidly evolving security threats. Ensuring correctness, scalability, comprehensiveness, and adaptability across the full SoC lifecycle now exceeds the practical limits of conventional toolchains and human-centric workflows.

The emergence of large language models (LLMs) introduces a transformative opportunity for SoC design automation. Beyond natural language understanding and code generation, advanced LLMs demonstrate capabilities in architectural reasoning, specification refinement, vulnerability analysis, and design-space exploration. However, monolithic models alone are insufficient for the multidisciplinary and iterative nature of chip design. An agentic paradigm—where specialized LLM-driven agents collaborate within a coordinated framework—enables modular reasoning, cross-layer verification, security validation, and adaptive decision-making throughout the design process.

This talk will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification. The framework integrates design synthesis, threat modeling, formal reasoning, runtime monitoring strategies, and hardware–software co-verification into a cohesive workflow. Looking ahead, such agentic systems point toward a future of self-optimizing, security-aware, and continuously verified silicon—where AI-driven design environments not only accelerate innovation but also fundamentally redefine how we conceive, build, and trust next-generation microelectronic systems.

 

United States

9:00 am - 9:10 am
Warren Savage
Warren Savage
Researcher
University of Maryland Applied Research Laboratory for Intelligence and Security

Welcome and Introduction

9:10 am - 10:00 am
Mark Tehranipoor
Mark M. Tehranipoor
Distinguished Professor
Department of Electrical and Computer Engineering, University of Florida

Featured Presentation

ESD Alliance

This webinar will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification.

9:00 am - 10:00 am Off Add to Calendar 2026-09-10 09:00:00 2026-09-10 10:00:00 ESD Alliance Webinar: Gen-AI for Chip Design and Security This webinar will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification. United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register Now
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Date: May 8, 2026

Location: Drammen, Norway

Board-level and semiconductor test data are often analyzed separately, limiting correlation across the product lifecycle. Linking PCB assembly (PCBA) test results, including in-circuit and functional test, with upstream wafer, sort, and final test data remains difficult, particularly in photonics, advanced packaging, and high-density integration environments. yieldWerx and WATS announce a partnership to bridge this gap in the PCB test and semiconductor manufacturing workflows.

WATS is a test data management platform purpose-built for electronics manufacturers. It captures, standardizes, and analyzes high-volume test data from PCBA (printed circuit board assembly) production environments, including in-circuit test (ICT), functional test, and final test, giving engineers real-time visibility into board-level yield, anomalies, and quality metrics across the production line.

yieldWerx operates at the semiconductor level, connecting data across wafer fabrication, wafer sort, die, and packaged device test. Its enterprise analytics platform enables advanced yield analysis, traceability, and root cause investigation from design through silicon manufacturing.

Together, the platforms address the full product stack. This allows manufacturers to correlate PCBA-level signals with silicon quality data, improving visibility across test stages and enabling more effective analysis of yield and reliability issues.

Customer and industry benefits include:

Real-time PCBA test visibility for faster identification of yield and quality issues

Improved correlation between board-level test results and upstream chip or wafer data

Reduced time spent reconciling data across disconnected systems

Earlier detection of cross-stage patterns impacting yield and reliability

Faster root cause analysis spanning silicon, assembly, and board-level test

Better alignment between electronics manufacturing and semiconductor supply chain

The combined solution supports open architectures, APIs, and flexible deployment models, enabling integration without large-scale system changes.

About yieldWerx

yieldWerx is an enterprise analytics platform connecting data across the semiconductor product lifecycle, from design and wafer fabrication through wafer sort, die, and packaged device test, enabling advanced yield analysis, traceability, and data-driven decision-making across cloud, on-premises, and hybrid environments.

About WATS

WATS is a test data management and analytics platform developed by Virinco, built to collect, standardize, and analyze data from electronics manufacturing test systems. It provides real-time visibility into board-level performance across ICT, functional test, and final test operations, helping engineers monitor yield, detect anomalies, and improve quality at high volume.

Statements from Leadership
"We are excited to partner with yieldWerx. Our customers manufacture complex electronics where board-level test data alone only tells part of the story. By connecting PCBA production test data with yieldWerx's upstream semiconductor intelligence, we can give them a more complete picture of their product quality and yield." -- Tom Lomsdalen, CEO, Wats

“Our customers have been asking for a unified view that links semiconductor yield data with downstream electronics test results, and this partnership delivers exactly that. Together, yieldWerx and WATS empower engineering teams to move faster on root cause analysis, reduce escapes, and make smarter decisions across the entire product lifecycle.” -- Aftkhar Aslam, CEO, yieldWerx

For further information, please visit https://www.yieldWerx.com or https://www.Wats.com/.

Semiconductor industry leader takes the helm to accelerate Beneq’s next phase of growth in atomic layer deposition

Espoo, Finland, 8 May, 2026 – Beneq Oy, the home of atomic layer deposition (ALD), today announced the appointment of Dr. Jason Harrison as Chief Executive Officer. Dr. Harrison succeeds Dr. Tommi Vainio and will lead Beneq into its next phase of growth across semiconductor, optical, and emerging technology markets.

A Strategic Leadership Transition
Beneq enters its next phase of growth from a position of strong commercial momentum. Recent milestones include the qualification of the Beneq Transform® cluster tool for volume production of GaN power and RF filter devices; the introduction of Beneq Transmute™ and Beneq Transform® XP, both engineered for high-volume manufacturing (HVM) of specialty semiconductors; growing adoption of the P-Series for coating critical chamber parts in advanced node devices; and selection of the C2R™ for AR waveguide production in next-generation XR optics.

Against this backdrop, the Board of Directors has determined that the time is right to align executive leadership with the company's evolving strategic priorities. As part of this transition, Dr. Tommi Vainio has decided to step down as CEO to pursue other opportunities. The Board of Directors extends its sincere thanks to Tommi, whose leadership advanced Beneq's technology platform, strengthened its market position in thin film deposition, and guided the company through important stages of its development.

A Proven Leader for a Scaling ALD Business
Dr. Harrison brings extensive global experience across the semiconductor and advanced technology sectors. He holds a Ph.D. in Quantum Chemistry and has built a distinguished career spanning device manufacturing, process development, and equipment solutions, with senior leadership roles at Intel, Lam Research, Veeco, and Applied Materials covering research and development, new product introduction, global account management, and business unit leadership. This combination of technical depth and commercial acumen positions him to scale Beneq’s commercial execution and growth across its global customer base.

Looking Ahead
Under Jason’s leadership, Beneq will accelerate strategic execution across its expanding portfolio, deepen customer engagement across North America, Asia, and Europe, and continue investing in innovative ALD solutions from R&D to HVM to deliver long-term value to customers, employees, and stakeholders.

Dr. Patrick Rabinzohn, Member of the Board of Directors, Beneq, said: “Jason brings the technical depth, the business and account management experience, and the global perspective Beneq needs at this stage of its growth. His academic background and compelling track record across the semiconductor industry positions Jason to build on the momentum the company generated especially.”

Dr. Jason Harrison, Chief Executive Officer, Beneq, added: “Beneq has a strong technology foundation, a talented team, and a growing pipeline of customers in some of the most important markets in semiconductors and optics. I look forward to working with the team to accelerate execution and deliver on the trust our customers place in us.”

About Beneq
Beneq pioneered industrial production of Atomic Layer Deposition (ALD) with the introduction of the first commercial ALD equipment in 1984. Today, Beneq advances ALD adoption and validation with a portfolio that includes the Beneq Transform®, Transform XP, Transform 300, and Transmute™ for specialty semiconductor device fabrication; TFS 200 and TFS 500 for R&D; the P400A, P800, and P1500 batch systems for coating critical semiconductor chamber components and complex part geometries; and spatial ALD platforms such as the C2R™ and roll-to-roll processing equipment. Headquartered in Espoo, Finland, Beneq enables ALD integration from lab to fab for semiconductors, optics, and functional coatings.

Press Contacts
Lie Luo
Head of Marketing
[email protected]

ROSENHEIM, Germany / KUALA LUMPUR, 5 May 2026 — esmo group (esmo), a leading global full-service systems integrator, developer, and supplier of advanced automation solutions for the semiconductor test industry, today announces the debut of its X-change Cart. A dedicated, semi-automated Device Interface Board (DIB) exchange system that enables a complete load board changeover by a single operator in under one minute, the X-change Cart addresses the safety, efficiency, and reliability challenges associated with manual board handling on the semiconductor test floor.

In high-mix semiconductor test environments, load board changeovers are a frequent and operationally significant activity. The reliance on manual handling has long presented challenges around changeover time, operator safety, and the risk of damage to high-value boards.

“Across test floors, we kept seeing the same pattern,” said Josef Weinberger, Head of Business Unit, esmo semicon. “Board changeovers were slow, physically demanding, and too dependent on individual technique. In tight spaces, that's where mistakes happen and time is lost. That observation drove us to build a dedicated solution that makes changeovers fast, repeatable, and manageable by a single operator in under a minute.”

Engineered for the Modern Test Floor

The X-change Cart removes the physical demands and variability of manual board handling from the equation entirely. Through a structured, HMI-controlled process, a single operator can lock, rotate, and transfer a board to the tester within a minute. The ability to carry two boards in a single trip makes that timescale achievable in practice. Thoughtful design details, including a ±180° rotation at the locking mechanism and a ±90° tower swivel, address the real-world constraints of a busy test floor.

Broad compatibility with leading ATE platforms (e.g. Teradyne, Advantest, SPEA and more) facilitates integration into existing multi-vendor environments without reconfiguration, allowing OSATs and IDMs to realise multiple benefits without disruption to their current setup.

For facilities with longer-term automation objectives, an optional configuration allows the interface tower to be mounted onto a customized AGV or AMR, providing a practical upgrade path toward autonomous test floor operations. The modular design further allows additional features to be incorporated as operational requirements evolve.

Weinberger added, “Reliability in production comes down to the details. The gripper head is engineered to perform consistently under real production conditions, with ESD-safe construction ensuring the board is protected at every point of contact. That level of engineering discipline is what makes the difference on a real production floor.”

X-change Cart Key Features

  • Modular DIB exchange system for reliable, error-free board loading and unloading
  • One-person operation — complete board change in under one minute
  • Transports two load boards simultaneously for rapid exchange
  • Full multi-axis rotation: ±180° at locking mechanism | ±180° Y-axis | ±90° Z-axis
  • Compatible with leading ATE platforms — Teradyne, Advantest, SPEA and more
  • Interfaces with test head, prober, DIB-loader, storage rack, and maintenance workbench
  • Tower swivels ±90° for use in narrow corridors and constrained test floor layouts
  • Integrated Human-Machine Interface (HMI), sensor detection, safety hand-brake, and modular battery
  • Optional: fully automated configuration mountable on AGV or AMR

The X-change Cart will be available for live demonstration at the esmo booth throughout SEMICON Southeast Asia 2026. Visit esmo at Booth 2145, Hall 8, Level 2, MITEC Kuala Lumpur from 5–7 May 2026, or contact [email protected] to arrange a meeting or request further information.

United States AI Techniques in Semiconductor MFG Business Executive Technical

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Milpitas, CA 95035

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SEMI HQ
673 S Milpitas Blvd.
Milpitas, CA 95035
United States

Morning, Day 1: August 5th, 2026

9:00 am - 10:30 am
Surya Kalidindi
Multiscale

Emergent AI/ML Tools for Semiconductor Manufacturing Technology Optimization

Semiconductor manufacturing faces a broad set of complex challenges addressed through Yield Management Systems (YMS), Fault Detection and Classification (FDC), Run-to-Run (R2R) control, Design of Experiments (DOE), and Statistical Process Control (SPC). Existing machine learning approaches are predominantly scoped to individual process steps or short loops, leaving full-traveler analysis — essential for informed tool decisions such as hold, parameter adjustment, and recipe modification — largely unaddressed. Bespoke, step-specific models do not generalize across process nodes or design variants, and manually configuring analytical workflows for each new use case is time-intensive and error-prone as technology nodes diversify. General-purpose coding agents built on large language models (LLMs) partially close this gap by automating workflow generation, but they lack the semiconductor-specific domain knowledge required for robust, production-grade solutions: open-source ML packages carry no fab context, and proprietary data curation and signal-processing conventions are rarely captured in public training corpora.

This session shows how a fab-aware agentic approach closes that gap, focusing on three use cases: YMS, FDC, and Process DOE. It opens with a technical primer built on a common pipeline — preprocessing and feature reduction, uncertainty-aware imputation, regime-aware modeling (physics and virtual-metrology priors when data is scarce, data-driven as it grows), and interpretable attribution rather than black-box scores — instantiated differently across the three, with emphasis throughout on when a result can be trusted. YMS downselects high-dimensional metrology, imputes sparse measurements, and trains a tuned regressor ensemble (GPR, gradient-boosted trees, neural nets), with feature attribution (SHAP) mapped to process step and tool. FDC aligns traces, then layers univariate control limits (SPC) with multivariate anomaly detection (PCA, Hotelling T², MEWMA), per-sensor attribution, and alarm-budgeted limits that transfer across chambers. Process DOE designs experiments, fits uncertainty-aware surrogates (Gaussian processes), reduces dimensionality (PCA), and selects runs sequentially (single- and multi-objective Bayesian optimization). Attendees then see these techniques operationalized live by a domain-specific agentic platform and work directly with the agents on curated datasets.

By the end, attendees will understand how problem formulation, data characteristics, and method selection shape outcomes, and what distinguishes a domain-aware agentic workflow from a general-purpose coding agent. The session is interactive by design — participant choices steer the live analysis, and attendee input shapes how these capabilities evolve.

10:30 am - 11:00 am
Maryia Kurdina
AI R&D Group Leader
TEL and AI Design (TTAD)

Real-Time Equipment Health Monitoring Using Gaussian Process Regression on Sensor Signals

Will present a real-time health monitoring method for semiconductor equipment using multi-sensor time-series signals. From a small set of baseline runs (typically 5–20), Gaussian Process Regression is used to learn expected sensor behavior and associated confidence bands over repeatable operating segments. At runtime, deviations from these bands are aggregated into health scores per sensor and segment to identify abnormal behavior early. The system automatically reports anomalies and raises warnings to support proactive maintenance and reduce unplanned downtime and quality risk. To address the O(N^3) training cost of standard GPR, we use a split-training approach that achieves linear scaling, keeping computation practical for production use.​

11:00 am - 11:20 am

Break

11:20 am - 12:20 pm
Viraj Modak, Aditi Gautam, Saira Qureshi
Nvidia

Predict Before Failure: A Predictive Maintenance Blueprint with NV-Tesseract and NeMoClaw

Semiconductor fabs generate high-volume, multivariate sensor telemetry from process tools, ambient monitoring systems, sub-fab equipment, etc. Scheduling maintenance operations depends on more than just reacting to alarms/alerts: teams need to forecast how equipment will behave and detect abnormal trajectories/baseline shifts before failures occur.​
​
This session introduces an open Predictive Maintenance Blueprint that embeds NV-Tesseract as the core time series AI component. The pipeline performs multivariate forecasting on equipment sensor data, then runs diffusion-based anomaly detection on the forecasted window to flag emerging degradation patterns. ​

The blueprint is packaged as a reusable, deployable workflow with Hugging Face weight retrieval, configurable sensor channels, and structured outputs for downstream automation.​

We extend this blueprint with NVIDIA NeMoClaw, treating predictive maintenance as an always-on agent workflow: an autonomous agent ingests sensor streams, invokes the NV-Tesseract pipeline, interprets anomaly scores, and produces operator-ready summaries and recommended actions under OpenShell runtime guardrails. ​

Together, this shows how foundational time series models and agent orchestration can be coupled to build a production-style Predictive Maintenance stack for semiconductor operations.​

What the Audience Will Learn​:
Predictive maintenance is shifting from threshold-based SCADA alarms to forecast-then-detect workflows that catch drift earlier on multivariate equipment signatures.​

Foundational time series models (like NV-Tesseract) are increasingly deployed as components inside larger agent systems, not as standalone notebooks.​

Semiconductor and industrial teams are adopting blueprint + agent patterns (similar to NeMoClaw deployments in EDA, simulation, and factory ops) to move from prototype to governed, repeatable workflows.​

Practical lessons: multivariate sensor alignment matters; model weights and configs should be versioned and auto-retrieved; anomaly outputs must be explainable enough for maintenance engineers to trust and act on.​

Architecture takeaways:​
When to use multivariate forecasting vs. single-signal monitoring.​

Why diffusion-based anomaly detection fits correlated, high-dimensional fab sensor data better than univariate reconstruction approaches.​

How NeMoClaw can orchestrate the pipeline: data ingest → inference → thresholding → alert routing → human-in-the-loop review.

12:20 pm - 1:30 pm

Lunch

1:30 pm - 2:00 pm
Sean Tropsa & Kyle Clark
SEEQ

Practical Agentic AI at Scale for Manufacturing: Lessons Learned from Large-Scale Deployments​

Agentic AI is nearing mainstream adoption, yet many organizations still lack a clear strategy for deployments at scale. In order to bring LLM capabilities to manufacturing, companies need to go beyond what mainstream AI suppliers can deliver; they need AI deployments to be governed, reliable, repeatable, and scalable enough to earn trust and deliver measurable results. Most importantly, it must be grounded in and continuously integrate the knowledge of subject matter experts who understand the complexity of real systems and processes.​

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In this session, we will share lessons learned from deploying large-scale agentic AI solutions in the semiconductor industry. We will explore how SME expertise and operational context can be embedded into Agentic AI systems to create trusted, high-value results. Specifically, we will show how an auto-Triage/RCA a Facilities Anomaly event workflow can be set up such that, as the event triggers, an AI agents completes a first pass investigation that is ready for consumption by the end user shortly after an event triggers with an optional integration with CMMS systems to ease the creation of a work order to drive faster time to resolution and greater consistency in event disposition. We will also demonstrate how engineers can build custom apps and AI agents on demand, without requiring an AI specialist or extensive coding skills, while maintaining the structure and scalability needed for enterprise adoption. Attendees will leave with practical insights for enabling better, faster decisions across engineering, technician, and operator workflows.

Afternoon, Day 1: August 5th, 2026

2:00 pm - 3:00 pm
Steven Sheets
Lam Research

Human-Machine Collaboration for Improving Semiconductor Process Development

One of the bottlenecks to building semiconductor chips is the increasing cost required to develop chemical plasma processes that form the transistors and memory storage cells1,2. These processes are still developed manually using highly trained engineers searching for a combination of tool parameters that produces an acceptable result on the silicon wafer3. The challenge for computer algorithms is the availability of limited experimental data owing to the high cost of acquisition, making it difficult to form a predictive model with accuracy to the atomic scale. Here we study Bayesian optimization algorithms to investigate how artificial intelligence (AI) might decrease the cost of developing complex semiconductor chip processes. In particular, we create a controlled virtual process game to systematically benchmark the performance of humans and computers for the design of a semiconductor fabrication process. We find that human engineers excel in the early stages of development, whereas the algorithms are far more cost-efficient near the tight tolerances of the target. Furthermore, we show that a strategy using both human designers with high expertise and algorithms in a human first–computer last strategy can reduce the cost-to-target by half compared with only human designers. Finally, we highlight cultural challenges in partnering humans with computers that need to be addressed when introducing artificial intelligence in developing semiconductor processes.​

What the Audience will Learn:
How Bayesian optimization can help enhance speed-to-solution for semiconductor manufacturing.

3:00 pm - 3:20 pm

Break

3:20 pm - 5:20 pm
Sainyam Galhotra
Third AI Automation

From Prediction to Action: Causal AI for Real-Time Root-Cause Analysis in Semiconductor Manufacturing

Semiconductor fabs generate massive volumes of data across tools, sensors, inspection systems, and process logs—yet most AI deployments remain predictive, identifying anomalies without explaining their root cause. This results in prolonged root cause analysis (RCA), costly downtime, and repeated trial-and-error fixes.​

In this talk, we present a practical approach to moving from prediction to action using causal AI. By unifying multi-modal data like images, time-series signals, and process metadata into a single intelligence layer, we enable systems that reason about cause-and-effect relationships rather than correlations.​

We will discuss how such systems can be trained efficiently using weak supervision and deployed at the edge to meet latency, privacy, and reliability requirements. We also highlight how continuous monitoring and model refinement in production ensure sustained performance in dynamic manufacturing environments.​

Drawing from real-world deployments, we show how this approach reduces RCA time from hours to minutes, improves diagnostic accuracy, and enables prescriptive actions for faster yield recovery and improved operational efficiency.​

What the Audience will Learn:​
1. Why predictive AI falls short for RCA and how causal AI bridges the gap​
2. How to build an “intelligence layer” on top of MES and traceability systems​
3. Practical methods for leveraging limited labeled data ​
4. How to integrate multi-modal data (inspection images + sensor logs + process flows)​
5. How to build AI agents that improve with more data​

How this AI technique is being used in industry today (real deployments, lessons learned, impact): In semiconductor manufacturing environments, causal AI systems are being deployed alongside existing inspection and MES infrastructure to accelerate and improve root cause analysis.​

In one deployment, defect patterns observed across multiple inspection stages were correlated with tool-level and process metadata. Instead of manual investigation across dozens of steps, the system identified a specific tool-stage interaction responsible for recurring defects. This reduced RCA time from 20–40 hours to under 10 minutes while improving diagnostic consistency.​

Demo: Yes​

Hands-on Session:
Yes,​ Applying weak supervision to label defect data with minimal manual effort​
Interpreting causal relationships across process steps​
Monitoring and updating models in a production-like setting​

5:20 pm - 7:20 pm

Reception

Morning, Day 2: August 6th, 2026

9:00 am - 10:00 am
Akhilesh Kumar​ ​
Synopsys/ANSYS

Get More from Your Sign-off Flow: Agentic AI That Makes Power & Signal Integrity Engineers Radically More Productive

Agentic AI is moving from research demos to production EDA flows, and the leverage is very clear in power and signal integrity sign-off, where engineers routinely write 1000+-API Python scripts, search for root causes through ~100 GB log files, and stitch results across half a dozen vendor tools. This talk presents our experiences with building, shipping, and supporting a multi-agent system for a production sign-off tool used on modern VLSI and 3DIC designs — covering what it took to move from a single LLM "wrapper" to a hardened agentic system that customers can actually trust with their IP.​

We will walk through the full stack: a multi-agent architecture (code-generation, log-debug, RCA/diagnostics) built on a Deep-Agent framework; an Agent Skills pattern that makes diagnostic workflows modular, composable, and customer-extensible; MCP used in both directions (the Copilot consumes vector-DB and API knowledge as MCP, and the tool itself is exposed as an MCP server so other EDA agents and customer orchestrators can drive it); and a governance layer covering tiered action approval, API-hallucination guards, prompt sanitization, audit trails, and on-premise / air-gapped local-LLM deployment. We will close on the next frontier: cross-vendor agent-to-agent flows, for example, place-and-route → parasitic extraction → power integrity → timing — orchestrated through MCP, with humans setting policy at well-defined checkpoints rather than copy-pasting between tools.​

The session is built for practitioners. A curated set of short demo videos recorded from real Agentic AI sessions on representative designs showing the agent generate scripts and run a multi-step RCA end-to-end, with explanations on what is happening under the hood at each step.​

What the Audience Will Learn​:
1. Reference architecture for a production EDA Copilot: Multi-agent decomposition (code-gen, log-debug, RCA), RAG over manuals/API catalogs, and tool execution inside the host EDA product.​
2. The Agent Skills pattern for RCA / diagnostics: Composable Agent Skills (IR-drop RCA, anomaly detection, comparative run analysis) the orchestrator plans over and that customers can extend without touching the core.​
3. MCP as a two-way integration framework: Consuming knowledge and tool capabilities as MCP and exposing the EDA tool itself as an MCP server so customer or partner agents can drive it.​
4. Governance and guardrails for production: Tiered action approval, API-validation against the catalog to block hallucinations, prompt sanitization for IP, audit trails, and runaway controls.​
5. A practical LLM strategy: Cloud frontier models, qualified open-weight local LLMs for air-gapped customers, and distillation + RL fine-tuning strategies with LLM-as-judge and production feedback.​
6. The feedback flywheel: What to instrument to drive weekly prompt fixes, monthly workflow updates, and quarterly model improvements.​
7. Cross-vendor agentic flows: Sequential chaining, parallel fan-out, and iterative loops across EDA tools over MCP.​

How This AI Technique Is Being Used in Industry Today​

The Copilot is a shipped, per-user binary that launches alongside a production sign-off tool, attaches to the user's interactive session, and runs entirely on customer infrastructure (cloud LLM or fully on-premise).​

Demo Session: Curated Videos (20 min)​

Rather than a live hands-on segment, the demo is a curated set of short, pre-recorded clips captured from real Copilot sessions on representative designs. This keeps the demonstration crisp and reproducible, and the speaker narrates each clip — calling out which agent, skill, or MCP call is firing and why.​

10:00 am - 10:20 am

Break

10:20 am - 11:20 am
Abhinav Kumar
Applied Materials

From Data Silos to Autonomous Discovery: Agentic AI in Semiconductors

Semiconductor manufacturing is increasingly challenged not by the availability of data, but by the difficulty of integrating and reasoning across fragmented, heterogeneous information sources spanning process data, metrology, and engineering knowledge. This session introduces a practical, system-level perspective on building agentic AI capabilities for semiconductor applications, beginning with foundational considerations in data definition, representation, and consistency across structured and unstructured domains.​

The discussion focuses on how these foundations enable a transition from isolated analytics toward more integrated, decision-oriented systems. Architectural patterns are explored for combining data-driven models, simulation, and domain knowledge into cohesive workflows, with emphasis on reliable orchestration, traceability of reasoning, and appropriate human oversight—elements that are critical for deploying AI in high-stakes manufacturing environments.​

The session concludes with an overview of how emerging approaches are extending these ideas toward more adaptive and semi-autonomous optimization systems. Attendees will gain a structured view of the end-to-end stack—from data preparation to decision support—and practical insights into considerations for adopting agentic AI methodologies in semiconductor manufacturing settings.

11:20 am - 11:50 am
Justin Hayes
VP of Field Engineering and Semiconductor SME
Vectara​

Building a Trustworthy Semiconductor Knowledge Base for Agentic Insight Generation

Semiconductor organizations face doubling advanced-node design costs, compressing design cycles, and scarce engineering talent while their most valuable asset, engineering knowledge, sits fragmented across schematics, waveforms, 8D reports, JIRA tickets, fab SOPs, and decades of tribal expertise. Generic search and AI tools routinely fail on this dense, technical content. ​

Drawing on real-world deployments at Broadcom, SanDisk, Altera, and Texas Instruments, Vectara will explore the solution architecture and real-world deployment of their domain-specialized Knowledge Hub and Agentic AI Platform designed specifically for the semiconductor lifecycle. ​

We'll walk through the multi-stage ingestion pipeline that preserves formulas, nested tables, and schematics natively; Vectara unified retrieval fabric that replaces fragmented, separately licensed point tools; and the agent layer that runs multi-hop, semantically deep queries across technical logs and historical failures - letting engineers surface root-cause indicators in plain language, no SQL required. ​

Crucially, the session will focus on what production-grade accuracy demands: grounded, citation-backed answers over complex IP for generating net-new insights, and streamline cross-team knowledge reuse that engineering teams, and agents can trust.

11:50 am - 1:00 pm

Lunch

Afternoon, Day 2: August 6th, 2026

1:00 pm - 2:30 pm
Garima Sharma
Mathworks

Making Sense of Equipment Time‑Series Data: From Signals to Insight

Modern semiconductor equipment generates vast amounts of time-series and inspection data, but much of it remains under-utilized. This session presents a practical, end-to-end workflow—from data preparation and AI modeling (including anomaly, defect, and drift detection) to validation and deployment—using familiar manufacturing data. It also highlights how synthetic data and generative AI can accelerate model development while maintaining robust validation and engineering control.​​

What the Audience will Learn:​
Attendees will learn how to turn equipment data into actionable insights using an end-to-end AI workflow—from data preparation to deployment. They will also see how multiple AI approaches, synthetic data, and generative AI can accelerate development while maintaining rigorous engineering validation.​

Demo / Hands-on Session: Yes

2:30 pm - 2:45 pm

Break

2:45 pm - 4:15 pm
Jon Herlocker
Cohu

Achieving Business Results from Air-gapped Agentic AI Automation in Semiconductor Manufacturing - Lessons from the Field

Agentic AI has crossed a capability line where it can now effectively automate non-trivial portions of work that previously was only done by factory engineers - process engineers, yield engineers, test engineers, maintenance engineers. At Cohu, we have been working closely every week with our customers to roll out agentic capabilities that are leading to significant automation, yield, and capacity improvements. Along the way, we have needed to overcome significant constraints - such as prohibitions on providing sensitive process data to cloud AI providers - and had to manage the more complicated issue of integrating agentic AI into legacy systems and processes. In this talk I can share some of ways that our customers are benefiting from agentic AI and talk about some of the learnings gained through these various deployments. ​

What the Audience will Learn:​
Key learnings for the audience a) real use cases of agentic AI in global semiconductor manufacturing companies; b) practical recommendations for how to prepare for and be successful with the deployment of agentic AI in semiconductor manufacturing. ​
​
Demo:​
FDC model creation, and fault analytics​
Yield analytics​
Tester Operations Management​
Test Engineering - lot disposition analytics ​
Maintenance optimization and predictive maintenance​
Line support optimization

- Smart MFG

 

The SEMI Smart Manufacturing Initiative is hosting a two-day workshop titled "AI Techniques in Semiconductor Manufacturing" at SEMI HQ in Milpitas, CA, on August 5–6, 2026. This event is part of a continuing series focused on integrating advanced AI into the semiconductor landscape. The workshop is designed to help participants understand: The real-world deployment, impact, and lessons learned from AI techniques. Strategies for building observable and scalable multi-agent workflows. The industry transition from restrictive data silos toward autonomous discovery. Methods for achieving tangible business results and automation through diverse AI applications.

8:00 am - 5:00 pm Off Add to Calendar 2026-08-05 08:00:00 2026-08-06 17:00:00 AI Techniques in Semiconductor Manufacturing  The SEMI Smart Manufacturing Initiative is hosting a two-day workshop titled "AI Techniques in Semiconductor Manufacturing" at SEMI HQ in Milpitas, CA, on August 5–6, 2026. This event is part of a continuing series focused on integrating advanced AI into the semiconductor landscape. The workshop is designed to help participants understand: The real-world deployment, impact, and lessons learned from AI techniques. Strategies for building observable and scalable multi-agent workflows. The industry transition from restrictive data silos toward autonomous discovery. Methods for achieving tangible business results and automation through diverse AI applications. SEMI HQ 673 S Milpitas Blvd. Milpitas, CA 95035 United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register Now
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Brewer Science Earns 2026 USA TODAY Top Workplaces Award
Employee-Owner Feedback Recognizes Company’s People-First Culture

Rolla, MO – April 14, 2026 – Brewer Science, Inc., a global leader in developing and manufacturing next-generation materials and processes for the microelectronics and optoelectronics industries, has been named a 2026 USA TODAY Top Workplace. The recognition underscores Brewer Science’s long-standing commitment to fostering a people-first culture.

The USA TODAY Top Workplaces award honors organizations with 150 or more employees that have created exceptional workplace cultures centered on trust, engagement, and employee well-being. This year, more than 42,000 organizations were invited to participate. Award recipients are recognized for building environments that prioritize employee listening and meaningful engagement. USA TODAY showcased the winners online and at the National Awards Summit in Las Vegas.

Winners are determined solely by authentic employee feedback collected through a confidential survey administered by Energage, the HR research and technology company behind the Top Workplaces program since 2006. Results are based on employee responses to Workplace Experience Themes, which research shows are strong indicators of organizational health and performance.

“Earning a USA TODAY Top Workplaces award is a testament to an organization’s credibility and commitment to a people-first culture,” said Eric Rubino, CEO of Energage. “This award, driven by real employee feedback, is more than just a recognition — it’s proof that your employees believe in the organization and its leadership. Job seekers and customers look for this trusted badge of credibility and excellence. It signals a company that values its people, and that kind of culture resonates in today’s competitive market.”

In addition to the national USA TODAY recognition, Brewer Science continues to receive strong regional and industry-specific honors. In 2025, the company was named a Top Workplace in Greater St. Louis for the ninth consecutive year and earned recognition as a 2025 National Top Workplace in the Manufacturing Industry. These sustained accolades reflect a culture intentionally designed to provide employee-owners with a fulfilling and purpose-driven work experience that fuels innovation across the microelectronics industry.

“Delivering customized solutions to customers’ complex challenges requires a strong sense of clarity and commitment across the company,” said Dan Brewer, co-CEO of Brewer Science. “That commitment is rooted in our value to create an environment where employees are empowered to think creatively, collaborate openly, and innovate boldly. Our employee-owners take pride in the products they bring to our customers, partners, and the industry as a whole.”

Learn more about Brewer Science’s culture and explore career opportunities at:
https://www.brewerscience.com/about-us/company/careers/

ABOUT BREWER SCIENCE
Brewer Science is a global leader in developing and manufacturing next-generation materials and processes that foster the technology needed for tomorrow. Since 1981, we’ve expanded our technology portfolio within advanced lithography, advanced packaging, smart devices, and printed electronics to enable cutting-edge microdevices and unique quality monitoring systems for water and air applications. We are Certified Employee-Owned and a Certified B Corporation™, using our business as a force for good. Our headquarters are in Rolla, Missouri, with customer support throughout the world. Learn more at: www.brewerscience.com.

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Company Contact:
Nathan Ayres
Email: [email protected]

ABOUT ENERGAGE
Energage is a purpose-driven company that helps organizations turn employee feedback into useful business intelligence and credible employer recognition through Top Workplaces. Built on 20 years of culture research and the results from 30 million employees surveyed across more than 80,000 organizations, Energage delivers the most accurate competitive benchmark available. With access to a unique combination of patented analytic tools and expert guidance, Energage customers lead the competition with an engaged workforce and an opportunity to gain recognition for their people-first approach to culture. For more information or to nominate your organization, visit energage.com or topworkplaces.com.