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Japan

Japan Standards Technical
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SEMI Japan
26F, xLINK Marunouchi Eiraku Bldg.
1-4-1 Marunouchi
Chiyoda-ku, Tokyo
1000005
Japan

Standards

Liquid Chemicals Japan TC Chapter Meeting 

Date: Thursday, May 21, 2026

Time: 3:30 pm - 5:30 pm JST

Venue: SEMI Japan Office + OVTCCM (Hybrid)

 

AGENDA

 

Standards Contact Information:

Takeaki Hirabara

Standards & EHS, SEMI Japan

Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

Questions? Contact your local staff coordinator: Click here

3:30 pm - 5:30 pm Off Add to Calendar 2026-05-21 15:30:00 2026-05-21 17:30:00 Liquid Chemicals Japan TC Chapter Meeting Liquid Chemicals Japan TC Chapter Meeting Date: Thursday, May 21, 2026Time: 3:30 pm - 5:30 pm JSTVenue: SEMI Japan Office + OVTCCM (Hybrid) AGENDA Standards Contact Information:Takeaki HirabaraStandards & EHS, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click here SEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi Chiyoda-ku, Tokyo 1000005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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Otemachi PLACE HALL & CONFERENCE
Otemachi PLACE East Tower
2-3-1 Otemachi,
Chiyoda-ku, Tokyo
1000004
Japan

Standards

Physical Interfaces & Carriers Japan TC Chapter Meeting 

Date: Thursday, May 21, 2026

Time: 9:00 am - 12:00 pm JST

Venue: Room 102 @ Otemachi PLACE HALL & CONFERENCE + OVTCCM (Hybrid)

 

AGENDA

 

Standards Contact Information:

Takeaki Hirabara

Standards & EHS, SEMI Japan

Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

Questions? Contact your local staff coordinator: Click here

9:00 am - 12:00 pm Off Add to Calendar 2026-05-21 09:00:00 2026-05-21 12:00:00 Physical Interfaces & Carriers Japan TC Chapter Meeting Physical Interfaces & Carriers Japan TC Chapter Meeting Date: Thursday, May 21, 2026Time: 9:00 am - 12:00 pm JSTVenue: Room 102 @ Otemachi PLACE HALL & CONFERENCE + OVTCCM (Hybrid) AGENDA Standards Contact Information:Takeaki HirabaraStandards & EHS, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click here Otemachi PLACE HALL & CONFERENCE Otemachi PLACE East Tower 2-3-1 Otemachi, Chiyoda-ku, Tokyo 1000004 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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India Japan Malaysia Singapore South Korea Taiwan United States Vietnam Inside the Fab Training

Course Description 

This course provides a comprehensive introduction to semiconductor manufacturing, guiding participants through the complete journey from silicon fundamentals to chip fabrication and packaging. Designed for professionals new to the semiconductor industry, the course explains key concepts, terminology, devices, and manufacturing processes used in modern fabs. 

Who Should Attend

Anyone interested in understanding semiconductor manufacturing, including new employees, professionals in related industries, and those seeking to broaden their knowledge of the field.  

Learning Objectives

Upon completion of the course, participants should be able to:

  • Explain fundamental semiconductor concepts, including silicon materials, doping, PN junctions, and basic device behavior. 
  • Identify and correctly use common semiconductor manufacturing terminology.
  • Outline the key steps involved in front-end wafer fabrication, from bare silicon to patterned wafers.
  • Summarize back-end manufacturing processes, including assembly, packaging, and testing.

Topics Included

  • Basic Electronics and Microelectronics
  • Process Nodes
  • Device Physics and Transistor Operation
  • Crystal Growth and Wafer Preparation
  • Advanced Transistor Technologies
  • Circuit Design and Layout
  • Wafer Processing

Important Information

Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access the course knowledge. 

Can't find the training link on the day of the training? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders 24 hours in advance and 1 hour before, with the same link. Please keep these emails on hand to access the training on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.

 

Kalya Shubhakar
Kalya Shubhakar
Senior Lecturer
 

 

Singapore

- SEMI U

Strengthen your knowledge and skills by learning about the journey from silicon fundamentals to chip fabrication and packaging. 

Pricing                     
  • Members:  $399
  • Non-Members:  $449

* * Group pricing for 10+ attendees: $3,800 and 20+ attendees: $7,600
Any questions, please contact [email protected]

10:00 am - 2:00 pm Off Add to Calendar 2026-08-10 10:00:00 2026-08-13 14:00:00 Inside the Fab: An Introduction to Semiconductor Manufacturing (Asia) Strengthen your knowledge and skills by learning about the journey from silicon fundamentals to chip fabrication and packaging. Pricing                     Members:  $399Non-Members:  $449* * Group pricing for 10+ attendees: $3,800 and 20+ attendees: $7,600Any questions, please contact [email protected] Singapore SEMI.org [email protected] Asia/Singapore public Asia/Singapore Register Now
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Thank you to our sponsors:  

 

 

         Sundt Construction Company & General Contractor | Sundt                                   SCREEN logo

 

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United States

9:00 am - 9:10 am

Welcome and Overview of the Water Management Working Group

9:10 am - 9:25 am
Pascal Osten
Leader, Water Solution Providers Cohort
Pascal Osten
DAS Environmental Expert GmbH

Procedures Guide

9:25 am - 9:35 am
Catherine Marsan-Loyer
Co-Lead, Fab, OSATs Cohort
Catherine Marsan-Loyer
C2MI

Water Savings Guide and Baseline-setting

9:35 am - 9:45 am
Jared Burdik
Co-Lead, Fab, OSAT Cohort
Jared Burdick
Sundt Corp.

Solutions Maturity Scale

9:45 am - 9:55 am

Q&A & WrapUp

EHS SMG Sustainability EMG FOA Standards

Join the SEMI Water Management team and document authors for a webinar discussing their research and findings for the Water Management Strategy Reports.  The reports are guides for water managers for understanding their water balance, baseline, potential savings and a general maturity scale for several solutions to be considered to move up the maturity scale to Zero Liquid Discharge (ZLD). The webinar will provide an overview on how the documents should be used to work with water solutions providers and provide strategies for both new and legacy facilities with end-of-pipe solutions as well as treatments for individual process stage water discharge. 

The webinar will include a discussion of next steps for the continued development of the reports, including how they interact with SEMI Standards and the industry roadmaps.

Reports can be downloaded HERE.

9:00 am - 10:00 am Off Add to Calendar 2026-05-21 09:00:00 2026-05-21 10:00:00 Water Management Strategies Webinar Join the SEMI Water Management team and document authors for a webinar discussing their research and findings for the Water Management Strategy Reports.  The reports are guides for water managers for understanding their water balance, baseline, potential savings and a general maturity scale for several solutions to be considered to move up the maturity scale to Zero Liquid Discharge (ZLD). The webinar will provide an overview on how the documents should be used to work with water solutions providers and provide strategies for both new and legacy facilities with end-of-pipe solutions as well as treatments for individual process stage water discharge. The webinar will include a discussion of next steps for the continued development of the reports, including how they interact with SEMI Standards and the industry roadmaps.Reports can be downloaded HERE. United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register Here
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High-performance connectivity software delivers structured, high-volume equipment data required by tier-one fabs and advanced packaging facilities ahead of the expected mid-2026 SEMI standards update

POITIERS, March 25, 2026 – Agileo Automation, a leading provider of control and connectivity solutions for global semiconductor manufacturing, today unveils Agil'EDA, a new software solution implementing Equipment Data Acquisition (EDA), a set of SEMI standards also known as Interface A, to enable semiconductor equipment manufacturers to meet the evolving high-performance connectivity requirements of tier-one fabs and advanced packaging facilities.

As semiconductor manufacturing moves towards higher levels of automation and data-driven optimization, fab owners increasingly require EDA alongside traditional SECS/GEM connectivity from semiconductor OEMs for their production tools. Agil'EDA addresses this by separating the control flow from the data flow, ensuring that structured, high-frequency data collection does not interfere with critical equipment operations.
Designed for long-term deployment, Agil'EDA fully supports the widely used EDA Freeze 2 (SOAP/XML) and is architected for the transition to Freeze 3 (gRPC/protocol buffers). This next-generation standard offers significantly higher data throughput and reduced latency. Agileo has already successfully tested and validated its EDA Freeze 3 implementation at SEMI’s North America Standards Fall Meetings in November 2024 in Milpitas, California. SEMI’s EDA Freeze 3 standards suite is expected to be released mid-2026.

Complementing the SECS/GEM standards used to control equipment behavior, Agil’EDA incorporates robust cybersecurity features such as authentication and encrypted communications. The product is available as a stand-alone solution for any existing equipment software using a platform-independent gRPC application programming interface (API) to communicate with it or as a pre-integrated component within Agileo’s A²ECF-SEMI framework. When used with Agil'GEM and Agil'GEM300, it provides a comprehensive connectivity solution that significantly reduces time to market for OEMs.

"With the growing demand for data to improve yield in tier-one fabs, as well as in Advanced Packaging and 3D integration, EDA is no longer optional. It is becoming a mandatory requirement for equipment entering the world's most advanced fabs," explains Marc Engel, chief executive officer of Agileo Automation. "The key value we deliver for OEMs is a fast and easy adoption path for a seamless EDA architecture that delivers compliant production machines to global fab customers. By providing a future-proof architecture ready for Freeze 3, which will significantly increase performance, we address OEMs’ current needs while preparing them for the evolving requirements of semiconductor manufacturing, including AI-driven process control."

- ends -

About Agileo Automation
Agileo Automation is a trusted partner for equipment manufacturers, helping them build smarter, automated, and more connected machines that integrate seamlessly into advanced semiconductor fabs. Founded in 2010 in Poitiers, France, Agileo helps OEMs with control, communication, data acquisition, and testing across their tools through proven software and expert support. Its flagship A²ECF-SEMI framework provides a solid foundation for developing equipment controllers fully aligned with SEMI SECS/GEM, GEM300, and EDA standards. As an active member of SEMI and the OPC Foundation, Agileo Automation contributes directly to shaping the standards that drive manufacturing. For more information, please visit our website or follow us on LinkedIn.

Dresden, Germany, March 24, 2026 – As semiconductor manufacturing continues to expand in China, reliable and efficient environmental technologies are becoming increasingly important for stable and sustainable fab operation. DAS Environmental Experts presents its SALIX wet scrubber product family, a series of high-efficiency point-of-use systems designed for the treatment of waste gases from wet chemical processes in semiconductor manufacturing.

SALIX systems are engineered to ensure high removal efficiency and stable operation in demanding semiconductor production environments. SALIX reliably removes substances such as IPA, ammonia and hydrofluoric acid (HF) from waste gas streams of modern single wafer clean systems – a key contribution to safe and sustainable semiconductor manufacturing. In addition, the technology removes particles, salts and droplets from the processed gas stream. The robust system design supports high uptime and long maintenance intervals, contributing to reliable fab operation.

A key advantage of the SALIX product family is its flexible portfolio. SALIX products are among the smallest and most compact systems on the market and are suitable for both new fabs and retrofit applications in existing fabs. DAS Environmental Experts offers the technology in four different products, providing semiconductor manufacturers with a wide range of configuration options:

• NEW: SALIX – the latest release with improved performance and optimized system operation
• SALIX MINI – a compact two-stage system for space-constrained installations
• NEW: SALIX MICRO [SR1.1]– a highly compact configuration with pre-scrubber section for flexible integration

This structured product portfolio enables customers to select the most suitable system according to process requirements, fab layout and integration needs. The availability of multiple system variants within one technology platform provides semiconductor manufacturers with excellent flexibility in system selection and plant design.

SALIX systems are designed for compatibility with all common process tools and can be adapted to a wide range of wet chemical applications. Their compact design and flexible configuration support efficient integration into modern fabs, helping manufacturers optimize both environmental performance and operational efficiency.

The SALIX product family will be presented during SEMICON China 2026 (March 25–27, Shanghai New International Expo Centre). Interested visitors can learn more about the technology and its applications at the DAS Environmental Experts booth (Booth N2 | 2619).

With more than three decades of experience in environmental technology for the semiconductor industry, DAS Environmental Experts continues to support chip manufacturers worldwide with solutions that combine high process reliability, efficient emission treatment and long-term operational stability.

About the Company
DAS Environmental Experts Group (DAS Group), headquartered in Dresden, Germany, was founded in 1991 and is now a global organization with subsidiaries on three continents and more than 950 employees worldwide. Over the past three decades, DAS Group has become one of the leading technology and equipment providers for waste gas abatement solutions with a focus on semiconductor industry.
In addition, DAS Group develops advanced process and system solutions for industrial water treatment, with extensive expertise in the recycling and reuse of wastewater from the semiconductor industry.
DAS solutions are engineered to meet the stringent purity requirements of semiconductor manufacturing, helping clients comply with global environmental standards.

Registration

Please be sure to check / understand the followings before applying

  • Due to the nature of this product, we do not accept cancellations or refunds after the application has been made. Please understand this in advance.
  • When applying for this event, please register using a corporate email address.
  • SEMI Member Price is avilable for those who work for a SEMI member company or a wholly owned subsidiary that is registered as a subsidiary. If you are unsure, please click HERE to inquire. Please note that if your membership status cannot be confirmed, you will be charged the general price.
  • Payment is only possible by credit card. You can download your receipt from Receipt / Application History in your My Page.
  • Please note that places will be allocated on a first-come, first-served basis, so please apply as soon as possible.

    First deadline: June 5 (Fri.)
    Final deadline: June 25 (Thu.)

  • Symposium Fee
    SEMI Members : 280,000 JPY (Excluding tax)
    Please note that you will be responsible for the cost of local accommodation, transportation and participation in the golf competition. 
    A shuttle bus service is scheduled to run between New Chitose Airport and the venue.
  • Accommodation Charge 
    51,460JPY - 78,660JPY per night (including Breakfast and tax)
  • Golf Competition Participation [option]
    20,000JPY (Excluding tax)
  • Other Activities [option]
    2,200JPY - 38,500JPY (Excluding tax)
  • Travel Expenses
    Please bear your own travel and transportation expenses to New Chitose Airport.

SEMI Japan Event Registration
Email: [email protected]

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Japan Symposium Registration Accommodation and Shuttle Bus Booking Golf Registration ISS2026_top_event_bnr_508x448_en Business Executive

Accommodation and Shuttle Bus

Please see below for details on accommodations and shuttle buses.

The Windsor Hotel Toya Resort & Spa 

336 Shimizu, Toyako-cho, Abuta-gun, Hokkaido 049-5722

  • Superior Room Sea Side (40㎡) (Non-Smoking) 

    1 person usage:  51,460 JPY / night (per person) 
    2 people usage:  28,800 JPY / night (per person) 

  • Superior Room Lake Side (40㎡) (Non-smoking) 

    1 person usage:  54,760 JPY / night (per person) 
    2 people usage:  30,450 JPY / night (per person) 

  • Junior Suite Room Sea Side (58㎡) (Non-Smoking) 

    1 person usage:  72,060 JPY / night (per person) 
    2 people usage:  38,700 JPY / night (per person) 

  • Junior Suite Room Lake Side (58㎡) (Non-Smoking) 

    1 person usage:  78,660 JPY / night (per person) 
    2 people usage:  42,000 JPY / night (per person) 

    *Breakfast, consumption tax, bathing tax, and service charge are included.

[Outbound] July 8 (Wed) New Chitose Airport → Windsor Hotel Toya Resort & Spa

  • Duration: 120 minutes
  • Fare: Free (application is required)
  • Meeting / Departure: 
    Please arrive on a flight landing at New Chitose Airport between 8:30 and 10:00.
    Multiple shuttle services will be arranged to coincide with your flight arrival time.

     [For reference] Flight Schedule
    New Chitose AirportANAJAL

[Return] July 10 (Fri) The Windsor Hotel Toya Resort & Spa → New Chitose Airport

  • Travel Time: Approx. 120 minutes
  • Fare: Free (Advance reservation required)
  • Departure: 

Departures will begin from around 14:50, operating sequentially.
(Please note that departure times may vary depending on the program’s end time.)
*If you are taking the return bus, please book a flight departing at 6:30 PM or later.

JTB Global Marketing & Travel
ISS Japan 2026 Desk

*Inquiries can be received only by e-mail.
E-mail:  [email protected]
Office Hours: 10:00-16:30 (Mon-Fri except Saturdays, Sundays and Holidays)

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Overview

We will be holding “ISS Japan 2026”, a conference to discuss strategies and issues with an eye on the future of the industry.
As digital technology supports global prosperity, we will provide opportunities for exchanging opinions and networking on important issues such as sustainability, energy issues, and the latest technology, in order for Japan to demonstrate leadership as an important base for semiconductor manufacturing.

Date
July 8 - 10, 2026
Organizer
SEMI
Supporting Organization
Hokkaido
Attendee
150
(includes Government Officials, Top Executives of Semiconductor Device, Equipment, Material, and Component Companies)

*Please note that the program is subject to change.

The Windsor Hotel TOYAResort & Spa
Shimizu, Toyako-cho, Abuta-gun
Hokkaido
049-5722
Japan

Conference Check-In, Welcome Lunch

11:15 am

Session 1 Opening

1:30 pm
Jim Hamajima
President
SEMI Japan

Opening Remarks

Ajit Manocha, SEMI
Ajit Manocha
President & CEO
SEMI

Welcome Remarks

Daishiro-Yamagiwa
Daishirou Yamagiwa
Member, House of Representatives (LDP)
Chairman, Diet Members Caucus for the Promotion of Semiconductor Strategy(LDP)

Special Presentation

Break

2:30 pm

Session 2 Global Technology Leaders

2:40 pm
Kota Nosaka
Kota Nosaka
Representative Director, Vice President
Micron Memory Japan
Yutaka Emoto
Yutaka Emoto
Vice President and Center General Manager
TSMC Japan 3DIC R&D Center

Advancing Tools & Materials to Empower 3DIC Manufacturing for AI Innovations

The roadmap for advanced packaging in AI applications presents significant challenges, particularly with scaling up and incorporating more chiplets.
This expansion poses obstacles in terms of yield and productivity.
To address these challenges, CoP (Chip-on-Panel) technology will be introduced to complement current CoW (Chip-on-Wafer) to accelerate 3DIC scale up. However, this shift requires substantial infrastructure development, especially for tool development and material innovations. Meanwhile, material usage will be significantly increased, raising concerns about supply chain resilience.
All of which will play a pivotal role in enabling this critical technology expansion and requires seamless collaborations across backend eco-system.

Biography

Akio Yamaguchi
Akio Yamaguchi
President and Representative Director, IBM Japan
Representative Director, Japan Association of Corporate Executives

Technological Evolution and Economic Growth

As global change accelerates and the international environment becomes increasingly uncertain, the effective use of technologies such as AI is essential for Japan to achieve sustainable economic growth. At the same time, building a “Collaborative Growth Model” rooted in empathy enables us to realize true prosperity. This lecture explores the latest technological trends and discusses Japan’s vision for sustainable growth.

Biography

Hiromichi Nozaki
Hiromichi Nozaki
National Technology Office・Chief Technology Officer
Microsoft Japan

An Autonomous Digital World Powered by AI Agents: The New Frontier of Value Creation Enabled by Generative AI

Generative AI is beginning to create an “autonomous digital world,” in which operations and decision-making are orchestrated autonomously through AI agents.
In this session, we will provide an overarching view of how these technological advancements are transforming corporate business processes, organizational structures, and executive decision-making, and examine the fundamental impact these changes have on competitiveness and business strategy.
In addition, the session will offer insights for Japanese companies and the Japanese market from a global perspective, while sharing Microsoft’s vision for the future and strategic perspectives on driving new value creation.

Biography

Break

4:40 pm

Session 3 Geopolitics, Economic Security in Asia

5:00 pm
Kazumi Nishikawa
Kazumi Nishikawa
Deputy Director General for Semiconductor and Information Policy Deputy Director General for Economic Security
Ministry of Economy, Trade and Industry

Economic Security and Semiconductor

This presentation will discuss the growing importance of the semiconductor industry amid concurrent geopolitical tensions,
supply chain disruptions, and technological advancements; outline strategies for fostering innovation and strengthening supply chain resilience;
and introduce the Japanese government’s AI and semiconductor strategy in light of these developments.

Biography

J.W. Kuo
Jyh-Huei Kuo
Former Minister of Economic Affairs, Taiwan

Inside Taiwan’s Semiconductor Strategy: Technology, Supply Chains, and Geopolitics

This presentation explores Taiwan’s semiconductor development strategy as a "pivotal fulcrum" of the global AI industry. First, it examines how Taiwan maintains its technological leadership by leveraging advanced process nodes and the unique cluster advantage of "zero distance between R&D and production". Second, from a supply chain perspective, it analyzes innovative models for the global deployment of the industrial ecosystem. Furthermore, the session addresses the strategic management of key technical know-how amidst geopolitical challenges and defines a collaborative positioning of "deep coupling" with global partners. Finally, it highlights the evolution and vision
of government policy as it transforms from a "regulator" into an "enabler".

Biography

Kazuhide Ueno
Kazuhide Ueno
Partner, Attorney-at-law
TMI Associates

Geopolitics, Economic Security, and Asia (China/India)

This session explains approaches to addressing economic security risks, incorporating the latest developments in export and investment regulations in the semiconductor sector. In particular, it focuses on risks associated with business operations in China and India.

Biography

Shuhei Yamada
Shuhei Yamada
Specially Appointed Professor, MBA Program
J. F. Oberlin University

China’s Semiconductor Supply Chain: Accelerating Self-Reliance

In March this year, the Chinese Communist Party and government adopted the 15th Five-Year Plan (2026–2030), reaffirming their commitment to accelerating “self-reliance and self-strengthening” in high-tech industries centered on semiconductors. This presentation examines how far China’s semiconductor supply chain has advanced toward greater autonomy amid prolonged U.S.–China technology tensions. By analyzing developments in key firms, it also considers how Japanese companies should respond to these changes.

Biography

Break

7:00 pm

Welcome Reception &Dinner

7:20 pm
Akira Amari
Akira Amari
Former Member of the House of Representatives
Honorary Chairman, Diet Members Caucus for the Promotion of Semiconductor Strategy(, LDP)

Kiyohiro Houkin
Kiyohiro Houkin
President
Hokkaido University

Session 4 BreakFast & Round Table

7:30 am

①Supply chain Resilience
②International Competitiveness
③Geopolitics
④Energy

Coffee Break

9:20 am

Session 5 The Insights from Round Table Discussion

9:40 am

Break

10:50 am

Session 6 Leadership and Strategy to Forge Japan's Future

11:00 am
Shingo Yamagami
Shingo Yamagami
Special Advisor
TMI Associates

How Should Japan Respond to the Turbulent World?

The world has witnessed the Russian invasion of Ukraine, China’s wolf warrior diplomacy and a series of economic coercion, and the US military operations in Venezuela as well as Iran.
How should Japan react to the measures by major powers that shake the foundations of the rules-based international order established after WWII?

Fawning China, worshipping the US, and the deterioration of Japan’s presence in the world.
How could Prime Minister Takaichi extricate Japan’s diplomacy from such a stalemate that has continued since PM Suga through PM Kishida and Ishiba?

These will be discussed candidly in light of the speaker’s 40-year-long experience as a diplomat.

Biography

Yoshimitsu Kaji
Yoshimitsu Kaji
Chairman, Chief Sustainability Development Officer
CinnamonAI

Lunch

12:00 pm

Off-site Networking Activity (Option)

1:00 pm

Dinner Party

7:00 pm
Ryuichi Yokota
Ryuichi Yokota
Mayor of Chitose

Session 7 Economic and Market Trends

8:20 am
Takeru Hanaya
Takeru Hanaya
Senior Analyst, Equity Research
SMBC Nikko Securities

SPE Shaping the Next-Gen Semiconductor Industry

AI is dominating the semiconductor market. As AI-related semiconductor prices rise and demand continues to grow, the outlook for the Semiconductor Production Equipment (SPE) market is improving. In addition to demand fueled by technological innovations unique to AI semiconductors, the industry faces an urgent need to construct new fabrication facilities and add production lines to keep up with increased volumes. In this seminar, we will explore the outlook for both the semiconductor and SPE markets.

Biography

Mikiya Yamada
Mikiya Yamada
Equity Research Dept. /Senior analyst
Mizuho Securities

Semi-Materials Supporting Japan's Competitive Edge

We would like to examine the current status and future prospects of Japan's Semiconductor Materials Industries that not only provides solutions for BEOL where semiconductor elements are formed on wafer surface but also for BEOL where thermal and insulation managements are vital. We would like to briefly touch the implications of geopolitical risks.

Biography

Minami Hamanaka
Minami Hamanaka
Associate Partner
McKinsey & Company

GenAI and Chips in the Post-Training Era

AI progress continues to accelerate. Frontier development is shifting from scaling pretraining to optimizing inference and strengthening agent/orchestration layers. This drives demand beyond GPUs to DPUs and data center infrastructure. As physical AI and multimodal models rise, this talk examines the implications for the semiconductor industry.

Biography

Coffee Break

9:50 am

Session 8 Global Technology Roadmap for the Semiconductor Era

11:00 am
Naoko Doi
Naoko Doi
Senior Research Director
The Institute of Energy Economics, Japan

Toward a Secure Electricity Supply: Meeting the AI and Semiconductor Demand

Global electricity demand is rising due to the growing needs of AI and semiconductors, alongside advancing electrification in the industry, transport, and buildings. In developing Asian countries, structural shifts toward electrification are also being pursued to counter soaring oil prices, making the securing of a stable power supply a shared global challenge.This presentation highlights future demand outlooks and proposes solutions—including AI-driven energy efficiency, grid enhancement, and "watt-bit" integration—and draws implications for Japan.

Biography

Farewell Lunch

11:40 am

Session9 Grand Finale Japan's International Competitiveness

12:30 pm
Oliver Faynot
Oliver Faynot
Silicon Component Division Manager
CEA-Leti

Shaping the Future of High-Value-Added Electronic Products

Artificial Intelligence (AI) has push the semiconductor industry toward a great challenge of energy efficiency. AI rely on massive infrastructure that are converting electricity into token. The demand is very high at either device level (high transistor density, huge amount of memory, etc.), technology level (3D integration, 3D partitioning, etc.) and infrastructure (power management, optical interconnection, etc.). These challenges are a unique opportunity to promote innovation at system level to reach a sustainable way to support AI requirements in terms of energy.
Biography

12:30 pm
Satoshi Nohara
Satoshi Nohara
Director-General, Commerce and Information Policy Bureau
Ministry of Economy, Trade and Industry
Jun Sawada
Jun Sawada
Chairman and Member of the Board
NTT

Toward a Science and Technology-oriented Nation: The Future of Japan

As the world grapples with challenges such as population decline and intensifying global competition, how can Japan achieve sustainable growth? This session will highlight technologies such as space, AI, and robotics from a broad perspective that spans industry, society, and philosophy. We will explore Japan’s future and strategic direction through “science and technology-oriented nation,” a concept advocated by Keidanren.
Biography

Atsuyoshi Koike
Atsuyoshi Koike
CEO
Rapidus
Jim Hamajima
SEMI Japan
President

Closing Remarks

End

2:40 pm

-

ISS (Industry Strategy Symposium)
Japan 2026

日本語ページはこちら

Off Add to Calendar Disabled

Off-site Networking Activity

On the afternoon of the second day, we invite you to relax and enjoy a moment of calm surrounded by the wide open skies and lush greenery of Hokkaido’s magnificent natural landscape.
As part of ISS Japan’s off-site networking activities designed to foster connections among participants, we offer not only a golf competition but also a variety of alternative activities for those who do not wish to participate in golf.

ISS Networking Golf

Golf course
Windsor Great Peak of Toya
(Adjacent to the ISS venue)

Date
Thursday, July 9

Schedule
12:00-13:00 Lunch
13:00-18:30 Golf Tournament
19:00-20:30 Dinner Party

Activities

For those not participating in the golf tournament, we invite you to enjoy a variety of activities that allow you to experience the magnificent natural landscapes of Hokkaido.
A wide range of activity programs offered by the hotel is available.
https://www.windsor-hotels.co.jp/en/activity/

Reservations can be made via the link below.
Reservation Contact Information
Tel: +81-142-73-1177 (Hours: 8:00 AM – 5:00 PM)
Email: [email protected]
* When making your reservation, please mention that you will be attending “ISS JAPAN."

 
Asia/Tokyo

ISS Hokkaido 2025 Event Report

ISS 2025 参加者集合写真

We have compiled an overview of the 2025 event, along with photos of participants and their comments.

Download (PDF)

ISS 2025 参加者集合写真

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ISS Europe 2025

2025-05-26

Europe’s Semiconductor Strategy: Navigating Geopolitics, Building Resilience

As geopolitical dynamics continue to influence global industries, the semiconductor sector finds itself at a pivotal crossroad. During the SEMI Industry Strategy Symposium (ISS Europe) held in Sopot, Poland, a high-level panel on the Geopolitics of Semiconductors brought together leaders from across the ecosystem to explore Europe’s role in an increasingly fragmented world shaped by strategic dependencies and evolving alliances.

Read More

ISS Europe 2025

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SEMI Japan
26F, xLINK Marunouchi Eiraku Bldg.
1-4-1 Marunouchi,
Chiyoda-ku, Tokyo
1000005
Japan

Standards

Information & Control Japan TC Chapter Meeting 

Date: Friday, April 17, 2026

Time: 9:30 am - 12:00 pm JST

Venue: SEMI Japan Office Room 1 + OVTCCM (Hybrid)

 

AGENDA

 

Standards Contact Information:

Takeaki Hirabara

Standards & EHS, SEMI Japan

Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

Questions? Contact your local staff coordinator: Click here

9:30 am - 12:00 pm Off Add to Calendar 2026-04-17 09:30:00 2026-04-17 12:00:00 Information & Control Japan TC Chapter Meeting Information & Control Japan TC Chapter Meeting Date: Friday, April 17, 2026Time: 9:30 am - 12:00 pm JSTVenue: SEMI Japan Office Room 1 + OVTCCM (Hybrid) AGENDA Standards Contact Information:Takeaki HirabaraStandards & EHS, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click here SEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi, Chiyoda-ku, Tokyo 1000005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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Brings Advocacy for the adoption of RISC-V processors and processor verification tool standards

Leverages broad experience in EDA business strategy, marketing and sales

SAN JOSE, Calif., March 05, 2026 (GLOBE NEWSWIRE) -- Breker Verification Systems today named Larry Lapides, former Synopsys Executive Director of RISC-V Tools Business Development, to its Advisory Board.

In making today’s announcement, David Kelf, Breker’s CEO, noted that Lapides has been a tireless advocate for the adoption of RISC-V processors and the urgent need for RISC-V processor verification tool standards. “Larry’s RISC-V knowledge and his ties to the RISC-V community are welcome additions to Breker and our advisory board.”

“Breker sits at the forefront in the development of commercial processor verification solutions and is a valued member of the RISC-V community,” remarks Lapides. “It will be a pleasure to work with Breker to move this important effort forward.”

Larry Lapides Biography
Lapides joined Synopsys through the acquisition of Imperas Software, where he was Vice President of Worldwide Sales and Marketing. He previously ran worldwide sales at EDA companies including Verisity Design and has more than 30 years in software tools and EDA, plus time spent in infrared systems engineering.

Lapides holds a Bachelor of Arts degree in Physics from UC Berkeley, a Master of Science degree in Applied Physics from Cornell University and an MBA from Clark University in Worcester, Mass.

About Breker Verification Systems
Breker Verification Systems solves complex semiconductor challenges across the functional verification process from streamlining UVM-based testbench composition to execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions that provide test content portability and reuse. Breker’s solutions include a SystemVIP library of scenarios for RISC-V and Arm, core and SoC testing, coherency, security and other critical areas. Breker solutions easily layer into existing environments and operate across simulation, emulation, prototyping, and post-silicon execution platforms. Its Trek family is production-proven at leading semiconductor companies worldwide and enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easy verification knowledge reuse. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), privately held Breker has a reputation for dramatically reducing verification schedules in advanced development environments. Case studies that feature Analog Devices, Broadcom, IBM and other companies leveraging Breker’s solutions are available on the Breker website.

Engage with Breker at:
Website: www.brekersystems.com
Twitter: @BrekerSystems
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/

TrekSoC, TrekSoC-Si, TrekBox and SoC Scenario Modeling are registered trademark of Breker Verification Systems. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products.

Location: Richardson, Texas

Modus Test, a leader in advanced test socket testing solutions and performance validation, and yieldWerx, a semiconductor data and yield analytics platform, today announced a strategic partnership to help close the gap between test hardware and yield intelligence. The collaboration combines Modus Test’s high-performance socket test technology with yieldWerx’s enterprise-scale yield management platform to provide manufacturers with direct visibility into the relationship between socket health and device performance.

The partnership addresses a long-standing disconnect between test execution and data analytics in high- volume manufacturing. Degraded, misaligned, or worn sockets can introduce false failures or escapes without clear root-cause identification. By integrating hardware performance data with yield analytics, manufacturers can better distinguish contact-related artifacts from true silicon failures.
Through this partnership, customers can now:
• Monitor and trend socket performance across testers, sites, and handlers
• Correlate device failures to specific sockets, test cells, or contact events
• Identify unnecessary device rejects caused by socket degradation
• Detect potential escapes where devices pass due to intermittent contact issues
• Optimize preventive maintenance cycles using data-driven insights

By integrating Modus Test equipment data with yieldWerx’s wafer-, lot-, and device-level analytics, manufacturers gain the ability to separate true device behavior from test interface variability, improving confidence in test outcomes and accelerating root-cause resolution.

About yieldWerx
yieldWerx provides a semiconductor yield management platform that enables manufacturers to collect, analyze, and act on production data across the manufacturing lifecycle. The platform consolidates data from wafer fabrication through final test, delivering visibility into product quality, process performance, and yield improvement opportunities.

About ModusTest
Modus Test, LLC was founded on the idea that there are creative ways to improve results by combining innovation with the best-known methods in test design and manufacturing. Providing innovative test solutions includes the MPT series of parametric tests, systems, and accessories. Modus Test has a global presence and the capability to support customers in all the IC development centers and high-volume manufacturing sites around the world. See for yourself how combining innovation with best-known methods can improve your results.

Statements from Leadership
“yieldWerx was built to unify disparate manufacturing data into actionable yield intelligence,” said Aftkhar Aslam, CEO of yieldWerx. “Valuable data exists across testers, handlers, sockets, MES systems, and inspection tools, but it often remains siloed. Our platform connects these domains into a unified analytical framework that enables faster, data-driven decisions that reduce costs.”

“This partnership represents an important step forward in bringing greater transparency and intelligence to semiconductor test,” said Jesse Ko, COO of Modus Test. “Modus Test’s high-performance socket validation solutions, combined with yieldWerx’s powerful analytics platform, create a closed-loop ecosystem where hardware performance and yield outcomes are fully correlated. Together, we are enabling a smarter, more adaptive test environment.”

For further information, please visit https://www.yieldWerx.com or https://www.ModusTest.org.