REGISTRATION
- Early-Bird Registration Deadline: Wed, July 9, 5PM (KST)
- Group Registration Deadline: Fri, July 4, 5PM (KST)
- Registration fee includes a boxed lunch provided at the venue.
[Group]
- SEMI Member : KRW 275,000
- Non Member: KRW 330,000
* Group registration fee applies to groups of five or more from the same company.
* For group registration inquiries, please contact SEMI Korea Program Team([email protected]).
[Early Bird]
- SEMI Member: KRW 308,000
- Non Member: KRW 363,000
[On site]
- SEMI Member: KRW 385,000
- Non Member: KRW 385,000
OVERVIEW
- Date: July 16(Wed), 2025
- Time: 09:00 - 17:00
- Venue: Convention Hall 2, 3F, Suwon Convention Center
- Language: Korean (Simultaneous interpretation will NOT be provided.)
- Organizer: SEMI Korea
SPONSORS
 |  |  |
 |  |  |
 |  |
NOTICE
- The agenda is subject to change at the discretion of the speakers.
- Presentation files agreed by speakers will be provided to attendees after the event through SEMI registration website.
CONTACT
- SEMI Korea Program Team ([email protected])
- Simultaneous interpretation will NOT be provided.
Convention Hall 2, 3F, Suwon Convention Center
South Korea
System Level Advanced Packaging
Rapidly evolving progress of AI and HPC has significantly increased computational and memory needs such as higher performance, lower power consumption, and wider memory bandwidth with reduced latency. An end application of AI/HPC comes down to Datacenter construction. Meeting the challenge of delivering this processing power in the datacenter requires systematic innovation from the device to the datacenter level. It starts with integrating highly optimized, domain-specific accelerators which should be integrated into advanced 2.5D and 3.5D packaging that minimize losses and power for high-speed communication while taking advantage of workload power management. AI computing introduces significant challenges for energy consumption and thermal management. Power delivery network is crucial for CPU, GPU and NPU power and performance of which solution can be DTC, IVR, mtal-insulator-metal (MIM) capacitor and thin film inductor, backside power rail, etc.. While Moore’s law has continued to yield transistor scaling necessary for these applications, the ever growing demand from models for AI training and inference pushes Si scaling in conjunction with the advent of advanced interconnects via disaggregation and reaggregation of chips in advanced packaging.
We will discuss with examples and the challenges of utilizing packaging elements to their full potential and discuss how co-optimization is crucial to achieving the best results for any given set of system requirements and constraints.
Advanced Packaging and Reliability: Technologies Shaping the Next Generation
Advanced semiconductor packaging is now central to enabling continued performance scaling as conventional transistor scaling slows. This seminar introduces cutting-edge trends in advanced packaging, including 2.5D and 3D integration, fan-out wafer-level packaging, chiplet-based architectures, and glass interposers for optical I/O in AI and HPC systems. These technologies offer enhanced performance, form factor reduction, and system-level integration capabilities critical for future computing platforms.
Leveraging prior industry experience, this talk highlights real-world applications and challenges in designing and qualifying advanced SoC packages. Examples include CoWoS-based AI chip packaging, hybrid bonding techniques, and thermal design optimization for high-power systems.
As packaging structures become increasingly complex, reliability emerges as a critical bottleneck. The seminar explores major failure mechanisms such as thermal-mechanical fatigue, electromigration, interfacial delamination, and Through Glass Via (TGV) degradation. Reliability analysis methods including FEA-based stress modeling, time-to-failure prediction, and advanced failure diagnostics will be introduced.
By combining packaging innovation with reliability engineering, the talk aims to provide a comprehensive perspective on the technological and practical issues that must be addressed to enable robust, high-performance semiconductor systems in the AI and data-driven era.
Pushing the Boundaries: Challenges and Opportunities in Panel-Level Packaging Technology
As the AI era progresses, semiconductor devices are increasingly adopting 3D architectures to boost performance and power efficiency. At the same time, system technology co-optimization (STCO) is advancing through the use of chiplets and advanced wafer-level packaging. As the industry integrates more chips into chiplets, the size of interposers continues to grow. However, wafer-level packaging faces limitations in accommodating large interposers due to the constraints of 300mm wafer shapes and temporary carriers.
This trend is driving a shift toward panel-level packaging (PLP) to support higher packaging unit counts. Despite its potential, PLP still faces significant challenges—particularly in terms of process development and process control.
This paper explores the technical trends in panel-level packaging, focusing on the current challenges and potential solutions related to process control.
Break
Panel Discussion
Presentation New Innovations Enabling Fine Pitch D2W Hybrid Bonding
Heterogenous integration and advanced packaging is behind the technology that is enabling today’s AI and high-performance computing. This is done through complex architecture that utilizes platforms including microbumps, through silicon vias (TSV), high density fanout and hybrid bonding (HB). The integration of chiplets using any combination of these technologies is allowing the industry to extend the Moore’s law and overcome limitations of the Von Neumann architecture. Hybrid bonding is an especially appealing technology that helps improve power and performance (higher I/O density), as well as thermal management. Sub-10 ㎛pitch die-to-wafer (D2W) HB is already in production1) for 3DIC and the industry working on HB technology for High Bandwidth Memory as well2). However, there are continuous challenges for D2W that require new innovation in both processing and metrology & inspection (M&I), and also unique challenges for both logic and memory applications specific to its integration. The presentation will discuss how logic and memory HB technologies are different and what process and M&I technologies are needed to facilitate HVM of the HB technology across different applications. Process challenges including low temperature bonding, die warpage management and dicing will be discussed, while M&I challenges include the transition to e-beam technology for HB enablement.
1) R. Agarwal et al., “3D Packaging for Heterogeneous Integration”, IEEE ECTC, July 2022
2) Lee et al., “A Study on D2W Cu Bonding Technology for HBM Multi-die Stacking”, IEEE ECTC, May 2024
Trend and Technology of Glass Package Substrate
Design and Development of High Thermal Conductive Molding Compounds for Advanced Packaging Applications
The ongoing miniaturization and increased integration density in electronic circuit systems, particularly in advanced technologies such as DRAMs for Through-Silicon Via (TSV) and High Bandwidth Memory (HBM), have elevated thermal management to a critical challenge in microelectronic packaging. The functional performance, operational lifespan, and reliability of electronic devices fundamentally depend on efficient thermal dissipation. As power densities escalate, enhancing the thermal conductivity of EMCs has become imperative for effective heat removal from increasingly complex electronic components. Consequently, research efforts focused on developing epoxy resins with superior thermal conductivity and identifying appropriate high-conductivity fillers represent the most viable approaches to addressing thermal management challenges in contemporary microelectronic systems.
Recently, we have successfully developed a high-performance epoxy molding compound (EMC) that solves critical thermal management challenges in advanced microelectronic packaging applications. Not only do these compounds provide extremely safe protection of integrated circuits from moisture, mobile ion contaminants and adverse environmental conditions, including temperature fluctuations, humidity and mechanical stress, but the enhanced thermal and mechanical properties of EMC formulations address the heat dissipation requirements of advanced technologies such as small electronic circuit systems, especially TSV and HBM applications.
Next-Generation Thermal Strategies: The Liquid Cooling Revolution for AI Chips
Break
Panel Discussion
Next-generation semiconductor packaging technologies are advancing rapidly in response to the explosive growth of high-performance semiconductor markets, including AI chips and HBM. At the Advanced Packaging Summit 2025, industry leaders from top global companies will share the latest developments and insights in advanced packaging technologies. The morning session will spotlight core technologies such as SLP and PLP, while the afternoon session will feature in-depth presentations on essential next-generation packaging technologies including hybrid bonding, glass substrates, materials for heat control, and liquid cooling solutions. Each session will also include panel discussions to encourage broad and practical exchanges of technical experiences, offering valuable opportunities for networking. We invite you to explore the future direction of next-generation semiconductor packaging with global industry experts and expand both your insights and business horizons at this premier event.
