10:00 am -10:50 am 반도체 산업 현황
10:50 am - 11:05 am Break
11:05 am - 12:15 am 반도체 소자 구조 및 동작 원리
12:15 am - 2:00 pm Lunch
2:00 pm - 3:10 pm 실리콘 칩 제작 공정
3:10 pm - 3:25 pm Break
3:25 pm - 4:35 pm 실리콘 칩 제작 공정

※ 연사정보

최근 반도체 산업은 초고속, 저전력, 고집적 등 메모리 소자의 성능을 향상시키기 위한 방향으로 연구 개발을 활발하게 추진하고 있습니다. 반도체 소자를 실제로 구현하고 제품으로 만들어 내는 반도체 제조 공정은 웨이퍼 제조부터 패키징까지의 모든 단계를 포함하며 기술 혁신을 통한 반도체 칩 성능의 극대화를 위해 새로운 소재 도입 및 장비 개발과 함께 기존 소자의 구조를 개선하는 등의 다양한 방면으로 연구를 병행하고 있습니다.
본 강의는 먼저 반도체 산업의 특징 및 글로벌 반도체 산업 생태계 동향 파악과 함께 웨이퍼 위에 회로를 새기는 과정인 전공정 (Front-end Process), 완성된 칩을 보호하고 테스트하는 과정인 후공정 (Back-end Process) 을 포함한 반도체 제조 공정의 전반적인 내용에 대해 간단하게 살펴보고 이후 Thin Film 공정의 기본 개념 및 용어와 함께 해당 공정의 증착 방법, 각 증착 물질의 특징과 장단점에 대해 이해하고 이를 바탕으로 특히, Dielectric, Metal 물질별 응용 사례를 파악하여 Thin Film 공정에 대한 이해도를 높이는 과정입니다.

※ 연사정보

최근 반도체 집적도가 증가하면서 Patterning 공정에 대한 난이도 역시 급격히 증가하고 있다. 특히 2D 및 3D Patterning을 모두 담당하는 Etching 공정의 중요성은 그 어느 때 보다도 높아진 상황이다.
본 강의에서는 Etching process를 구현하는데 필수적인 Plasma physics 및 engineering을 소개하고, Etching mechanism 및 주요 물질 별 Etching chemistry, 차세대 Etching 기술 트렌드 등을 조망하고자 한다.

※ 연사정보

Rapidly evolving progress of AI and HPC has significantly increased computational and memory needs such as higher performance, lower power consumption, and wider memory bandwidth with reduced latency. An end application of AI/HPC comes down to Datacenter construction. Meeting the challenge of delivering this processing power in the datacenter requires systematic innovation from the device to the datacenter level. It starts with integrating highly optimized, domain-specific accelerators which should be integrated into advanced 2.5D and 3.5D packaging that minimize losses and power for high-speed communication while taking advantage of workload power management. AI computing introduces significant challenges for energy consumption and thermal management. Power delivery network is crucial for CPU, GPU and NPU power and performance of which solution can be DTC, IVR, mtal-insulator-metal (MIM) capacitor and thin film inductor, backside power rail, etc..  While Moore’s law has continued to yield transistor scaling necessary for these applications, the ever growing demand from models for AI training and inference pushes Si scaling in conjunction with the advent of advanced interconnects via disaggregation and reaggregation of chips in advanced packaging.  
We will discuss with examples and the challenges of utilizing packaging elements to their full potential and discuss how co-optimization is crucial to achieving the best results for any given set of system requirements and constraints.

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※ 연사정보

Advanced semiconductor packaging is now central to enabling continued performance scaling as conventional transistor scaling slows. This seminar introduces cutting-edge trends in advanced packaging, including 2.5D and 3D integration, fan-out wafer-level packaging, chiplet-based architectures, and glass interposers for optical I/O in AI and HPC systems. These technologies offer enhanced performance, form factor reduction, and system-level integration capabilities critical for future computing platforms.
Leveraging prior industry experience, this talk highlights real-world applications and challenges in designing and qualifying advanced SoC packages. Examples include CoWoS-based AI chip packaging, hybrid bonding techniques, and thermal design optimization for high-power systems.
As packaging structures become increasingly complex, reliability emerges as a critical bottleneck. The seminar explores major failure mechanisms such as thermal-mechanical fatigue, electromigration, interfacial delamination, and Through Glass Via (TGV) degradation. Reliability analysis methods including FEA-based stress modeling, time-to-failure prediction, and advanced failure diagnostics will be introduced.
By combining packaging innovation with reliability engineering, the talk aims to provide a comprehensive perspective on the technological and practical issues that must be addressed to enable robust, high-performance semiconductor systems in the AI and data-driven era.

※ 연사정보

As the AI era progresses, semiconductor devices are increasingly adopting 3D architectures to boost performance and power efficiency. At the same time, system technology co-optimization (STCO) is advancing through the use of chiplets and advanced wafer-level packaging. As the industry integrates more chips into chiplets, the size of interposers continues to grow. However, wafer-level packaging faces limitations in accommodating large interposers due to the constraints of 300mm wafer shapes and temporary carriers.
This trend is driving a shift toward panel-level packaging (PLP) to support higher packaging unit counts. Despite its potential, PLP still faces significant challenges—particularly in terms of process development and process control.
This paper explores the technical trends in panel-level packaging, focusing on the current challenges and potential solutions related to process control.

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Abstract - Heterogenous integration and advanced packaging is behind the technology that is enabling today’s AI and high-performance computing. This is done through complex architecture that utilizes platforms including microbumps, through silicon vias (TSV), high density fanout and hybrid bonding (HB). The integration of chiplets using any combination of these technologies is allowing the industry to extend the Moore’s law and overcome limitations of the Von Neumann architecture. Hybrid bonding is an especially appealing technology that helps improve power and performance (higher I/O density), as well as thermal management. Sub-10 ㎛pitch die-to-wafer (D2W) HB is already in production1) for 3DIC and the industry working on HB technology for High Bandwidth Memory as well2). However, there are continuous challenges for D2W that require new innovation in both processing and metrology & inspection (M&I), and also unique challenges for both logic and memory applications specific to its integration. The presentation will discuss how logic and memory HB technologies are different and what process and M&I technologies are needed to facilitate HVM of the HB technology across different applications. Process challenges including low temperature bonding, die warpage management and dicing will be discussed, while M&I challenges include the transition to e-beam technology for HB enablement.

1) R. Agarwal et al., “3D Packaging for Heterogeneous Integration”, IEEE ECTC, July 2022
2) Lee et al., “A Study on D2W Cu Bonding Technology for HBM Multi-die Stacking”, IEEE ECTC, May 2024

※연사정보

The ongoing miniaturization and increased integration density in electronic circuit systems, particularly in advanced technologies such as DRAMs for Through-Silicon Via (TSV) and High Bandwidth Memory (HBM), have elevated thermal management to a critical challenge in microelectronic packaging. The functional performance, operational lifespan, and reliability of electronic devices fundamentally depend on efficient thermal dissipation. As power densities escalate, enhancing the thermal conductivity of EMCs has become imperative for effective heat removal from increasingly complex electronic components. Consequently, research efforts focused on developing epoxy resins with superior thermal conductivity and identifying appropriate high-conductivity fillers represent the most viable approaches to addressing thermal management challenges in contemporary microelectronic systems.
Recently, we have successfully developed a high-performance epoxy molding compound (EMC) that solves critical thermal management challenges in advanced microelectronic packaging applications. Not only do these compounds provide extremely safe protection of integrated circuits from moisture, mobile ion contaminants and adverse environmental conditions, including temperature fluctuations, humidity and mechanical stress, but the enhanced thermal and mechanical properties of EMC formulations address the heat dissipation requirements of advanced technologies such as small electronic circuit systems, especially TSV and HBM applications.

※ 연사정보

※ 강사정보

※ 강사정보

※ 강사정보

As the era of lateral shrink is coming to a cliff, the need for looking at the remaining axis is uprising - the Z-axis. For DRAM, the introduction of vertical channel is very near, and even the introduction of a full 3D-DRAM is not far away. Fortunately, we have experience of VNAND, which could tell us many things about the difficulties following the 3D stacking structures. Starting from the change in the material we've gone through regarding the conversion of planar to vertical NAND, prospection of the material innovation for 3D-DRAM will be shared. The introduction of materials for the construction of deep holes and lengthy lines will be addressed. Also, needs for innovative sacrificial and auxiliary materials will be presented.

※ 연사정보

As DRAM scaling approaches fundamental limits, advanced architectures such as 3D DRAM and 4F² DRAM have emerged as promising solutions. The industry initially anticipated the adoption of these technologies around the 1d to 0a nm nodes; however, they remain in development, with mass production likely postponed until the 0b node. For instance, current 3D DRAM samples feature 8–12 layers, while the target is approximately 90 layers. Recent advancements include 3D DRAM with vertical bit-line architecture, demonstrating improved on-current performance and gate control through 5-layered cell stacks utilizing Si/SiGe sacrificial layers and hybrid bonding. Meanwhile, novel 4F² DRAM transistor structures exhibit enhanced operational margins and mitigate floating body effects through dual-gate designs. Additionally, a 3D stackable DRAM architecture with horizontally stacked transistors has been proposed to address challenges such as gate-induced drain leakage (GIDL) and row hammer effects, supported by both experimental and simulation results. Collectively, these innovations underscore the potential of 3D and 4F² DRAM as next-generation solutions to overcome scaling bottlenecks and meet the growing demand for high-density, low-power memory.

※ 연사정보

The development of semiconductor technology can be continuously achieved through the collaboration of materials, processes, devices, and systems, and 3D devices and 3D integration process technologies will be essential in the future. From this perspective, the structural change of semiconductor transistors is expected to evolve from the current Gate-All-Around FET (GAAFET) to a new Complementary FET (CFET) device. This structural change of semiconductor devices requires new materials and process technologies. Various technologies are required, such as Monolithic or Sequential 3D integration, Si/Si or Si/Non-Si substrates, new low-resistivity metals, CMP, Bonding, TSV, and Back-Side Power Network Delivery (BSPDN). In this presentation, we will examine the technological trends from the materials and process perspectives for the development of CFET device technology.

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For the past six decades, hazardous gas hydrides like GeH4, Si2H6, and B2H6 have been essential to the semiconductor industry. Their high reactivity, strong reducing power, and ability to grow high-quality, carbon-free layers have made them vital for applications ranging from Si and SiGe epitaxy to tungsten metallization. In recent years, new applications and integration schemes have emerged, demanding higher-performance hydride sources for low-temperature Chemical Vapor Deposition (CVD) and epitaxy. This increased global demand drives production investments, despite the challenges of handling, facilitating, and logistics constraints such as limited shelf-life, pyrophoricity, and toxicity. In this talk, we will provide an overview of the current gaseous hydrides landscape and its challenges. We will discuss how the gas industry can ensure the semiconductor industry's continued safe access to these critical materials through enhanced stewardship, optimized supply chains, packaging, and manufacturing techniques. Furthermore, we will provide insights into technology trends towards new-generation, extra-low-temperature epitaxy and high dopant sources, and their potential use in future transistor architectures.

Emergence of artificial intelligence (AI) is predicted to drive global chip sales to ~$1 trillion revenue by 2030. This surge of AI-targeted chip demand is driving ever-increasing requirement in compute speed to >109 petaFLOPS. High-bandwidth memory (HBM) architecture is well-suited to fulfill this requirement, currently offering >1TB/s bandwidth. To continue improving HBM performance, materials engineering innovations are required in critical packaging building blocks, such as TSV and Hybrid Bonding. Solutions from equipment manufacturer standpoint were presented, in relation to TSV gapfill, low-temperature (<300˚C) hybrid bonding enablement, and bond strength consideration for higher I/O count in the future. Timely solutions to the dynamic HBM integration challenges should be seen holistically and to this end, active partnerships and collaboration across the ecosystem are encouraged.

※ 연사정보

The semiconductor industry continues to advance, propelled by growing demand for AI-driven computing and storage technologies and diverse digital applications. However, this growth is tempered by rising economic uncertainty and escalating trade tensions, particularly due to recent U.S. tariff policies, which threaten to disrupt global supply chains. The semiconductor materials sector faces multifaceted challenges, including increasing rapid technological innovation, geopolitical volatility, large-scale capacity expansions and climate change actions. While the market remains relatively stagnant in 2024 compared to 2023, a rebound is anticipated in 2025–2026, driven by long-term demand for advanced computing and storage solutions. A shifting supplier landscape is emerging, marked by the rise of regional players—notably in China—and consolidation among multinational corporations pursuing economies of scale through mergers and acquisitions. Geopolitical pressures are driving localization and dual sourcing, which raise costs, reduce efficiency, and complicate supply chains. This talk highlights the need for a delicate balance between innovation-driven growth and the escalating operational challenges in the semiconductor materials industry.

※ 연사정보

As the commercialization of artificial intelligence (AI) and the advancement of technologies such as high-performance computing (HPC) and deep learning (DL) progress, the need to process large amounts of data quickly has emerged. Traditional DDR and GDDR memory have limited bandwidth, so HBM, which offers higher performance, has been commercialized, driving the development of new technologies.
Compared to traditional memory chips, HBM has increased chip size and higher defectivity vulnerability due to chip stacking processes. This has led to new technical approaches for wafer defectivity control across the entire material ecosystem.
This presentation reviews the latest trends in filtration/purification technologies aimed at minimizing the impact of particles and impurities in this material ecosystem. By examining current HVM devices and next-generation HBM-related technologies, we aim to contribute to wafer defect control.

※ 연사정보

As semiconductor manufacturers continue the vertical scaling of 3D memory devices, advanced metrology and process control strategies are becoming increasingly essential for maintaining yield and reliability. The rising aspect ratios (AR > 100) of device features present significant challenges for conformal thin-film deposition via atomic layer deposition (ALD). Ultra-thin dielectric films and multilayer stacks—widely used in 3D memory channel holes—are particularly sensitive to process variations. Even minor deviations in ALD process conditions can result in non-uniform film coverage, defect formation, or electrical performance issues, all of which are difficult to detect and monitor within high-aspect-ratio structures.
To address these challenges, Chipmetrics has developed a novel method based on lateral ultra-high-aspect-ratio test structures (PillarHall®) for ALD process development, monitoring, and tool qualification. In the PillarHall® test wafers, the aspect ratio exceeds 1000, enabling practical and non-destructive measurement of film conformality. The method offers a sensitive and scalable solution for improving ALD process qualification, benchmarking tool performance, and enhancing production stability.
This presentation will highlight recent advancements in PillarHall® technology, with a focus on its application in ALD tool qualification and ALD process window control.

※ 연사정보

There have been lots of technical advances in the fileld of semiconductor industry for the last dacades ever since DRAM and NAND were invented and commercialized. Meanwhile, form factor was changed from 8F2 to 6F2 in DRAM, and the concept of 3D stacking was adopted in NAND flash memory. Furthermore, EUV tool has been adopted and are being successfully used to make the fine pattern in logic and DRAM as well. And also, it has been very long since ALD was taken as a new advanced depostion technology to meet the need for excellent conformality. But all these new process technologies couldn’t have been possible without the advances in process materials such as advanced photo resist, precursors, functional chemicals and CMP slurries. Recently, those process materials are beginning to open the new possibilities for the innovation of process integations, resulting in cost reduction and giving an extra performance to the process tools. In this talk, the role, the current issues and future challenges will be discussed focusing on the process materials in semiconductor industry.
Starting from photo resist, thin and etch resistant resist has been cosistantly required to suppress the pattern collapse and wiggling during the patterning process. Since the EUV was adopted in DRAM and Logic, high sensitivity EUV resist is now being intensively explored to obtain low DtS as well as good CD uniformity to make the best use of the enomoursly high-priced EUV tool in a cost effective way. For the sake of that, even metal-containing resist is also being tried for high quality patterning. Additionally, thick KrF resist is also required at 3D NAND flash memory with the increase of ON stack and especially for the new platform to be. And for the future, the new concept of PR based on small sized polymer will be worth trying and dry type developer would be also necessary to keep the pattern stable without collapse or wiggling.
With regard to the wet chemicals and CMP slurries, advanced functional chemicals are getting more and more important rather than convetnional cleaning chemicals that are used after etch and CMP process. W or Mo recess chemical in 3D NAND would be that very case. Those chemicals should assure the good uniformity in terms of recess amount in the vertical direction. Most of all etch and CMP prcesses need post cleaning steps to clean the residue, but during that, some unwanted part of the surroundings is apt unavoidably to be removed deteriorating the device proformance in the end. Therefore, special clean chemical will be also needed to minimize the unwanted film loss as well as residue removal. When it comes to the slurry, the shape of the abbrasive particles consistently has been changing from sharp and pointed to the rounded one by adopting colloidal synthesis to suppress the scratch during CMP. The size of the abrasive particle tends to get smaller but slurry is required to make up the decreased removal rate by properly regulating components within slurry. With the change of material to be polished such as Mo or Carbon, new slurry for those new materials will be a new drive for CMP related materials.
Precursor and some functional gases have been contributing to the quality improvement or deposition modication of functional materials such as high-k materials in DRAM. As always, there should be more technical areas, in which precursor and gas will be able to play an important role in ASD(Areal Selective Deposition) or ALE(Atomic Layer Etching) process.
Since process materials needs to be considered from the operation of FAB line unlike the process tools, it must be managed well from the aspect of consistent quality control and risk management of supply chain and safety. In the past, process material used to play a simple and supporting role in the process and tools as well. But now, it is becoming a time for the process materials to play a more active role in cost reduction and risk management as well as providing technology for semiconductor industry. Especially, new process materials are also required to meet the needs for low carbon emission during the process and safety issues from the using PFAS containg materials that are hazardous to human body. Way of doing work needs to be also changed in a way that R&D activities have to be shifted to the earlier engagement. And plus, the collaboration between device maker and process material supplier shoud be much closer and earlier than before so that the developed materials can be successfully adopted at a targeted process and a tool for it. As the material supply chain has been becoming very unstable since corona pandemic and US-China trade conflict, it needs to be managed with a good predictability and balance as well in order for consistent and stable supply in case of unexpected issues at a supply chain.

※ 연사정보

10:00 am - 10:50 am 반도체 산업 현황
10:50 am - 11:05 am Break
11:05 am - 12:15 pm 반도체 소자 구조 및 동작 원리
12:15 pm - 2:00 pm Lunch
2:00 pm - 3:10 pm 실리콘 칩 제작 공정
3:10 pm - 3:25 pm Break
3:25 pm - 4:50 pm 실리콘 칩 제작 공정

※ 연사정보

본 강의는 최신 반도체 제조 기술 중 하나인 3나노미터(3nm)급 공정을 기반으로 한 GAA(GateAll-Around) MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor) 소자에 대한 구조와 동작 이해를 중점으로 다룬다. 최근 발표된 연구 기술과 논문을 기반으로 반도체 소자의 연구 동향과 기술적인 이슈를 탐구한다.

※ 연사정보

현재 전기 전자 산업에서 폭넓게 사용되고 있는 Silicon material의 경우, 낮은 가격으로 고순도의 Silicon을 제작할 수 있고 150mm부터 450mm까지 다양한 Size로 단결정 (Single Crystal)을 성장시킬 수 있다는 장점 때문에 반도체 산업에서 널리 사용되고 있다. 특히 Silicon wafer의 경우, 1916년 Czochralski에 의해 처음으로 단결정 성장 방법이 개발된 이후, 1982년 Vladimir V. Voronkov에 의해 점 결함의 거동 (behaviors of point defects, vacancies and self-interstitials)이 이론적으로 확립되면서 급속도로 그 사용 빈도가 높아지기 시작하였다. 이러한 Silicon wafer의 제작 방법은 크게 Ingot을 성장시키는 growing process와 얇은 원판 형태로 가공하는 wafering process로 나뉘어 설명할 수 있다. 본 강의에서는 Silicon ingot을 성장시키는 growing process와 Wafer의 형상 제어를 목적으로 하는 shaping process, Wafer 표면의 경면을 목적으로 평탄도를 제어하는 Polishing proces, 마지막으로 청정도 제어 목적의 Cleaning process를 포함하는 wafering process 설명을 통해 전반적인wafer 제조 process에 대한 이해를 높일 예정이다. 또한 Silicon wafer의 metrology 를 Crystal, Surface, Electrical, Contamination 관점에서 설명함으
로써 분석 방법 및 영역에 대한 포괄적 이해를 돕고자 한다.

※ 연사정보

반도체 회로 패턴이 점점 미세화 되면서 반도체 소자를 형성하기 위한 공정 진행 방법 또한 점점 어려워지고 복잡해지고 있다. 특히 반도체 제품의 Pattern Shrinkage, SPT/DPT 공정의 확대, 구조변화 등에 따라 다양한 형태의 불량들이 발생할 뿐만 아니라 불량 Size 또한 더욱더 작아지고 있어 제조 공정 과정에서 발생되는 문제점을 빠르고 정확하게 확인할 수 있는 In-line 계측 기술에 대한 요구가 높아지고 있다. 본 강의에서는 반도체 제조 공정 과정에서 사용되는 Metrology & Inspection 분야의 중요 장치들의 기본적인 작동 원리와 종류를 알아보고, 각 장비들의 활용 사례를 통하여 공정상의 문제점 파악과 해결 방법들을 살펴보고, 향후 신제품 대응에 필요한 차세대 Metrology & Inspection Tools의 개발 Trend에 대해서 다루고자 한다.

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리소그래피(Lithography, 노광 공정)는 반도체 공정에서 회로를 구성하기 위한 밑그림을 그리는 단계로 반도체 소자의 집적도를 결정한다. 설계된 반도체 회로를 스캐너 등의 노광 장치를 이용해 웨이퍼 위에 도포한 감광제로 패턴을 전사해 구현하는 공정이다. 본 강의에서는 리소그래프 공정에 대한 기본 개념을 소개하고 마스크, OPC(Optical Proximity Correction), 스캐너 노광 장치, 감광제의 작동 원리를 설명하고 미세 패턴 형성을 위한 차세대 노광 기술에 대해 소개한다.

※ 연사정보

반도체 소자의 고속화 및 고집적화에 따라 다층배선구조에 있어서 배선층수의 증가와 패턴의 미세화에 대한 요구가 여전히 높다. CMP (Chemical Mechanical Planarization)는 미세패턴을 형성하기 위한 노광장치의 Depth of focus가 작아지면서 광역평탄화를 실현하기 위해 도입되었는데, 현재는 STI, Cu damascene 등 패턴형성 및 TSV 같은 packaging 쪽에도 사용되고 있어 그 중요성이 나날이 커지고 있다. Cleaning은 Particle, Metal, Polymer, Organic contamination, Native Oxide 및 Damaged Layer 등과 같은 Wafer 상의 원하지 않는 물질들을 제거하여, Device Yield를 감소시키는 노광 불량, Gate Oxide 불량, 전기적 접촉저항 불량 및 배선의 단락 등과 같은 결함을 제어하는 모든 공정을 의미한다. 패턴 미세화에 따라 난이 도가 급격히 증대되어 패턴손상 없는 새로운 세정공정개발의 필요성이 커지고 있다. 본 강 의에서는 CMP 및 cleaning의 기본 개념과 필수 구성요소를 장비와 재료 측면에서 살펴보고, 차세대 CMP 및 cleaning의 방향에 대해서 다루고자 한다.

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Doping 및 Diffusion 공정 (Implantation, Annealing, Oxidation, Nitridation, Deposition)은 지난 50 년간 핵심 반도체 제조 기술로서 고성능 소자 제작을 위해 사용되어 왔으며, 현재도 새로운 기술로서 진화하고 있다. 본 중급 과정에서는 각 공정에 대한 기초, 심화, 응용에서부터 차세대 공정까지 폭넓게 다룰 예정이다. Ion implantation 에서는 목적, 장단점, Hardware 구성, Process 응용, Doping profile, Channeling, Defect, TED, 신기술에 대해 소개한다. Annealing 에서는 목적, 종류 (sRTA, fRTP, LSA), Activation, Junction 조절, 장비 종류 및 Hardware 구성에 대해 소개한다. Oxidation 에서는 산화 Kinetics, 산화막 물성, Defect/Charge, 다양한 산화 방식(Dry, Wet, Plasma, Radical)과 장비에 대한 소개가 이루어진다. Nitridation 에서는 방식(Thermal, Plasma)에 따른 N profile, 소자 특성, 장비에 대해 다룬다. Deposition (LPCVD, ALD) 에서는 증착 Kinetics, 분류 방식, 다양한 박막 종류 (Poly Si, SiO2, Si3N4, SiON, Metal) 및 공정 응용에 대해 소개할 예정이다.

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반도체 패키지란 전공정에서 만들어진 웨이퍼를 실제로 전자 제품 속에서 활용할 수 있는 반도체 소자로 만들어 주는 중요한 후공정 단계라고 볼 수 있다. 그렇기 때문에 반도체 패키지 기술은 우 리가 많이 사용하고 있는 스마트폰이나 웨어러블 등과 같은 IT분야 뿐만이 아닌 의료분야, 농업 분야 등 전자 기기가 사용되는 모든 산업 분야에 걸쳐 최종사용자의 기기 모양과 기능에 커다란 영 향을 끼치게 되는데, 전자 기기에 들어가는 반도체 소자가 고속, 저전력, 다기능화, 소형화 등이 요구됨에 따라 그를 뒷받침해 주는 반도체 패키지 기술의 중요성도 커지고 있다. 본 강의에서는 반도 체에서 패키지가 어떤 역할을 하는지 알아보고, Substrate를 이용해서 만들어지는 일반적인 반도체 패키지 공정과 flip chip, WLCSP 등의 웨이퍼 레벨 패키지 기술에 대해서도 소개한다. 더불어, TSV를 비롯한 3D 적층 패키지 기술에 대해서 장단점을 논의하고, 최신 패키지 기술 trend 등을 주로 다루게 될 것이다.

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최근 반도체 산업은 초고속, 저전력, 고집적 등 메모리 소자의 성능을 향상시키기 위한 방향으로 연구 개발을 활발하게 추진하고 있습니다. 반도체 소자를 실제로 구현하고 제품으로 만들어내는 반도체 제조 공정은 이를 위해 새로운 기술 및 소재의 개발과 함께 기존 소자의 구조를 개선하는 등의 다양한 연구를 병행하고 있습니다.본 강의는 Thin Film 공정의 기본 개념 및 용어와 함께 해당 공정의 증착 방법, 각 증착 물질의 특징과 장단점에 대해 이해하고 이를 바탕으로 특히, Dielectric, Metal 물질 별 응용 사례를 파악하여 Thin Film 공정에 대한 이해도를 높이는 과정입니다.

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최근 반도체 집적도가 증가하면서 Patterning 공정에 대한 난이도 역시 급격히 증가하고 있다. 특히 2D 및 3D Patterning을 모두 담당하는 Etching 공정의 중요성은 그 어느 때 보다도 높아진 상황이다. 본 강의에서는 Etching process를 구현하는데 필수적인 Plasma physics 및 engineering을 소개하고, 기본적인 Etching mechanism 및 주요 물질 별 Etching chemistry, 차세대 Etching 기술 트렌드 등을 조망하고자 한다.

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