downloadGroupGroupnoun_press release_995423_000000 copyGroupnoun_Feed_96767_000000Group 19noun_pictures_1817522_000000Member company iconResource item iconStore item iconGroup 19Group 19noun_Photo_2085192_000000 Copynoun_presentation_2096081_000000Group 19Group Copy 7noun_webinar_692730_000000Path
Skip to main content
Default Banner Image

China

Breker Verification Systems and Moores Lab AI Partner to Create First AI-Driven SoC Verification Solution
• Test Suite Synthesis, agentic AI integration will enable automated specification test generation across range of SoC designs on varied verification platforms
• AI-driven synthesis verification flow prototype to be demonstrated during DVCon U.S. in March
• Joint Breker, Moores Lab AI reception at DVCon U.S. Monday evening followed by AI in verification panel
SAN JOSE, CALIF.––February 26, 2026––Breker Verification Systems and Moores Lab AI today formalized a partnership to create the first AI-driven SoC verification flow integrating Breker’s Trek Test Suite Synthesis with Moores Lab agentic AI technology.

The solution leverages Breker’s vast experience in test generation for complex system design scenarios with the agentic AI VerifAgent™ product from Moores Lab AI. It seamlessly enables automated multicore, multitool, C or transaction level modeling (TLM) test generation for complex SoC scenarios from manually composed specifications.

The flow uses agentic AI to read a specification and generate appropriate scenario models for test synthesis that will produce combined C and SystemVerilog tests that can be run on simulation and emulation platforms targeting high-coverage SoC scenarios.

A prototype of the AI-driven verification flow will be demonstrated in Breker’s Booth (#203) and the Moores Lab AI Booth (#101) during DVCon U.S. March 2 through March 4 at the Hyatt Regency in Santa Clara.

“SoC verification requires highly complex scenario tests that find unpredictable corner cases across advanced, multi-core architectures,” says David Kelf, CEO of Breker Verification Systems. “The Moores Lab AI VerifAgent technology is an excellent complement to our proven Trek synthesis products that leverages our deep verification experience to drive the first AI SoC verification solution.”

“Breker has long been a pioneer in portable stimulus and system-level verification innovation,” notes Shelly Henry, CEO of Moores Lab AI. “Integrating VerifAgent with the Breker solutions creates a powerful synergy that enables engineering teams to verify increasingly complex silicon much faster and with greater confidence. We’re excited to partner with Breker to bring AI-driven transformation to SoC-level verification workflows.”

Combining Test Suite Synthesis with Agentic AI
Test Suite Synthesis generates high coverage tests efficiently for complex SoC-specific scenarios using various verification approaches, while agentic AI can accelerate the understanding of specifications to automatically derive verification plans and scenario models.

Combining the two can drive an automated verification solution that enables test generation for complex SoC scenarios from a manually composed specification that may be applied across a broad range of designs on varied verification platforms.

Availability
The AI-driven verification flow will be developed throughout 2026.

For more information, visit: http://www.breker.com or [email protected], or www.mooreslab.ai or [email protected].

Breker and Moores Lab AI at DVCon U.S.
In addition to the AI-driven verification flow prototype, Breker will exhibit and demonstrate its RISC-V CoreAssurance and SoCReady SystemVIP and Trek Test Suite Synthesis solutions at DVCon U.S. To arrange a demonstration or private meeting, send email to [email protected].

Moores Lab AI will showcase the VerifAgent product and discuss its product roadmap for agentic AI-driven silicon engineering at DVCon U.S. Email [email protected] to schedule an on-site meeting.

On Monday, March 2, Breker and Moores Lab AI will host an evening reception at DVCon in the Hyatt Regency Hotel Cypress room beginning at 6:30 p.m. and followed by a panel discussion on AI-driven SoC verification.

About Breker Verification Systems
Breker Verification Systems solves complex semiconductor challenges across the functional verification process from streamlining UVM-based testbench composition to execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions that provide test content portability and reuse. Breker’s solutions include a SystemVIP library of scenarios for RISC-V and Arm, core and SoC testing, coherency, security and other critical areas. Breker solutions easily layer into existing environments and operate across simulation, emulation, prototyping, and post-silicon execution platforms. Its Trek family is production-proven at leading semiconductor companies worldwide and enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easy verification knowledge reuse. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), privately held Breker has a reputation for dramatically reducing verification schedules in advanced development environments. Case studies that feature Analog Devices, Broadcom, IBM and other companies leveraging Breker’s solutions are available on the Breker website.

Engage with Breker at:
Website: https://www.brekersystems.com/
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/
X: @BrekerSystems

About Moores Lab AI
Moores Lab AI is building the next generation of AI tools for semiconductor design and verification. Its agentic AI platform transforms the chip development lifecycle by drastically reducing engineering time and cost, without changing existing flows, tools, or documentation. Moores Lab AI is headquartered in Austin, Texas, and proudly develops its products entirely in the United States.

For more information, visit www.mooreslab.ai or on social media:
LinkedIn: https://www.linkedin.com/company/mooreslabai/
X: @MooresLabAI

China India Japan Malaysia Singapore Taiwan Vietnam Chiplet & Heterogeneous 6/30 Training

Course Description 

This workshop reviews the needs of the packaging solution to meet the demand for digitalization through the artificial intelligent and Internet-of-things from urbanization, sustainability to industry. The course provides an overview of the fabrication process of IC carriers of leadframe, ceramics, substrate and flex and how they have to evolve to meet the heterogeneous integration. With these foundations, various stacking and integration technologies through wirebonding, flip chip and 3D interconnect from interconnect to system level will be shared. Packaging innovation of TSV, fan-in, fan-out wafer level packaging and its challenges will also be shared for chiplet and heterogeneous integration. It ends off by sharing the embedded technologies and embedded multi-die interconnect bridge for chiplet and heterogeneous integration.

The course looks into the R&D development as well as the dynamics changes of heterogeneous integration technologies in the Semiconductor packaging arena. This workshop curates the technologies development to date and provides the necessary information for professionals in the manufacturing and R&D environment to perform their tasks.

Who Should Attend

This course is intended for both manufacturing and R&D know-how in IC packaging professionals, including but not limited to:

  • Directors
  • Managers
  • Process Engineers
  • R&D Engineers
  • Sales and Application Engineers who supply packaging materials and tools

Learning Objectives

  • Understand why chiplet and heterogeneous integration for advanced packaging
  • Review of IC carriers
  • Summarize 3D and TSV for Chiplet and Heterogeneous Integration
  • Explain Fan-in and Fan-out wafer-level packaging for chiplet and heterogeneous integration
  • Describe chiplet, embedded, and embedded multi-die interconnect beam for chiplet and glass substrate for heterogenous integration 

Instructor

Dr. Lee Teck Kheng

Institue of Technical Education

Instructor Bio

Testimonials 

See what previous course participants had to say about this training!

  • "All the necessary information are neatly fitted into a few slides prepared by Dr. Lee"
  • "I found the review of the material between sessions and the slides to follow along with to be the most beneficial aspects of the training."
  • "Much thanks to Dr. Lee & SEMI University for giving me a chance to study all my unclear items in the past."

Important Information

Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access course knowledge. 

Can't find the training link day of? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders about 24 hours in an advance and an hour before with the same link. Please keep these emails on hand to access the trainings on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.

Singapore

SEMI U

Chiplet and heterogeneous integration of packaging has been embraced as the next revolutionary innovation to meet the quest of size, cost, and performance for packaging. The technologies are seen as another disruptive technology to bring devices into a package by integrating the various Multi-chip module (MCM), 3D packaging, Through Silicon Via (TSV), and Fan-out wafer level packaging (Fo-WLP) technologies into a system in the package for applications. Chiplet, EMIB, and glass substrate will also be shared in this course. 

Pricing
  • Members: $599
  • Non-Members: $649

* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected]

8:30 am - 5:00 pm Off Add to Calendar 2026-06-30 08:30:00 2026-06-30 17:00:00 Chiplet and Heterogeneous Integration for Microelectronics Packaging (Asia) Chiplet and heterogeneous integration of packaging has been embraced as the next revolutionary innovation to meet the quest of size, cost, and performance for packaging. The technologies are seen as another disruptive technology to bring devices into a package by integrating the various Multi-chip module (MCM), 3D packaging, Through Silicon Via (TSV), and Fan-out wafer level packaging (Fo-WLP) technologies into a system in the package for applications. Chiplet, EMIB, and glass substrate will also be shared in this course. PricingMembers: $599Non-Members: $649* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected] Singapore SEMI.org [email protected] Asia/Singapore public Asia/Singapore Register Now
Event format
Promote in calendar
Off

Registration Details

Registration is required for this event as it is likely to reach maximum room capacity, at which point interested attendees will be waitlisted.

SEMI Members:  $150

Non-Members of SEMI:  $200

Refunds possible before May 1, 2026.  Substitutions allowed up to May 20.

Questions? Contact James Amano at [email protected].

Belgium China France Germany India Ireland Italy Japan Singapore South Korea Taiwan United States 2026 EHS Summit Banner Business Executive Technical

The Summit includes strategic business and technical information for many levels and sectors of the ecosystem, including:

  • Government relations/advocacy staff
  • EHS regulatory professionals
  • Senior executives
  • Business development
  • Device manufacturers
  • Equipment suppliers
  • Materials suppliers
  • Component suppliers
  • Fab and facility systems construction companies

SEMI
673 South Milpitas Blvd.
Milpitas, CA 95035
United States

8:30 am

Badge Pickup and Networking

9:00 am
Joe Stockunas
Joe Stockunas
President, SEMI Americas
SEMI

Welcome and Introduction

9:05 am
James Amano
James Amano
Senior Director, EHS
SEMI

SEMI EHS Overview

9:20 am
Russ Lamotte
K. Russell LaMotte
Principal
Beveridge & Diamond, PC

US Regulatory Landscape: PFAS, PIP, TTR, and more

9:50 am
Iranda Chaki
Iranda Chaki
Senior Policy Coordinator
SEMI Europe

Europe: PFAS Restriction, POPs, F-Gas, GENESIS, REACH

10:15 am

Break

10:45 am
Michael Golden
Michael Golden
Director, Navy Programs & Microelectronics Initiatives
Office of the Deputy Assistant Secretary of War for Product Support

US Department of War Perspective on Semiconductor Supply Chain Risks

11:15 am
Patrick Gottsacker
Patrick Gottsacker
Supply Chain Regulatory Compliance Program Manager
Intel

US EPA: TSCA New Substances of Concern

11:45 am

Morning Session Q&A

12:15 pm

Lunch & Networking

1:15 pm
James Amano
James Amano
Senior Director, EHS
SEMI

Review of afternoon agenda

1:20 pm
Andrew Petraszak
Andrew Petraszak
Tokyo Electron
Patrick Gottsacker
Patrick Gottsacker
Intel

PFAS Transparency

1:50 pm
Masahide Yodogawa
Masahide Yodogawa
Director, Technology Co-Creation Promotion Group
AGC, Inc.

PFAS Recycling

2:15 pm
Ben Kallen
Ben Kallen
Sr. Manager, Public Policy & Advocacy
SEMI
Andrew Petraszak
Andrew Petraszak
Tokyo Electron

SEMI Washington DC Update: Federal and State-level Advocacy

2:40 pm

Afternoon Q&A

3:00 pm - 3:30 pm

Networking

EHS Sustainability Standards

Plan now to join fellow semiconductor industry professionals at SEMI Headquarters in Milpitas, California at the 2026 SEMI EHS Summit.

Industry experts will present on the regulatory matters that will impact the industry in 2026 and beyond, followed by discussions on taking collective action to strengthen semiconductor manufacturing. 

Topics:

  • US Regulatory Landscape under second Trump Administration
  • US State-level legislation
  • Europe: PFAS restriction, REACH restriction, Packaging and Packaging Waste Regulation, GENESIS Consortium, etc.
  • US Department of War Perspective on Semiconductor Supply Chain Risks
  • Stockholm Convention
  • Emerging regulations in Asia
  • Supply Chain Transparency
  • US EPA Technology Transition Rule (HFC Phasedown)
  • US EPA TSCA New Substances of Concern

Attend, network and strategically prepare your company.  This is an in-person event only.

8:30 am - 3:30 pm Off Add to Calendar 2026-05-28 08:30:00 2026-05-28 15:30:00 2026 EHS Summit Plan now to join fellow semiconductor industry professionals at SEMI Headquarters in Milpitas, California at the 2026 SEMI EHS Summit.Industry experts will present on the regulatory matters that will impact the industry in 2026 and beyond, followed by discussions on taking collective action to strengthen semiconductor manufacturing. Topics:US Regulatory Landscape under second Trump AdministrationUS State-level legislationEurope: PFAS restriction, REACH restriction, Packaging and Packaging Waste Regulation, GENESIS Consortium, etc.US Department of War Perspective on Semiconductor Supply Chain RisksStockholm ConventionEmerging regulations in AsiaSupply Chain TransparencyUS EPA Technology Transition Rule (HFC Phasedown)US EPA TSCA New Substances of ConcernAttend, network and strategically prepare your company.  This is an in-person event only. SEMI 673 South Milpitas Blvd. Milpitas, CA 95035 United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register Now
Event format
Promote in calendar
On
Belgium China France Germany India Ireland Italy Japan Malaysia Singapore South Korea Taiwan United States Watch the recording ICP 2026 2 Business Executive Technical
Highlighted content

United States

Sustainability

SEMI Sustainability, in collaboration with STX Group, hosted a webinar on Internal Carbon Pricing (ICP) for the semiconductor value chain. The session was anchored in a new industry report developed with input from members of SEMI’s Carbon Pricing Workgroup and will feature speakers from ASML, Delta Electronics, and Lam Research.  The webinar  highlighted the 5 key steps in creating and implementing your own ICP plan, and understand the process, its benefits and the opportunities offered.

The presentations explored key insights from the report alongside SEMI member perspectives, with speakers sharing practical examples and lessons learned—from early exploration to applied approaches—across the semiconductor value chain. 

Off Add to Calendar Disabled America/Los_Angeles
Event format
Promote in calendar
Off

Oxford Instruments, a leading provider of advanced plasma processing solutions, today announced a plasma equipment supply agreement with Applied Optoelectronics Inc. (AOI) (Nasdaq: AAOI), a leading provider of advanced optical and hybrid fibre-coaxial networking products that power the internet, for several etch and deposition cluster systems at their facility in Sugar Land, Texas.

The agreement will support AOI’s transformative expansion and technological advancements in indium phosphide (InP) for optoelectronic device manufacturing, as the company rapidly scales to increase production capacity within the U.S.

As AOI undergoes a significant growth phase, the company is upgrading its production capabilities to meet increasing demand for high-performance InP optoelectronic devices. Oxford Instruments’ advanced plasma etch and deposition processing systems will play a key role in this transformation by supporting AOI with fully automated 3-4-6-inch capable production systems for InP processes.

“AOI is expanding its U.S. manufacturing capacity in Texas to support demand for our optical transceivers in AI datacentres, and key suppliers like Oxford Instruments will help us continue to upgrade our fully automated production line,” said Fred Chang, Senior Vice President and North American General Manager at AOI. “With our combined technology, we can speed the processing of multiple wafer sizes, ranging from 3 to 6 inches, while improving overall quality and reducing costs.”

“AOI has been a valued long-term partner, and we are thrilled to have earned their trust as the chosen supplier for their production expansion and technology upgrades. Our unique high-temperature Electrostatic Chuck (ESC) design, which enables advanced processing capabilities, was a key factor in their decision. AOI also conducted an extensive vendor qualification process, including a visit to our brand-new purpose-built manufacturing facility in Bristol, UK, where we received high praise for our technology and production capabilities,” said Emiel Thijssen, Vice President of Sales and Business Development USA, Oxford Instruments Plasma Technology. “We are also investing significantly to ensure we continue to deliver world-class service capability in the Texas region, focusing on the availability of spares and expanding our field service and process engineering teams, to support the rapid expansion of leading manufacturers in the region such as AOI.”

###


For media enquiries, please contact:
Grant Baldwin, Head of Marketing
Oxford Instruments Plasma Technology
E: [email protected]
About Oxford Instruments plc
Oxford Instruments provides academic and commercial organisations worldwide with market-leading scientific technology and expertise across its key market segments: Materials Analysis, Healthcare & Life Science and Semiconductors. Innovation is the driving force behind Oxford Instruments' growth and success, supporting its core purpose to accelerate the breakthroughs that create a brighter future for our world. The vigorous search for new ways to make our world greener, healthier and more productive is driving unprecedented levels of R&D investment in new materials and techniques to support productivity and decarbonisation worldwide, creating a significant opportunity for Oxford Instruments to grow.

Oxford Instruments holds a unique position to anticipate global drivers and connect academic researchers with commercial applications engineers, acting as a catalyst that powers real world progress. Founded in 1959 as the first technology business to be spun out from Oxford University, Oxford Instruments is now a global company listed on the FTSE250 index of the London Stock Exchange (OXIG).

For more information, visit www.oxinst.com

About AOI 
Applied Optoelectronics, Inc. (AOI) is a leading developer and manufacturer of advanced optical and HFC networking products that are the building blocks for AI datacentres, CATV and broadband fibre access networks around the world. AOI supplies this critical infrastructure to tier-one customers across cloud computing, CATV broadband, telecom, and FTTH markets. The company has R&D facilities in Atlanta, GA, and engineering and manufacturing facilities at its corporate headquarters in Sugar Land, TX, as well as in Taipei, Taiwan and Ningbo, China. For additional information, visit www.ao-inc.com. 

Advancing Thermal Scanning Probe Lithography

Zurich, Switzerland — Following the successful introduction of the modular NanoFrazor nanolithography system in 2024, Heidelberg Instruments is proud to announce the installation of the newest NanoFrazor. The system is equipped with the recent modules, enabling parallelized thermal scanning probe lithography (t-SPL). The beta site is hosted by the research partner EPFL, the Swiss Federal Institute of Technology in Lausanne, Switzerland. The installation marks a significant step forward in joint efforts to bring next-generation nanofabrication technologies into practice, promising advances in nanoscale research and applications.

Designed for high-resolution lithography down to 20 nm, with application flexibility and increased throughput, the system features parallelized t-SPL with ten heated tips writing simultaneously, Direct Laser Sublimation (DLS), and advanced automation. “Parallelizing t-SPL was the logical next step in advancing thermal nanolithography. The implementation, however, was far from trivial.” states Dr. Emine Cagin, CTO of Heidelberg Instruments Nano AG. “Parallelization required a decade of development, culminating in a new and scalable framework for electronics and software that now powers the new NanoFrazor.”

The new module, named the Decapede, increases the throughput up to tenfold, without compromising on high-resolution capabilities. “With improved throughput, we are considering upscaling grayscale nano surfaces that enable deterministic and localized strain engineering of 2D materials from chip-level to wafer-scale for potential industrial integration”, says Berke Erbas, Postdoctoral Researcher in the Microsystems Laboratory at EPFL. “We also aim to upscale grayscale nanoimprint lithography stamps fabricated through t-SPL and dry-etching approaches.”

EPFL — A Hub for Innovation
EPFL’s expertise in t-SPL and broad nanofabrication capabilities make it an ideal beta site and mark the continuation of a long-standing, trusted partnership with Heidelberg Instruments. The consortium of research groups involved brings together a combination of deep knowledge in t-SPL and diverse nanofabrication techniques, along with fresh ideas and challenging applications. The generous commitment to providing continuous feedback will help Heidelberg Instruments further validate the system performance and refine user interfaces.

From Nanoelectronics to Quantum Devices, a Look Ahead
The EPFL beta site is not only a testing and validation site for the system’s capabilities but first and foremost a catalyst for innovation in nanolithography. Applications at the EPFL beta site span nanoelectronics, plasmonics, quantum devices, and bio-nano-sensors. Jürgen Brugger, Professor in Microengineering and Materials Science at EPFL, highlights: “t-SPL has proven to be an excellent tool for educating junior researchers due to its capabilities for fast prototyping with a low threshold to create nano-patterns in short time scales. We are excited to expand towards parallel writing capabilities.” For example, the Laboratory of Nanoscience for Energy Technologies (LNET), Professor Giulia Tagliabue, is exploring the use of its gray-scale functionalities for realizing advanced metasurfaces that can strongly confine light at nanoscale dimensions for energy conversion and probing of interfacial processes.

We are looking forward to seeing how the beta site will accelerate discoveries and enable new possibilities in nanoscale science, both in research and educational use of the NanoFrazor system.

Further information: https://heidelberg-instruments.com/product/nanofrazor/

Gütenbach, Germany – December 16, 2025 – RENA Technologies is proud to be a key industrial partner in a new 1.3 million Euro Government-funded project led by the National Physical Laboratory (NPL) and supported by the Department for Science, Innovation and Technology (DSIT). The initiative will establish critical new metrology capabilities to strengthen the UK’s semiconductor innovation infrastructure and accelerate the development and adoption of next-generation semiconductor materials and processes.

This strategic investment underlines the UK’s commitment to maintaining global competitiveness in semiconductors, helping to attract private investment, strengthen supply chains, and support long-term economic growth. As advanced semiconductor materials become central to technologies such as electric vehicles, renewable energy, 5G communications and advanced electronics, robust measurement, verification and standards are increasingly essential.

The project brings together a broad consortium spanning industry and academia. Together, the partners cover the full innovation landscape, from materials research and process development to device fabrication and performance verification.

“At RENA, we develop advanced wet processing and surface treatment solutions that are critical in manufacturing of compound semiconductors and emerging materials. Through this collaboration, RENA will contribute industrial insight and process expertise to ensure that new measurement and testing capabilities are closely aligned with real manufacturing challenges.” States Peter Schneidewind, CEO of RENA Technologies.

While silicon remains the foundation of much of today’s semiconductor industry, many high-growth applications increasingly depend on advanced materials such as gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and indium phosphide (InP). These materials offer superior performance in high-power, high-frequency and optoelectronic applications, but they also introduce new complexities in processing, characterization and quality assurance. Reliable standards and independent measurement methods are therefore essential to derisk innovation and support scale-up.

Through this project, consortium partners will work with NPL to:
• Develop new UK measurement and test capabilities for advanced semiconductor materials by combining academic research excellence with world-leading metrology expertise.
• Apply these capabilities to critical industry challenges, including assessing material integrity, verifying RF performance, and testing device reliability under demanding operating conditions.
• Share the resulting capabilities openly with industry, helping to build national consensus and strengthen the UK’s influence in international standards development for novel semiconductor technologies.

Following extensive consultation the consortium has identified three priority application areas where the UK can have the greatest global impact: power electronics, RF-communications, and optoelectronics. These areas align closely with RENA’s customer base and technology roadmap, particularly in power and compound semiconductor manufacturing.
By participating in this program, RENA reinforces its commitment to supporting the UK semiconductor ecosystem with industrially relevant innovation, enabling customers to adopt advanced materials with confidence, and helping position the UK as a global leader in next-generation semiconductor technologies.

About NPL
The National Physical Laboratory (NPL) is the UK's National Metrology Institute (NMI), developing and maintaining the national primary measurement standards, as well as collaborating with other NMIs to maintain the international system of measurement. As a public sector research establishment, it delivers extraordinary impact by providing the measurement capability that underpins the UK's prosperity and quality of life. NPL develops the metrology required to ensure the timely and successful deployment of new technologies and work with organizations as they develop and test new products and processes.

About RENA Technologies GmbH
RENA Technologies is a leading global supplier of production machines for wet chemical surface preparation. RENA products are used in path-breaking application fields such as semiconductors, MedTech, renewable energies, and the glass industry. RENA equipment is used to treat or modify surfaces of, for example, semiconductor wafers, solar cells, glass, optical substrates or other high-tech products using wet chemical processes. RENA offers proven standard machines as well as customer-specific solutions and process support.

 

Tirana, November 2025 – Atronix Sh.p.k., Albania’s pioneering Electronics Manufacturing Services company, officially inaugurated in November its new production facility at Tirana Industrial Park. The event marks a historic moment for Albania’s industrial landscape, establishing the country’s first advanced EMS factory with capacity to serve European and North American markets.

Equipped with the latest generation of JUKI SMT Production line with advanced AOI/X-ray inspection ERSA selective and wave soldering, and fully integrated traceability systems, Atronix introduces advanced technological capabilities. 

The inauguration ceremony brought together distinguished guests, including leading figures from the European electronics industry Mr. Dieter Weiss, EBRD representatives. Ms. Ekaterina Solovova, Ms. Egla Ballta, JUKI Europe Mr. Kenji Hirohata, Mr. Rui Vidal and Mr. Davor Jakulin international and national business partners, representatives from the Albanian Government, Academia and Universities, etc. 

“Our vision from the beginning was clear: to build a factory that stands at the same level with Europe’s most advanced EMS providers,” said Ms. Enkeleda Kuka, Founder & CEO of Atronix. “Today, we are proud to show that Albania can compete in high-precision electronics manufacturing.” During the ceremony, Atronix extended appreciation to its international collaborators, including JUKI Europe, Kurtz-Ersa, and several global clients and advisors who have contributed to the company’s rapid development. 

“In this challenging business climate, it is very good to see a new EMS company being opened in Albania. Eastern Europe will see a strong growth of electronic production in the future and Atronix will participate in this development.” said Mr. Dieter G. Weiss, European EMS industry expert and longstanding supporter of the project. 

This factory sets a new standard for high-value manufacturing in the country and demonstrates how it can transform Albania's industrial landscape. EBRD has supported Atronix through our Advice for Small Business program and looks forward to the future successes of Atronix" said Ms Ekaterina Solovova, Head of Albania, EBRD.

With its inaugural production lines now operational, Atronix is preparing for a strong expansion phase, targeting new partnerships in Electronic Manufacturing and broader industrial integration across Europe and North America. 

“Atronix symbolizes what the next chapter of Albanian industry can look like,” added Ms. Kuka. “We are committed not only to manufacturing high-quality electronics, but also to building trust, reliability, and long-term value for every client who chooses Albania as their production base. 

 

www.atronix.al[email protected]; Tirana Industrial Park 48, Kashar, Tirana,  Albania

Second-generation platform delivers advanced control, in-cycle annealing, and high-throughput performance for Wide Bandgap power and RF device manufacturing

Espoo, Finland, November 24, 2025 – Beneq introduces the Beneq Transform® XP, a second-generation ALD platform developed to meet the performance demands of Wide Bandgap (WBG) power and RF device technology development and manufacturing. Building on the proven Beneq Transform® platform, the new system adds advanced ALD control, faster cycle times, and greater process capabilities in a high-throughput format.

The Beneq Transform® XP features a second-generation, flow-optimized 25-wafer mini-batch thermal ALD reactor that achieves breakthrough deposition rates with single-digit-second cycle times for common ALD oxides and nitrides. Refined flow and pressure dynamics ensure exceptional within-wafer and wafer-to-wafer uniformity – even at a few nm film thicknesses – while precise dwell-time control delivers excellent conformality on high-aspect-ratio structures.

Transform® XP also introduces advanced PEALD process control to precisely manage low-energy ions. This enables optimized plasma pre-cleaning and deposition, resulting in improved interface quality, tunable passivation, and enhanced device performance and reliability. The system integrates in-cycle annealing, a proprietary step that densifies and purifies films to achieve stoichiometric, low-impurity materials and crystalline alignment, such as AlN lattice orientation.

“Transform® XP is our response to the next wave of device challenges in power and RF manufacturing,” said Dr. Mikko Söderlund, Head of Sales, Semiconductor ALD at Beneq. “Customers value the original Transform® for its versatility and reliability. With XP, we introduce capabilities they specifically asked for – improved ion control, faster cycles, and in-cycle film densification – all in a versatile platform.”

With over a dozen Beneq Transform® clusters installed globally for WBG pilot and production use, and more than 100 process modules shipped, Beneq continues to support leading IDMs, foundries, and RTOs advancing More-than-Moore technologies.

About Beneq

Beneq pioneered industrial production of Atomic Layer Deposition (ALD) with the introduction of the first commercial ALD equipment in 1984. Today, Beneq advances ALD adoption and validation with a portfolio that includes the Beneq Transform®, Transform XP, Transform 300, Transmute™, and Prodigy™ for specialty semiconductor device fabrication; TFS 200 and TFS 500 for R&D; the P400A, P800, and P1500 batch systems for coating critical semiconductor chamber components and complex part geometries; and spatial ALD platforms such as the C2R™ and Genesis for roll-to-roll processing. Headquartered in Espoo, Finland, Beneq enables ALD integration from lab to fab for semiconductors, optics, and functional coatings.

Press Contact
Charlotte Bärlund
Event and Communications Lead
[email protected]

Breker Verification Systems today confirmed its RISC-V functional verification solutions were pivotal for verification of the NOEL-V, one of Frontgrade Gaisler’s fault-tolerant RISC-V processor IP cores.

“The development of Frontgrade Gaisler’s IP cores is guided by a philosophy that does not tolerate design issues,” notes Jan Andersson, Director of Engineering at Frontgrade Gaisler. “This demands the most robust verification environment, something Breker’s verification solution has contributed to improve, with its broad range of tests and in-depth corner case coverage.”

The ultra-high verification coverage afforded by Breker’s RISC-V SystemVIP and Test Suite Synthesis products make it a key technology in Frontgrade Gaisler’s development program. Breker provides test suites for the complete verification of RISC-V cores and SoCs from detailed microarchitectural analysis to advanced system integrity validation.

The NOEL-V processor by Frontgrade Gaisler, targets high-reliability applications, with its high-performance and fault-tolerant design. Built on the RISC-V architecture, NOEL-V offers customization options, allowing SoC designers to create solutions tailored to their specific needs. The processor is at the heart of the GR765, Frontgrade’s next-generation radiation-hardened space microprocessor.

“We are delighted to work with Frontgrade Gaisler to achieve their extreme coverage goals and eliminate unpredictable corner cases, both of which are necessary given the extreme environments in which their devices are deployed,” says David Kelf, Breker’s CEO. “Our RISC-V test suites have become an essential component in the development flows of over 20 commercial entities and other organizations, providing us with unique experience with the numerous unusual verification issues inherent in these processors.”

Breker extended testing to target advanced, system-level integrity, in addition to its existing test suites and generators focused on instruction set architecture testing, included in its RISC-V SystemVIP. It provides coverage by driving cross functional stress verification and unpredictable corner case discovery with its test suite synthesis technology applied across the verification flow from simulation, through emulation and prototyping to post silicon validation.

About Frontgrade Gaisler
Frontgrade Gaisler, a Frontgrade company, is a leading provider of radiation-hardened microprocessors and IP cores for critical applications, particularly in the space industry. The company’s processors are ideal for any space mission or other high-reliability application due to their reliability, fault tolerance, and radiation tolerance. Frontgrade Gaisler microprocessors can be found all over the solar system, from Mercury to Neptune. www.gaisler.com

About Breker Verification Systems
Breker Verification Systems solves complex semiconductor challenges across the functional verification process from streamlining UVM-based testbench composition to execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions that provide test content portability and reuse. Breker’s solutions include a SystemVIP library of scenarios for RISC-V and Arm, core and SoC testing, coherency, security and other critical areas. Breker solutions easily layer into existing environments and operate across simulation, emulation, prototyping, and post-silicon execution platforms. Its Trek family is production-proven at leading semiconductor companies worldwide and enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easy verification knowledge reuse. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), privately held Breker has a reputation for dramatically reducing verification schedules in advanced development environments. Case studies that feature Analog Devices, Broadcom, IBM and other companies leveraging Breker’s solutions are available on the Breker website.

Engage with Breker at:
Website: www.brekersystems.com
Twitter: @BrekerSystems
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/