Breker Donates Advanced Test Suite Components to RISC-V International for Use in Future Compliance Activities
• Donation includes open-source system integrity tests for core and SoC certification
• Unique Breker tests complements existing test sets
• Breker’s RISC-V SystemVIP will be demonstrated at booth #P4 during RISC-V Summit North America 2025
SAN JOSE, CALIF. –– October 16, 2025––Breker Verification Systems today announced a donation to RISC-V International of a subset of its RISC-V advanced test suite developed through its work with more than 20 RISC-V core producers.
The donation is designed to be complementary to the existing Architectural Compliance Test (ACT) and ongoing ISA compliance activities, consisting of unique tests not available from other sources.
Breker provides test suites for the complete verification of RISC-V cores and SoCs from detailed microarchitectural analysis to advanced system integrity validation. The radonation will consist of a subset of these tests to target ISA compliance. The test donation will cover both core and SoC certification and will include, but is not limited to, coherency, hypervisor, vectors, advanced interrupt architecture, IOMMU and other scenarios. Each component is designed to complement existing tests.
“Breker is now working with over 20 commercial entities and other organizations to verify their RISC-V cores, providing us with unique experience of the myriad of unusual verification issues inherent in these processors,” says David Kelf, Breker’s CEO. “We are giving back to the RISC-V community by providing a subset of these tests, open source, that can target ISA compliance and for other purposes.”
The announcement of the donation coincides with the RISC-V Summit North America Tuesday, October 21, through Thursday, October 23, at the Santa Clara Convention Center in Santa Clara, Calif. As a Platinum Sponsor, Breker will exhibit in Booth #P4 and offer five presentations as part of the RISC-V Summit program.
“At RISC-V International, we greatly value the expertise of the Breker team and the contributions they have made to ongoing ISA compliance work,” remarks Andrea Gallo, RISC-V International’s CEO. “I am looking forward to Breker’s donation and the impact it can have in complementing and extending our existing ACT test suites.”
Breker’s donation provides alignment with RISC-V International programs. This will provide value to the company’s customers, as well as the RISC-V designer community, by aligning Breker’s full RISC-V verification test suite with RISC-V test developments.
In addition to existing test suites and generators, which are focused on random instruction generation for instruction set architecture testing, with SystemVIPs, Breker has been able to significantly extend testing to advanced system-level integrity. Using test suite synthesis technology, Breker is able to provide a high degree of coverage by driving cross functional stress verification and unpredictable corner case discovery. The donation will include tests generated using test suite synthesis.
David Kelf and Adnan Hamid, Breker’s Executive President and CTO, were elected Chairperson of the Requirements Working Group and Vice-Chairperson of the Test Plan Working Group, respectively, in the RISC-V International Certification Steering Committee.
Breker at RISC-V Summit North America 2025
Breker will demonstrate its RISC-V CoreAssurance and SoCReady SystemVIPs and Trek Test Suite Synthesis solutions at RISC-V Summit North America, Tuesday, October 21 through Thursday, October 23, at the Santa Clara Convention Center.
Presentations featuring Breker executives include:
Member Day: “Framework for RISCV Certification—Software, Hardware and Systems”
Nambi Ju, Lyle Technologies, LLP
Tuesday at 4 p.m. in Grand Ballroom H (Level 1)
Demo: “RISC-V AIA Expanding Interrupts: Applications, Implementation and Verification”
Adnan Hamid
Wednesday at 1 p.m.
Exhibit Hall A, Demo Theater
“RISC-V System Level Certification from Verification Foundations”
Adnan Hamid
Wednesday at 3:15 p.m.
Theater (Level 2)
Lightning Round: “Leveraging AI to understand the RISC-V ISA Specification”
Dave Kelf and Nambi Ju
Wednesday at 4:15 p.m.
“Unleashing ML Processing Power Through RISC-V Vectors: Applications, Implementation and Verification”
Brian Baker, Solutions Architect
Thursday at 2:35 p.m.
Grand Ballroom G (Level 1)
To arrange a demonstration or private meeting, send email to [email protected].
About Breker Verification Systems
Breker Verification Systems solves complex semiconductor challenges across the functional verification process from streamlining UVM-based testbench composition to execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions that provide test content portability and reuse. Breker’s solutions include a SystemVIP library of scenarios for RISC-V and Arm, core and SoC testing, coherency, security and other critical areas. Breker solutions easily layer into existing environments and operate across simulation, emulation, prototyping, and post-silicon execution platforms. Its Trek family is production-proven at leading semiconductor companies worldwide and enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easy verification knowledge reuse. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), privately held Breker has a reputation for dramatically reducing verification schedules in advanced development environments. Case studies that feature Analog Devices, Broadcom, IBM and other companies leveraging Breker’s solutions are available on the Breker website.
Engage with Breker at:
Website: www.brekersystems.com
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TrekSoC, TrekSoC-Si, RISC-V CoreAssurance SystemVIP and RISC-V SoCReady SystemVIP are registered trademarks of Breker Verification Systems. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products.
