About the Speaker: Rich Boardman is a 15-year veteran of the Semiconductor industry whose expertise lies in equipment sets, process technology and consumables related to wafer or substrate dicing, grinding or polishing. Rich is a Senior Sales Engineer at GDSI, located in San Jose, California.
United States
Join us for this second webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication.
In this session, GDSI will provide an introduction of the Stealth Dicing process, highlight the applications it is most well suited to, and share design rules and process window specifications.
The Stealth laser dicing process is a water-free, particle-free wafer singulation method. It is particularly well suited to MEMS, Quantum, bio-sensing and Silicon Photonics to name a few use cases. Secondarily, it offers great value for multi-project wafer (MPW) applications since it allows singulation of the whole wafer in a single process step, negating the need for wafer sub-dicing and remounting.
Find out if your current wafer layout is compatible with the Stealth Dicing process, and if not, what must be done to ensure initial success with this innovative dicing technology. .
Mark D. Poliks, Ph.D. is a SUNY Distinguished Professor of Engineering and Empire Innovation Professor in Systems Science and Industrial Engineering and Materials Science and Engineering at the State University of New York at Binghamton. He is director of the Center for Advanced Microelectronics Manufacturing (CAMM), a New York State Center of Advanced Technology and home to the New York Node of NextFlex. He serves as Chair of the Smart Energy Transdisciplinary Area of Excellence at the Binghamton campus. 
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