downloadGroupGroupnoun_press release_995423_000000 copyGroupnoun_Feed_96767_000000Group 19noun_pictures_1817522_000000Member company iconResource item iconStore item iconGroup 19Group 19noun_Photo_2085192_000000 Copynoun_presentation_2096081_000000Group 19Group Copy 7noun_webinar_692730_000000Path
Default Banner Image

Germany

Previous Page
Germany

Dresden, Germany, March 24, 2026 – As semiconductor manufacturing continues to expand in China, reliable and efficient environmental technologies are becoming increasingly important for stable and sustainable fab operation. DAS Environmental Experts presents its SALIX wet scrubber product family, a series of high-efficiency point-of-use systems designed for the treatment of waste gases from wet chemical processes in semiconductor manufacturing.

SALIX systems are engineered to ensure high removal efficiency and stable operation in demanding semiconductor production environments. SALIX reliably removes substances such as IPA, ammonia and hydrofluoric acid (HF) from waste gas streams of modern single wafer clean systems – a key contribution to safe and sustainable semiconductor manufacturing. In addition, the technology removes particles, salts and droplets from the processed gas stream. The robust system design supports high uptime and long maintenance intervals, contributing to reliable fab operation.

A key advantage of the SALIX product family is its flexible portfolio. SALIX products are among the smallest and most compact systems on the market and are suitable for both new fabs and retrofit applications in existing fabs. DAS Environmental Experts offers the technology in four different products, providing semiconductor manufacturers with a wide range of configuration options:

• NEW: SALIX – the latest release with improved performance and optimized system operation
• SALIX MINI – a compact two-stage system for space-constrained installations
• NEW: SALIX MICRO [SR1.1]– a highly compact configuration with pre-scrubber section for flexible integration

This structured product portfolio enables customers to select the most suitable system according to process requirements, fab layout and integration needs. The availability of multiple system variants within one technology platform provides semiconductor manufacturers with excellent flexibility in system selection and plant design.

SALIX systems are designed for compatibility with all common process tools and can be adapted to a wide range of wet chemical applications. Their compact design and flexible configuration support efficient integration into modern fabs, helping manufacturers optimize both environmental performance and operational efficiency.

The SALIX product family will be presented during SEMICON China 2026 (March 25–27, Shanghai New International Expo Centre). Interested visitors can learn more about the technology and its applications at the DAS Environmental Experts booth (Booth N2 | 2619).

With more than three decades of experience in environmental technology for the semiconductor industry, DAS Environmental Experts continues to support chip manufacturers worldwide with solutions that combine high process reliability, efficient emission treatment and long-term operational stability.

About the Company
DAS Environmental Experts Group (DAS Group), headquartered in Dresden, Germany, was founded in 1991 and is now a global organization with subsidiaries on three continents and more than 950 employees worldwide. Over the past three decades, DAS Group has become one of the leading technology and equipment providers for waste gas abatement solutions with a focus on semiconductor industry.
In addition, DAS Group develops advanced process and system solutions for industrial water treatment, with extensive expertise in the recycling and reuse of wastewater from the semiconductor industry.
DAS solutions are engineered to meet the stringent purity requirements of semiconductor manufacturing, helping clients comply with global environmental standards.

Cancellation Policy
Belgium France Germany Ireland Italy United States Seimconductor Device Assembly Training

Course Description 

This three-day virtual workshop (4 hours a day) provides a complete overview of the semiconductor manufacturing process. The class focuses on key process steps needed to form a functioning device. Some important science and engineering ideas needed to understand device manufacturing will be discussed. The workshop is designed for non-technical personnel needing an understanding of the fab process steps.  Some technical background from attendees will improve the workshop learning. 

The first day will overview the fab process steps with a brief summary of how a transistor functions. We will discuss how multiple transistors are connected to form a logic or memory device. We will also cover how a transistor works with respect to the physical layout of Bipolar and MOSFET transistors. 

The second day will cover key fab process steps. Ion implantation, photolithography including DUV and EUV processes, plasma processes including deposition and etch, rapid thermal processing, and wet etch processing. Specific emphasis will be given to the different wet etch processes. 

The third day of the workshop will focus on the new transistor designs, including FinFET and CFET designs. We will also cover reasons for changing the transistor design and newer materials, including tantalum, hafnium, silicon germanium, and low-k dielectrics.  We will also review roadmaps of leading companies, including TSMC, Intel, and Samsung. 

After completing the workshop, the student will be able to describe all the fabrication and assembly process steps and have an understanding of how the process steps work together to form the completed integrated circuit, in addition to an understanding of future structures.

 

Who Should Attend

This course is intended for both manufacturing and R&D know-how in IC packaging professionals, including but not limited to:

  • Process Technicians
  • Material Engineers
  • Process Engineers
  • Equipment Manufactures
  • Technical Marketing Engineers

Topics Included

  • Silicon wafer manufacturing
  • Basic operating principles of transistors and semiconductor devices
  • Planar, FinFET, and GAA transistor formation and design differences
  • Fab processes needed to form a semiconductor, including the following:
    • Lithography, with a focus on DUV and EUV methods
    • Etching, including wet and plasma processes
    • Deposition, thermal, plasma, electroplating deposition
    • CMP and modern CMP processes
       

Important Information

Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access the course knowledge. 

Can't find the training link on the day of? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders about 24 hours in advance and an hour before with the same link. Please keep these emails on hand to access the training on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.

 

Dr. Tom Dory
ITM Consulting, Inc
Instructor Bio

United States

- SEMI U

Unlock the essentials of the semiconductor manufacturing process.  We will cover science and engineering concepts needed to understand device manufacturing. 

Pricing         

              Early Bird Pricing: $100 off

  • Members:  $699   $599
  • Non-Members:  $749   $649

* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected].

8:00 am - 12:00 pm Off Add to Calendar Disabled America/Los_Angeles Register Now
Event format
Promote in calendar
Off

SEMI Members:  $75

Use your corporate email address during log in to be recognized as a SEMI Member.

Non-Members:  $149

Students:  Free

Contact Basak Ulutas Ozturkler ([email protected]) with a picture of your student ID to receive your discount code.

watch on-demand
Belgium Germany Singapore Taiwan United States FEMC 29 recording Business Executive Technical
Highlighted content

Digital Twin is a virtual representation of the structure, context, and behavior of physical systems or a process, with a live link to a physical system serving as a key enabler for predictive and data-driven optimization. In Printed and Flexible Hybrid Electronics (FHE), manufacturing involves multiple interdependent variables—different printing technologies, inks, substrates, and process conditions—each introducing its own complexity. In practice, additional challenges such as equipment drift, batch-to-batch variations, and environmental fluctuations further impact process consistency and yield. Changing a process or transferring it between tools is often difficult, as each setup is highly customized and sensitive to local conditions. To address these challenges, Digital Twin frameworks connect data from design, fabrication, and metrology into continuously learning digital models. They enable early detection of process drifts, virtual experimentation for process development, and data-driven optimization that reduces time, cost, and waste.

This course introduces Digital Twin frameworks for FHE, focusing on Deep Neural Network (DNN)-based predictive models. Participants will learn how to integrate design, fabrication, and metrology data into continuously learning virtual twins that detect process drifts, enable virtual experimentation, and optimize manufacturing. The program covers the full workflow—from image processing and virtual metrology to AI model training, validation, and hyperparameter tuning—using real datasets. A hands-on “Build Your Own Digital Twin” module in Google Colab will provide practical experience in training and refining models for printed electronics applications, equipping attendees with both theoretical insight and applied skills for process optimization and performance prediction.

ABOUT THE SPEAKER

Benyamin Davaji, PhD
Benyamin Davaji is an Assistant Professor in the Department of Electrical and Computer Engineering at Northeastern University, Boston, Massachusetts, where his research centers on integrated microsystems for sensing and computation using mechanical waves. His work spans acoustic and ultrasound transducers, biointerfaces, and microcalorimetry, with a strong emphasis on data-guided nanofabrication, advanced semiconductor device manufacturing, and interdisciplinary approaches to microsystem design and manufacturing. He earned his Ph.D. in Electrical and Computer Engineering from Marquette University in 2016 and completed a postdoctoral appointment at Cornell University.

United States

Davaji Profile picture
Ben Davaji, PhD
Assistant Professor
Northeastern University
Gity Samadi
Moderator
Gity Samadi, PhD
Sr. Director, R&D Programs
SEMI
NBMC Smart MedTech FlexTech

Join us for a Master Class with Benyamin Davaji, PhD, as he introduces Digital Twin frameworks for Printed and Flexible Hybrid Electronics, demonstrating how AI- and DNN-based models integrate design, fabrication, and metrology data along with printing technologies to detect process drift, enable virtual experimentation, and optimize manufacturing performance. Participants gain hands-on experience building continuously learning digital twins to reduce variability, cost, and time to optimization. 

10:00 am - 12:00 pm Off Add to Calendar 2026-06-10 10:00:00 2026-06-10 12:00:00 FEMC#29 Digital Twins for Printed Electronics: How Can AI Learn FHE Printing? Join us for a Master Class with Benyamin Davaji, PhD, as he introduces Digital Twin frameworks for Printed and Flexible Hybrid Electronics, demonstrating how AI- and DNN-based models integrate design, fabrication, and metrology data along with printing technologies to detect process drift, enable virtual experimentation, and optimize manufacturing performance. Participants gain hands-on experience building continuously learning digital twins to reduce variability, cost, and time to optimization.  United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Watch on-demand
Event format
Promote in calendar
Off
Cancellation Policy
Belgium France Germany Ireland Italy United States Fundamentals of ALD, ALE and Precursors Chemistries Training

Course Description 

This course provides a practical introduction to atomic layer deposition, an essential technique in semiconductor manufacturing. You'll learn about ALD foundational concepts, including growth, advantages, measurements, and more, chemical precursors for use in ALD, selected ALD processes, area-selective deposition, and atomic layer etching. Overall, the applications and chemistry used in semiconductor processing, as they relate to ALD and ALE, are heavily discussed.

Who Should Attend

This course is intended for both manufacturing and R&D know-how in IC packaging professionals, including but not limited to:

  • Engeineers
  • Managers
  • Process Engineers
  • R&D Engineers
  • Sales and Application Engineers who supply packaging materials and tools

Learning Objectives

  • Understanding foundational concepts of ALD.
  • Describe chemical precursors for ALD applications.
  • Identify selected ALD processes and their associated films and materials. 
  • Explain area-selective deposition (ASD), and its uses.

  • Describe Atomic Layer Etching (ALE) concepts and understand it's relationship to ALD.

     

 

Important Information

Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access the course knowledge. 

Can't find the training link on the day of? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders about 24 hours in advance and an hour before with the same link. Please keep these emails on hand to access the training on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.

United States

Dr. Chuck Winter
Dr. Chuck Winter
Instructor
- SEMI U

Discover how atomic-scale precision is revolutionizing semiconductor manufacturing with Atomic Layer Deposition (ALD) and Etching (ALE). Course topics include ALD foundational concepts, Chemical Precursors and Processes, and Advanced ALD Techniques. 

Pricing

          Early Bird Pricing $100 off

  • Members: $845   $745
  • Non-Members: $945  $845

* Group pricing for 20+ attendees: $9900
Any questions, please contact [email protected]

7:30 am - 11:30 am Off Add to Calendar Disabled America/Los_Angeles Register Now
Event format
Promote in calendar
Off

Brings Advocacy for the adoption of RISC-V processors and processor verification tool standards

Leverages broad experience in EDA business strategy, marketing and sales

SAN JOSE, Calif., March 05, 2026 (GLOBE NEWSWIRE) -- Breker Verification Systems today named Larry Lapides, former Synopsys Executive Director of RISC-V Tools Business Development, to its Advisory Board.

In making today’s announcement, David Kelf, Breker’s CEO, noted that Lapides has been a tireless advocate for the adoption of RISC-V processors and the urgent need for RISC-V processor verification tool standards. “Larry’s RISC-V knowledge and his ties to the RISC-V community are welcome additions to Breker and our advisory board.”

“Breker sits at the forefront in the development of commercial processor verification solutions and is a valued member of the RISC-V community,” remarks Lapides. “It will be a pleasure to work with Breker to move this important effort forward.”

Larry Lapides Biography
Lapides joined Synopsys through the acquisition of Imperas Software, where he was Vice President of Worldwide Sales and Marketing. He previously ran worldwide sales at EDA companies including Verisity Design and has more than 30 years in software tools and EDA, plus time spent in infrared systems engineering.

Lapides holds a Bachelor of Arts degree in Physics from UC Berkeley, a Master of Science degree in Applied Physics from Cornell University and an MBA from Clark University in Worcester, Mass.

About Breker Verification Systems
Breker Verification Systems solves complex semiconductor challenges across the functional verification process from streamlining UVM-based testbench composition to execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions that provide test content portability and reuse. Breker’s solutions include a SystemVIP library of scenarios for RISC-V and Arm, core and SoC testing, coherency, security and other critical areas. Breker solutions easily layer into existing environments and operate across simulation, emulation, prototyping, and post-silicon execution platforms. Its Trek family is production-proven at leading semiconductor companies worldwide and enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easy verification knowledge reuse. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), privately held Breker has a reputation for dramatically reducing verification schedules in advanced development environments. Case studies that feature Analog Devices, Broadcom, IBM and other companies leveraging Breker’s solutions are available on the Breker website.

Engage with Breker at:
Website: www.brekersystems.com
Twitter: @BrekerSystems
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/

TrekSoC, TrekSoC-Si, TrekBox and SoC Scenario Modeling are registered trademark of Breker Verification Systems. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products.

Location: Richardson, Texas

Modus Test, a leader in advanced test socket testing solutions and performance validation, and yieldWerx, a semiconductor data and yield analytics platform, today announced a strategic partnership to help close the gap between test hardware and yield intelligence. The collaboration combines Modus Test’s high-performance socket test technology with yieldWerx’s enterprise-scale yield management platform to provide manufacturers with direct visibility into the relationship between socket health and device performance.

The partnership addresses a long-standing disconnect between test execution and data analytics in high- volume manufacturing. Degraded, misaligned, or worn sockets can introduce false failures or escapes without clear root-cause identification. By integrating hardware performance data with yield analytics, manufacturers can better distinguish contact-related artifacts from true silicon failures.
Through this partnership, customers can now:
• Monitor and trend socket performance across testers, sites, and handlers
• Correlate device failures to specific sockets, test cells, or contact events
• Identify unnecessary device rejects caused by socket degradation
• Detect potential escapes where devices pass due to intermittent contact issues
• Optimize preventive maintenance cycles using data-driven insights

By integrating Modus Test equipment data with yieldWerx’s wafer-, lot-, and device-level analytics, manufacturers gain the ability to separate true device behavior from test interface variability, improving confidence in test outcomes and accelerating root-cause resolution.

About yieldWerx
yieldWerx provides a semiconductor yield management platform that enables manufacturers to collect, analyze, and act on production data across the manufacturing lifecycle. The platform consolidates data from wafer fabrication through final test, delivering visibility into product quality, process performance, and yield improvement opportunities.

About ModusTest
Modus Test, LLC was founded on the idea that there are creative ways to improve results by combining innovation with the best-known methods in test design and manufacturing. Providing innovative test solutions includes the MPT series of parametric tests, systems, and accessories. Modus Test has a global presence and the capability to support customers in all the IC development centers and high-volume manufacturing sites around the world. See for yourself how combining innovation with best-known methods can improve your results.

Statements from Leadership
“yieldWerx was built to unify disparate manufacturing data into actionable yield intelligence,” said Aftkhar Aslam, CEO of yieldWerx. “Valuable data exists across testers, handlers, sockets, MES systems, and inspection tools, but it often remains siloed. Our platform connects these domains into a unified analytical framework that enables faster, data-driven decisions that reduce costs.”

“This partnership represents an important step forward in bringing greater transparency and intelligence to semiconductor test,” said Jesse Ko, COO of Modus Test. “Modus Test’s high-performance socket validation solutions, combined with yieldWerx’s powerful analytics platform, create a closed-loop ecosystem where hardware performance and yield outcomes are fully correlated. Together, we are enabling a smarter, more adaptive test environment.”

For further information, please visit https://www.yieldWerx.com or https://www.ModusTest.org.

Cancellation Policy
Belgium France Germany Ireland Italy Overview of Semiconductor Manufacturing 5/27 Training

Course Description

This course offers a solid foundation in semiconductor manufacturing, from basic concepts to advanced techniques, providing practical insights into the tools, processes, and technologies driving the industry.

Learning Objectives

  • Gain a comprehensive understanding of the semiconductor industry and manufacturing process, design, and eco-system of the semiconductor industry
  • Understand the jargon, tools, and materials used in the design and fabrication of an integrated chip
  • Effectively be able to communicate semiconductor manufacturing concepts with other associates and industry professionals

Course Topics

  • Basic Electronics and Microelectronics: Definitions of essential electronic terms/concepts and introduction to microelectronics and integrated circuits
  • Process Nodes: Process nodes and their impact on device performance and cost
  • Device Physics and Transistor Operation: Principles of device operation and transistor functionality
  • Crystal Growth and Wafer Preparation: Crystal growth techniques and wafer preparation processes
  • Advanced Transistor Technologies: FDSOI, FinFETs, and Gate-All-Around (GAA) transistors and their impact on device performance
  • Circuit Design and Layout: Introduction to circuit design, layout techniques, and tools
  • Wafer Processing: Mask Making and Lithography: Techniques and materials used in mask making and various lithographic methods (DUV, Immersion, EUV)
  • Clean Room Environments: Importance of clean rooms in semiconductor manufacturing and contamination issues
  • Etching and Cleaning Processes: Plasma and wet etching processes
  • Ion Implantation and Diffusion Techniques: Methods for doping and controlling diffusion in semiconductor fabrication
  • Deposition Techniques: RTP, CVD, ALD, and ALE techniques and their effect on device performance
  • Electroplating and Sputtering: Metal deposition techniques used in manufacturing
  • Packaging and Testing: Techniques such as wire bonding, die stacking, flip chip, and chiplets packaging, semiconductor testing processes
  • Metrology and Measurement Tools: Tools and methods used for precision measurement in semiconductor manufacturing
  • Semiconductor Industry Ecosystem: The major players in the industry 

Who Should Attend

Anyone interested in understanding semiconductor manufacturing, including new employees, professionals in related industries, and those seeking to broaden their knowledge of the field.

Instructor

Denny Frye 

PT International, LLC

Instructor Bio
 

Testimonials 

See what course participants had to say about this course!

  • "The expansive width of coverage with sufficient depth; well curated, relevant information with live references, and the open style of delivery which made the course more of a sharing than a lecture, was enjoyable."
  • "Denny's knowledge and ability to explain things in simplified ways was awesome!"
  • "I really enjoyed going over the topics and watching the in-depth videos. I also liked how we received the slide information prior to the class."
  • "The range of topics was perfect for an intro course."
  • "Denny did a great job explaining complex topics. The opportunity to ask questions directly was beneficial for the entire class. If a question couldn't be answered immediately, it was addressed by the next break at the latest."
  • "Thank you very much for the informative course. I appreciate the in-depth and in-detail insight in all aspects of Semiconductor Manufacturing!"

Important Information

Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access course knowledge. 

Can't find the training link day of? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders about 24 hours in an advance and an hour before with the same link. Please keep these emails on hand to access the trainings on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support. 

Germany

- SEMI U

Gain a comprehensive understanding of the semiconductor industry and the integrated circuit (IC) manufacturing process. This course is designed for new personnel in the field or anyone seeking a well-rounded knowledge of the tools, materials, and terminology used in semiconductor manufacturing.

Pricing

Early Bird Special - $100 off  

  • Members: $995 $895
  • Non-Members: $1095 $995

* Group pricing for up to 20+ attendees: $12,900
Any questions, please contact [email protected]

8:00 am - 4:30 pm Off Add to Calendar 2026-05-27 08:00:00 2026-05-28 16:30:00 Overview of Semiconductor Manufacturing (Europe) Gain a comprehensive understanding of the semiconductor industry and the integrated circuit (IC) manufacturing process. This course is designed for new personnel in the field or anyone seeking a well-rounded knowledge of the tools, materials, and terminology used in semiconductor manufacturing.PricingEarly Bird Special - $100 off  Members: $995 $895Non-Members: $1095 $995* Group pricing for up to 20+ attendees: $12,900Any questions, please contact [email protected] Germany SEMI.org [email protected] Europe/Berlin public Europe/Berlin Register Now
Event format
Promote in calendar
Off

Registration Details

Registration is required for this event as it is likely to reach maximum room capacity, at which point interested attendees will be waitlisted.

SEMI Members:  $150

Non-Members of SEMI:  $200

Refunds possible before May 1, 2026.  Substitutions allowed up to May 20.

Questions? Contact James Amano at [email protected].

Register Now
Belgium China France Germany India Ireland Italy Japan Singapore South Korea Taiwan United States 2026 EHS Summit Banner Business Executive Technical

The Summit includes strategic business and technical information for many levels and sectors of the ecosystem, including:

  • Government relations/advocacy staff
  • EHS regulatory professionals
  • Senior executives
  • Business development
  • Device manufacturers
  • Equipment suppliers
  • Materials suppliers
  • Component suppliers
  • Fab and facility systems construction companies

SEMI
673 South Milpitas Blvd.
Milpitas, CA 95035
United States

8:30 am

Badge Pickup and Networking

9:00 am
Joe Stockunas
Joe Stockunas
President, SEMI Americas
SEMI

Welcome and Introduction

9:05 am
James Amano
James Amano
Senior Director, EHS
SEMI

SEMI EHS Overview

9:20 am
Russ Lamotte
K. Russell LaMotte
Principal
Beveridge & Diamond, PC

US Regulatory Landscape: PFAS, PIP, TTR, and more

9:50 am
Iranda Chaki
Iranda Chaki
Senior Policy Coordinator
SEMI Europe

Europe: PFAS Restriction, POPs, F-Gas, GENESIS, REACH

10:15 am

Break

10:45 am
Michael Golden
Michael Golden
Director, Navy Programs & Microelectronics Initiatives
Office of the Deputy Assistant Secretary of War for Product Support

US Department of War Perspective on Semiconductor Supply Chain Risks

11:15 am
Patrick Gottsacker
Patrick Gottsacker
Supply Chain Regulatory Compliance Program Manager
Intel

US EPA: TSCA New Substances of Concern

11:45 am

Morning Session Q&A

12:15 pm

Lunch & Networking

1:15 pm
James Amano
James Amano
Senior Director, EHS
SEMI

Review of afternoon agenda

1:20 pm
Andrew Petraszak
Andrew Petraszak
Tokyo Electron
Patrick Gottsacker
Patrick Gottsacker
Intel

PFAS Transparency

1:50 pm
Masahide Yodogawa
Masahide Yodogawa
Director, Technology Co-Creation Promotion Group
AGC, Inc.

PFAS Recycling

2:15 pm
Ben Kallen
Ben Kallen
Sr. Manager, Public Policy & Advocacy
SEMI
Andrew Petraszak
Andrew Petraszak
Tokyo Electron

SEMI Washington DC Update: Federal and State-level Advocacy

2:40 pm

Afternoon Q&A

3:00 pm - 3:30 pm

Networking

EHS Sustainability Standards

Plan now to join fellow semiconductor industry professionals at SEMI Headquarters in Milpitas, California at the 2026 SEMI EHS Summit.

Industry experts will present on the regulatory matters that will impact the industry in 2026 and beyond, followed by discussions on taking collective action to strengthen semiconductor manufacturing. 

Topics:

  • US Regulatory Landscape under second Trump Administration
  • US State-level legislation
  • Europe: PFAS restriction, REACH restriction, Packaging and Packaging Waste Regulation, GENESIS Consortium, etc.
  • US Department of War Perspective on Semiconductor Supply Chain Risks
  • Stockholm Convention
  • Emerging regulations in Asia
  • Supply Chain Transparency
  • US EPA Technology Transition Rule (HFC Phasedown)
  • US EPA TSCA New Substances of Concern

Attend, network and strategically prepare your company.  This is an in-person event only.

8:30 am - 3:30 pm Off Add to Calendar 2026-05-28 08:30:00 2026-05-28 15:30:00 2026 EHS Summit Plan now to join fellow semiconductor industry professionals at SEMI Headquarters in Milpitas, California at the 2026 SEMI EHS Summit.Industry experts will present on the regulatory matters that will impact the industry in 2026 and beyond, followed by discussions on taking collective action to strengthen semiconductor manufacturing. Topics:US Regulatory Landscape under second Trump AdministrationUS State-level legislationEurope: PFAS restriction, REACH restriction, Packaging and Packaging Waste Regulation, GENESIS Consortium, etc.US Department of War Perspective on Semiconductor Supply Chain RisksStockholm ConventionEmerging regulations in AsiaSupply Chain TransparencyUS EPA Technology Transition Rule (HFC Phasedown)US EPA TSCA New Substances of ConcernAttend, network and strategically prepare your company.  This is an in-person event only. SEMI 673 South Milpitas Blvd. Milpitas, CA 95035 United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register Now
Event format
Promote in calendar
On

The Challenge

Ayar Labs’ engineering teams faced challenges ingesting and analyzing non-standard test data across electro-optical and final test flows while scaling to meet aggressive go-to-market timelines. They sought a test analytics partner capable of loading, validating, and extracting insights from diverse datasets while supporting real-time alerting, yield recovery, and deep engineering analytics.

The Implementation

Week 1–2: Connecting the Pipes

Within the first two weeks, a secure cloud instance of yieldWerx was deployed, and raw data files were streaming in. The platform’s flexible pipelines ingested test data without custom code. The yieldWerx team went further, helping refine business rules, improve data quality, and enrich the information for greater downstream impact.

Week 3: First Insights

By week three, live dashboards were operational. Engineers could view wafer maps, outlier signatures, and correlations that previously required manual effort and scripting. Instead of working across multiple spreadsheets, they now had traceable, drill-down analytics at their fingertips.

Week 4: Real Results

In less than a month, the system was already supporting real yield decisions. Lots that previously required lengthy reviews were dispositioned in hours. Engineers trusted the analytics, and leadership recognized the tangible impact on quality and time-to-market. Ayar Labs is now preparing to onboard additional data formats, including qualification, reliability, and characterization.

The Outcome

The 30-Day Challenge demonstrated that yieldWerx is not just another analytics solution. In weeks, not months, yieldWerx moved from fragmented data to a unified platform that drives yield improvement, accelerates ramps, and reduces risk.

About yieldWerx

yieldWerx, an industry leader in semiconductor yield management, provides a platform that enables manufacturers to collect, validate, and act on production data across the entire semiconductor manufacturing lifecycle.

About Ayar Labs

Ayar Labs, a leader in optical engines for co-packaged optics, is transforming AI infrastructure by accelerating data movement in scale-up networks. Its industry-first optical I/O solution enables customers to maximize compute efficiency and performance while reducing costs, latency, and power consumption. Based on open standards and optimized for AI training and inference, Ayar Labs’ optical interconnect solutions are backed by a robust ecosystem to easily integrate into AI systems at scale. Ayar Labs was founded in 2015 and is funded by domestic and international venture capital firms, as well as strategic investors including AMD, Applied Ventures, GlobalFoundries, Hewlett Packard Pathfinder, Intel Capital, and NVIDIA.

Statements from Leadership

“Our collaboration with yieldWerx gave us measurable results in just 30 days. Their platform ingested
our complex photonics data, and the insights have accelerated how we make yield and quality decisions.”

— Garth Thompson, CIO, Ayar Labs

“Partnering with Ayar Labs has been both inspiring and validating. Photonics test data is some of the most complex in the industry, spanning electrical, optical, and multi-dimensional signatures that traditionally take months to integrate. Delivering measurable results in just 30 days shows the power of a unified, modern analytics platform. We’re proud that yieldWerx is helping Ayar Labs accelerate their roadmap, improve yields, and bring truly groundbreaking optical I/O technology to market faster and with higher confidence. “

— Aftkhar Aslam, CEO, yieldWerx
For further information, please visit https://www.yieldWerx.com or https://ayarlabs.com/.

Belgium China France Germany India Ireland Italy Japan Malaysia Singapore South Korea Taiwan United States Watch the recording ICP 2026 2 Business Executive Technical
Highlighted content

United States

Sustainability

SEMI Sustainability, in collaboration with STX Group, hosted a webinar on Internal Carbon Pricing (ICP) for the semiconductor value chain. The session was anchored in a new industry report developed with input from members of SEMI’s Carbon Pricing Workgroup and will feature speakers from ASML, Delta Electronics, and Lam Research.  The webinar  highlighted the 5 key steps in creating and implementing your own ICP plan, and understand the process, its benefits and the opportunities offered.

The presentations explored key insights from the report alongside SEMI member perspectives, with speakers sharing practical examples and lessons learned—from early exploration to applied approaches—across the semiconductor value chain. 

Off Add to Calendar Disabled America/Los_Angeles
Event format
Promote in calendar
Off
Results per page
Select
Results per page
Subscribe to Germany