The evening begins at the Keysight office, Thursday, April 28, at 5:00pm with the ESD Alliance Annual Membership Meeting. You'll get an overview of the past year's activities and discover what's in store for 2022. The meeting flows directly into a Welcome Reception followed by the powerful CEO Outlook.
Enjoy a lively, nourishing networking reception that kicks off the CEO Outlook panel. Hear influential executives from Arm | Cadence | D2S | Keysight | Siemens share their insights on the current and future state of the design and semiconductor industries. Ed Sperling, Editor-in-Chief of Semiconductor Engineering, moderates a spirited, robust discussion, including an audience Q&A.
Registration | FREE for ESD Alliance and SEMI members | Non-member: $49 per person.
Keysight 5301 Stevens Creek Blvd. Building 5 Santa Clara, CA95051 United States
5:00 pm
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5:30 pm
Bob Smith
Executive Director
ESD Alliance
ESD Alliance Annual Membership Meeting
Overview of ESD Alliance activities for 2021 and plans for 2022.
5:30 pm
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6:30 pm
Networking
Enjoy light food and refreshments as you network with your peers.
6:30 pm
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7:30 pm
Ed Sperling | Moderator
Editor in Chief
Semiconductor Engineering
Moderator & Panelists
Hear panelists from ARM | CADENCE | D2S | Keysight | Siemens EDA discuss the state of the electronic system design industry as well as their views of the outlook for the coming years.
ESD Alliance and co-sponsor Keysight welcome you to join us in-person for the Annual ESDA Membership Meeting & CEO Outlook at the Keysight office in Santa Clara, CA.
ESDA CEO Outlook & Membership Meeting
April 28, 2022
5:00 PM - 7:30 PM
5:00 pm - 7:30 pm
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Add to Calendar2022-04-28 17:00:002022-04-28 19:30:00ESDA CEO Outlook & Membership MeetingESD Alliance and co-sponsor Keysight welcome you to join us in-person for the Annual ESDA Membership Meeting & CEO Outlook at the Keysight office in Santa Clara, CA.Keysight 5301 Stevens Creek Blvd. Building 5 Santa Clara, CA 95051 United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
FOA Summit (Q1 Collaborative Forum)
Registration
This meeting is open for FOA Members Only.
If you are interested in becoming a member, please contact Karim Somani - [email protected].
Join your fellow members for the FOA Annual Collaborative Forum - live and in-person - for informative new case studies, networking, dinners, and exhibits.
8:00 am - 10:00 pm
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Add to Calendar2026-02-24 08:00:002026-02-26 22:00:00FOA Summit (Q1 Collaborative Forum)Join your fellow members for the FOA Annual Collaborative Forum - live and in-person - for informative new case studies, networking, dinners, and exhibits. This event is for FOA Members only. To learn more about becoming an FOA member, email [email protected]. Visit the FOA web pages.Austin Marriott South 4415 South IH-35 Austin, TX 78744 United StatesSEMI.org[email protected]America/Chicagopublic
America/Chicago
About the Speaker: Rich Boardman is a 15-year veteran of the Semiconductor industry whose expertise lies in equipment sets, process technology and consumables related to wafer or substrate dicing, grinding or polishing. Rich is a Senior Sales Engineer at GDSI, located in San Jose, California.
United States
Richard Boardman
Senior Sales Engineer
GDSI
Join us for this second webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication.
In this session, GDSI will provide an introduction of the Stealth Dicing process, highlight the applications it is most well suited to, and share design rules and process window specifications.
The Stealth laser dicing process is a water-free, particle-free wafer singulation method. It is particularly well suited to MEMS, Quantum, bio-sensing and Silicon Photonics to name a few use cases. Secondarily, it offers great value for multi-project wafer (MPW) applications since it allows singulation of the whole wafer in a single process step, negating the need for wafer sub-dicing and remounting.
Find out if your current wafer layout is compatible with the Stealth Dicing process, and if not, what must be done to ensure initial success with this innovative dicing technology. .
MSIG Webinar: The New GDSI Dicing Process
March 30, 2002 8-9 AM PT
8:00 am - 9:00 am
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Add to Calendar2022-03-30 08:00:002022-03-30 09:00:00MSIG Webinar GDSI Dicing ProcessJoin us for this second webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication.
In this session, GDSI will provide an introduction of the Stealth Dicing process, highlight the applications it is most well suited to, and share design rules and process window specifications.
The Stealth laser dicing process is a water-free, particle-free wafer singulation method. It is particularly well suited to MEMS, Quantum, bio-sensing and Silicon Photonics to name a few use cases. Secondarily, it offers great value for multi-project wafer (MPW) applications since it allows singulation of the whole wafer in a single process step, negating the need for wafer sub-dicing and remounting.
Find out if your current wafer layout is compatible with the Stealth Dicing process, and if not, what must be done to ensure initial success with this innovative dicing technology. .United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
About the Speaker: Robert MacDonald is a MEMS engineer at GE’s Research. His research is focused on high performance inertial sensors. He has over 20 years of experience in the MEMS and semiconductor industries. His work has covered the product life cycle of chemical, inertial and optical sensors from design through market introduction and manufacturing.
Join us for this first webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication.
In this first in the series, GE Research will present their new MEMS process suitable for bulk silicon motion sensors. The process aims to deliver many features of complex MEMS flows, such as wafer level packaging with through silicon vias (TSVs), with a short cycle times and low mask counts. This webinar will introduce the Polaris process within the GE Research foundry and explain how to design the process, and our model for delivering new designs.
Designing MEMS with GE’s Polaris Process for Motion Sensor Fabrication
8:00 am - 9:00 am
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Add to Calendar2022-03-02 08:00:002022-03-02 09:00:00MSIG Webinar GE Polaris ProcessJoin us for this first webinar in the MSIG series on foundries, dicing, and packaging considerations in MEMS fabrication.
In this first in the series, GE Research will present their new MEMS process suitable for bulk silicon motion sensors. The process aims to deliver many features of complex MEMS flows, such as wafer level packaging with through silicon vias (TSVs), with a short cycle times and low mask counts. This webinar will introduce the Polaris process within the GE Research foundry and explain how to design the process, and our model for delivering new designs.United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
Moore’s Law continues to evolve - dramatically changing the Field Effect Transistor (FET). As FinFETs reach their performance limits, attention is turning to Gate All Around (GAA) architectures based on Horizontal Nanosheet technology. Such a fundamental shift in transistor architecture will create new challenges to processes and materials, presenting opportunities for companies well-positioned for this shift.
In this webinar, SEMI EMG brings experts to explain the technology trends driving the industry adoption of Gate All Around, how the major players are approaching this transition, and the implications this will have on the material supply chain
Gate All Around Transistors - Opportunities Abound
Position yourself for the next chapter of Moore's Law
10:00 am - 11:00 am
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Add to Calendar Disabled
America/Los_Angeles
SEMI is pleased to once again partner with the HIR Symposium for this 5th Annual Symposium. See the full Agenda.
Don't miss the plenary talk by SEMI President and CEO, Ajit Manocha at 7:40 am PST!
7:30 am - 12:30 pm
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Add to Calendar2022-02-23 07:30:002022-02-24 12:30:00Fifth Annual Symposium on Heterogeneous IntegrationSEMI is pleased to once again partner with the HIR Symposium for this 5th Annual Symposium. See the full Agenda.
Don't miss the plenary talk by SEMI President and CEO, Ajit Manocha at 7:40 am PST!Virtual, Online United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
Fifth Annual Symposium on Heterogeneous Integration
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CASTStandards
7:30 am - 12:30 pm
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Add to Calendar2022-02-23 07:30:002022-02-24 12:30:00Fifth Annual Symposium on Heterogeneous IntegrationVirtual, Online United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
[Silicon Valley Virtual Forum] Environmental Sustainability—Semiconductor Industry Challenges
Contact
Member Price: $49
Non-Member Price: $99
Registration is final. No refunds provided. No substitutions.
Sponsorships can be tailored to meet your branding and marketing objectives. Become a sponsor and brand your company at the Silicon Valley Virtual Forum.
Contact Shane Poblete, +1.202.847.5983 or Eric Rude, +408.943.7047 to learn about available sponsorship opportunities.
Environmental Sustainability—Semiconductor Industry Challenges
High demand for semiconductor chips is driving significant growth and increased visibility of the industry. At the same time, the world is becoming more environmentally conscious and the topic of sustainability of semiconductor manufacturing is coming to the forefront. This requires the entire semiconductor value chain to concurrently support this growing demand while minimizing waste, toxic chemicals and gas emission to produce these chips.
Join us for a Virtual Webinar on March 18, 2022 as the SEMI Silicon Valley Chapter presents “Environmental Sustainability—Semiconductor Industry Challenges” for a great line-up of industry leaders from their own perspectives.
