Hardware is at the heart of computing systems. However, recent years have seen increased attacks exploiting hardware vulnerabilities and exploits, which even traditional software-based protections cannot prevent. Hardware fuzzing has shown promise in detecting vulnerabilities in large-scale designs like modern processors. In this talk, we will describe the hardware vulnerabilities in hardware description languages, such as Verilog and VHDL. Then, we will explain a new and radical approach called hardware fuzzing to find these vulnerabilities and detail how fuzzing techniques can be combined with existing formal verification techniques to detect vulnerabilities efficiently. Finally, we will discuss a strategy for pinpointing vulnerabilities to accelerate the mitigation process and briefly talk about improving the efficiency of hardware fuzzing using ML/AI techniques, such as multi-armed bandit (MAB) and large language models (LLM).
Meet the Speakers
Guest Speaker
Jeyavijayan (JV) Rajendran Associate Professor Department of Electrical and Computer Engineering Texas A&M University Biography
Moderator
Warren Savage Researcher at University of Maryland Applied Research Laboratory for Intelligence and Security Biography
The ESD Alliance, a SEMI Technology Community, is hosting a webinar series, "Savage on Security," moderated by Warren Savage, Researcher at University of Maryland, Applied Research Laboratory for Intelligence and Security.
10:00 am - 11:00 am
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Add to Calendar2025-03-27 10:00:002025-03-27 11:00:00ESD Alliance Webinar: Savage on Security 2: Mar 27, 2025The ESD Alliance, a SEMI Technology Community, is hosting a webinar series, "Savage on Security," moderated by Warren Savage, Researcher at University of Maryland, Applied Research Laboratory for Intelligence and Security. United StatesSEMI.org[email protected]America/Los_AngelespublicRegister Now to Watch the Recorded Event
Siemens extends Veloce hardware-assisted verification and validation with new Innexis shift-left software
Innexis delivers a set of products and capabilities to address demand for shift-left software development in the IC development process
With more demanding software workloads, it is critical to facilitate the development and execution of realistic workloads early in the design phase to shorten overall development time and identify hardware and software defects earlier
Siemens Digital Industries Software announced today the Innexis product suite, a complement to its industry leading Veloce™ hardware-assisted verification and validation system.
Building on the success and rapid adoption of Veloce, Siemens’ Innexis product suite delivers a set of capabilities to address customer demand for shift-left software in the early phases of IC development. These products include a hardware/software development flow from virtual to hybrid to full RTL, an architecture native virtual platform for early high-speed software development and a simulation backplane that enables the development of digital twins in Siemens’ PAVE360™ software for software-defined vehicles and other complex systems.
“The complexity of integrated circuits (IC) is increasing exponentially, designers need more efficient methodologies to meet industry demands. Veloce has seen rapid adoption by industry leaders to help solve this critical bottleneck. The Innexis product suite extends workflow improvements from Veloce to help our customers shift left their IC development and debug cycle,” said Jean-Marie Brunet, vice president and general manager, Hardware-Assisted Verification, Siemens Digital Industries Software. “This enables IC design to begin months before final RTL, all while using a common software workload across the development process.”
Adoption of a shift-left approach for software development and IP verification processes is now mandatory. As chip designs become increasingly complex due to more demanding software workloads, it is critical to enable the development and execution of realistic workloads early in the design phase. A proactive shift-left software approach helps mitigate the risk of identifying issues late in the development cycle.
“The implementation of Innexis in our development process has significantly enhanced software and system validation performance, thereby improving the efficiency of our teams and projects. By enabling heterogeneous component modeling within virtual platforms, it allows us to create realistic high-speed models of System on Chips (SoCs),” said Ari Hautala, Principal System Architect, Nokia Mobile Networks. “Furthermore, the integration of these high-speed virtual platforms with RTL IP on Veloce emulators facilitates superior overall performance while still permitting precise cycle-accurate performance and power analysis on RTL model components. Additionally, Innexis offers exceptional visibility and debuggability for the SoC design, along with the capability to integrate and execute a large number of complex test cases effectively.”
Currently, the Innexis product suite consists of:
Innexis Developer Pro: Innexis Developer Pro software provides a connected development flow from virtual to hybrid to full RTL. This provides a comprehensive environment for accelerating the creation of complex SoC design supporting a wide range of use-cases including seamless hardware-software co-development, co-validation, and pre-silicon cycle accurate analysis and validation. Innexis Developer Pro supports the modelling of complex SoC’s with heterogeneous cores and custom SystemC model components. In addition, it provides the ability to run in both virtual plus RTL hybrid mode for high performance execution, and then at a time of interest switch to full RTL emulation enabling high accuracy analysis of the full SoC when required.
Innexis Architecture Native Acceleration (ANA): Innexis Architecture Native Acceleration software is a cloud- based high-speed virtual platform. By running natively on Arm based servers the software workloads run at much higher speeds than on typical instruction set simulation based virtual platforms. Cloud hosting also provides scalable compute resources and simple browser-based access and tools. Innexis Architecture Native Acceleration can also run on local Arm based servers if preferred. In both cases it enables early software development and testing, and early software defect identification.
Innexis Virtual System Interconnect: Innexis Virtual System Interconnect software facilitates the creation and simulation of comprehensive system level digital twin platforms by seamlessly connecting multi-behavioral virtual and physical subsystems, supporting a variety of communication protocols. Innexis Virtual System Interconnect behavioral models can include Innexis Developer Pro or Innexis Architecture Native Acceleration SoC models, supporting system-level shift-left software development and RTL verification.
To learn more about Siemens’ Innexis product suite and how it addresses the demand for shift-left software development in the integrated circuit development process, visit: www.siemens.com/innexis
About Siemens
Siemens Digital Industries Software helps organizations of all sizes digitally transform using software, hardware and services from the Siemens Xcelerator business platform. Siemens' software and the comprehensive digital twin enable companies to optimize their design, engineering and manufacturing processes to turn today's ideas into the sustainable products of the future. From chips to entire systems, from product to process, across all industries. Siemens Digital Industries Software – Accelerating transformation.
Note: A list of relevant Siemens trademarks can be found here. Other trademarks belong to their respective owners.
Heidelberg Instruments Reports Major Orders for the VPG+ 1400 FPD Volume Pattern Generator from Leading Asian Photomask Manufacturers
Heidelberg Instruments Reports Major Orders for the VPG+ 1400 FPD Volume Pattern Generator from Leading Asian Photomask Manufacturers
Heidelberg, Germany – Heidelberg Instruments has secured two major orders for its VPG+ 1400 FPD Volume Pattern Generator from leading photomask manufacturers in Asia, with a total order value between EUR 9 million and EUR 10 million. Deliveries are scheduled for 2025.
“These significant order intakes mark major milestones for the company, reinforcing our market position and driving further innovation and growth in the display technology sector”, says Alexander Forozan, VP of Global Sales and Business Development.
The VPG+ 1400 is Heidelberg Instruments’ largest system, specifically designed for large-format photomask patterning in the flat panel display (FPD) industry. It supports mask sizes up to 1400 x 1400 mm², making it ideal for various flat panel display generations (G4 to G8). The VPG+ 1400 sets a new standard for high-throughput photomask production, offering the precision and scalability required for large displays. Additionally, it delivers the accuracy needed to produce large-area halftone photomasks for flat panel displays.
Equipped with advanced metrology and alignment features, including Cognex AI-based image recognition, the system ensures precise alignment for multilayered masks. Its linear and nonlinear coordinate corrections further enable precise overlay across tools.
By addressing the diverse exposure needs of customers, Heidelberg Instruments' large-area VPG+ Volume Pattern Generators have proven to be valuable assets in display photomask production lines.
Agileo Automation Launches The E84 PIO Box For The Enhanced Compliance Testing Of Semiconductor Equipment With SEMI Standards
Innovative plug-and-play device helps conduct comprehensive equipment compliance tests for automatic carrier delivery in automated fabs
SEMICON Europa, Munich, Germany, November 12, 2024 – Agileo Automation, a leading provider of control and connectivity solutions for global semiconductor equipment manufacturers, today launches the E84 PIO Box at Booth #C2848. This handheld device offers a new lightweight interface for fab staff to test semiconductor equipment software for compliance with SEMI’s E84 and GEM300 standards suite for automatic carrier delivery. It improves the readability, identification, and validation of E84 signal exchanges and functional aspects in cleanrooms or workshops. Integrated with Agileo Automation’s Speech Scenario software that emulates the fab host and validates the SECS/GEM interface with predefined test scenarios, the E84 PIO Box can easily emulate automated carrier delivery systems such as overhead hoist transport or automated guided vehicles. It is able to detect non-compliance and other functional issues thanks to its close alignment with SEMI’s E84 standard. The device features a DB25 connector for easy integration with E84 passive systems such as a load port and connects directly to a PC via a single USB cable for both data and power supply.
“In highly automated fabs, even minor carrier delivery issues can lead to costly downtime. Our E84 PIO Box is designed to rigorously validate nominal and error cases, ensuring seamless operations and fast recovery, benefiting both equipment manufacturers and facilities alike,” explains Marc Engel, CEO of Agileo Automation. “Early adopters have seen significant improvements in overall equipment software quality and now approach each software update with greater confidence, backed by consistent testing results.”
About Agileo Automation
Since its inception in 2010 in Poitiers, France, Agileo Automation has empowered global semiconductor equipment manufacturers to optimize their production machines with control, communication, data acquisition, and testing solutions, enabling their deployment in large-scale fabs worldwide. At the heart of Industry 4.0, Agileo’s A²ECF-SEMI framework provides a robust foundation for developing equipment controller software, leveraging the SEMI SECS/GEM and GEM300 standard suites. As a member of SEMI and the OPC Foundation, Agileo is a key contributor to the development and integration of industry standards such as SEMI standards and OPC Unified Architecture (OPC-UA). For more information, please visit our web site or follow us on LinkedIn.
PDF Solutions announces industry leaders speaking at its AI Executive Conference on Dec 12th, 2024, in San Francisco
PDF Solutions, Inc. (Nasdaq: PDFS), a leading provider of comprehensive data solutions for the semiconductor ecosystem, today announces the list of industry leaders speaking at its AI Executive Conference to be held on December 12th, 2024, in San Francisco, CA.
This event features keynotes, presentations, panels and demonstrations offering insights into the power of AI to transform semiconductor design and manufacturing. It includes talks on the state of art and best practices to design, deploy, scale and manage AI/ML solutions across the global semiconductor industry from PDF Solutions executives, other industry thought leaders, solutions experts and partners and users.
Three keynote presentations will look at how AI is currently being deployed in semiconductor manufacturing. Aziz Safa, Vice President and General Manager at Intel, will describe “How Analytics and AI are helping to transform a leading semiconductor company.” Smitha Mathews from ADI will discuss how semiconductor companies can “Get ready for AI” and the lessons learned from a real-life deployment. John Kibarian, PDF Solutions’ CEO will explain how AI is the next evolution of PDF Solutions portfolio.
Confirmed speakers include:
Aziz Safa Intel, VP and GM Analytics and Automation
Smitha Mathews Analog Devices, Senior Manager, Data & Analytics Strategy
Mike Campbell Qualcomm, Senior VP Engineering
Shyam Gooty Microsoft, Senior Director Product Engineering
Jean Philippe Fricker Cerebras, Founder and Chief System Architect
Anton Devilliers TEL, VP RnD
Jayant D’Souza Siemens, Principal Technical Product Manager
Marc Hunter Siemens, Director Product Management
Ken Butler Advantest, Senior Director Applications Marketing
Eli Roth Teradyne, Product Manager
Sunil Gandhi SAP, Sr Director Industry Executive, High Tech
Jason Schnitzer Yurts, CTO
Steve Mahoney Yurts, VP Product Management
Handel Jones International Business Strategies (IBS), founder and CEO.
Date: December 12, 2024
Following the 70th Annual IEEE International Electron Devices Meeting.
Location: St. Regis Hotel 125 3rd St San Francisco, CA 94103
About PDF Solutions
PDF Solutions (NASDAQ: PDFS) provides comprehensive data solutions designed to empower organizations across the semiconductor ecosystem to improve the yield and quality of their products and operational efficiency for increased profitability. The Company’s products and services are used by Fortune 500 companies across the semiconductor ecosystem to achieve smart manufacturing goals by connecting and controlling equipment, collecting data generated during manufacturing and test operations, and performing advanced analytics and machine learning to enable profitable, high-volume manufacturing.
Founded in 1991, PDF Solutions is headquartered in Santa Clara, California, with operations across North America, Europe, and Asia. The Company (directly or through one or more subsidiaries) is an active member of SEMI, INEMI, TPCA, IPC, the OPC Foundation, and DMDII. For the latest news and information about PDF Solutions or to find office locations, visit https://www.pdf.com/.
Companies across the semiconductor value chain must respond to a dynamic horizon as the ISSB Standards are adopted by securities regulators, standard-setters and stock exchanges around the world. At the same time, investors are asking companies to voluntarily transition from the TCFD recommendations to the ISSB Standards to meet their information needs.
To clarify what the ISSB Standards mean for the semiconductor value chain, SEMI is pleased to collaborate with the IFRS Foundation, which is the organizational seat of the ISSB. Our webinar, ISSB Standards Adoption and Reporting for the Semiconductor Value Chain, outlines the stakes for companies, demonstrates the business value of the Standards (IFRS S1 and IFRS S2), answers audience questions, and provides a venue for information exchange. There will be a deep dive into implications for climate reporting under IFRS S2 after a high-level look at the background and workplan of the ISSB.
Our distinguished speakers from IFRS Foundation are Neil Stewart, Director of Corporate Outreach, and Jing Zhang, Head of Climate Research.
This event is part of the SEMI webinar series, “Global State of Play: Sustainability Regulations, Reporting, & Incentives.” This series offers semiconductor industry professionals the chance to interact with top-tier experts on the most pressing challenges in compliance, disclosure, and strategy for sustainable business.
Speakers
Neil Stewart, Director of Corporate Outreach, IFRS Foundation
Neil Stewart is the International Sustainability Standards Board’s New York-based Director of Corporate Outreach, working with preparers, industry associations, the accounting profession and consultants to build awareness and understanding of the ISSB Standards and SASB Standards. Neil joined SASB in 2020 from Citigroup.
Jing Zhang, Head of Climate Research, IFRS Foundation
Jing Zhang is Head of Climate Research on the International Sustainability Standards Board’s technical staff. Previously he was the Global Head of Quantitative Research at Moody’s Analytics. Jing has numerous published books and research papers on financial risk, including the Risk Publications book “Climate Change: Managing the Financial Risk and Funding the Transition.” Jing has a PhD from the Wharton School of the University of Pennsylvania.
Worldwide, companies in the semiconductor value chain are undergoing paradigm shifts in how they report sustainability-related risks and opportunities to stakeholders in government and capital markets.
Semiconductor manufacturing and design firms, together with their business partners, face heightened pressure to report on their performance related to climate transition, human capital management, supply chain management, and a host of other environmental, social, and governance issues.
On one hand, companies face a patchwork of reporting rules conditioned on where they do business. On the other hand, a global baseline of sustainability-related disclosures ushered in by the IFRS Foundation’s International Sustainability Standards Board (ISSB) is gathering momentum.
Times
Multiple sessions available!
EMEA: Thursday, January 23, 2025 6:00-7:00 pm Central European Time (AM Session - 9:00-10:00 am Pacific)
America: Thursday, January 23, 2025, 9:00-10:00 am or 4:00-5:00 pm Pacific Time
Asia Pacific: Friday, January 24, 2025 9-10 am Japan Standard Time (PM Session) 4-5 pm Pacific)
New horizons for semiconductors have been revealed by innovations in heterogeneous integration, especially due to the availability of an abundance of inter-chiplet wires. All this has implications on security leading to new challenges as well as opportunities. This talk presents an overview on how prior work on 2D SoCs may or may not be helpful in addressing this challenge.
Meet the Speakers
Guest Speaker
Ankur Srivastava Director of the Institute for Systems Research University of Maryland Biography
Moderator
Warren Savage Researcher at University of Maryland Applied Research Laboratory for Intelligence and Security Biography
The ESD Alliance, a SEMI Technology Community, is hosting a webinar series, "Savage on Security," moderated by Warren Savage, Researcher at University of Maryland, Applied Research Laboratory for Intelligence and Security.
ESD Alliance Webinar: Security Constructs for Heterogenous Integration
Savage on Security Webinar Series #1
Recording
Recorded January 23, 2025
Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.
If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!
Questions? Contact your local staff coordinator: Click here
1:30 pm - 4:30 pm
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Add to Calendar2024-12-13 13:30:002024-12-13 16:30:00Information & Control Japan TC Chapter MeetingInformation & Control Japan TC Chapter Meeting Date: Friday, December 13, 2024Time: 1:30 pm - 4:30 pm JSTVenue: Room 702, International Conference Tower 7F, Tokyo Big Sight, Tokyo, Japan in conjunction with SEMICON Japan + OVTCCM (Hybrid) AGENDA Standards Contact Information:Takeaki HirabaraSEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click hereRoom 702, International Conference Tower 7F, Tokyo Big Sight, 3-11-1, Ariake, Koto-ku Tokyo 1350063 JapanSEMI.org[email protected]Asia/Tokyopublic
Asia/Tokyo
Physical Interface & Carrier (PI&C) Japan TC Chapter Meeting
Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.
If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!
Questions? Contact your local staff coordinator: Click here
9:00 am - 12:00 pm
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Add to Calendar2024-12-12 09:00:002024-12-12 12:00:00Physical Interface & Carrier (PI&C) Japan TC Chapter MeetingPhysical Interface & Carrier (PI&C) Japan TC Chapter Meeting Date: Thursday, December 12, 2024Time: 9:00 am - 12:00 pm JSTVenue: Room 702, International Conference Tower 7F, Tokyo Big Sight, Tokyo, Japan in conjunction with SEMICON Japan + OVTCCM (Hybrid) AGENDA Standards Contact Information:Takeaki HirabaraSEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click hereRoom 702, International Conference Tower 7F, Tokyo Big Sight, 3-11-1, Ariake, Koto-ku Tokyo 1350063 JapanSEMI.org[email protected]Asia/Tokyopublic
Asia/Tokyo
Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.
If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!
Questions? Contact your local staff coordinator: Click here
9:00 am - 12:00 pm
Off
Add to Calendar2024-12-11 09:00:002024-12-11 12:00:00EH&S Japan TC Chapter MeetingEH&S Japan TC Chapter Meeting Date: Wednesday, December 11, 2024Time: 9:00-12:00 (JST)via SEMICON Japan @Tokyo Big Sight Conference Tower 7F Room 701 + OVTCCM (Hybrid) AGENDA Standards Contact Information:Hiroshi SatoSpecialist, Standards & EHS, SEMI JapanEmail: [email protected]: +81.3.3222.6018 NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click hereSEMI Japan Tokyo Big Sight @ Room 701, 7F, Conference Tower 3-11-1 Ariake Koto-ku Tokyo 1350063 JapanSEMI.org[email protected]Asia/Tokyopublic
Asia/Tokyo
