Verific Design Automation today affirmed its position as the leading provider of front-end platforms powering an emerging electronic design automation (EDA) space by collaborating with a group of well-funded artificial intelligence (AI) EDA startups.

These new AI EDA companies use Verific’s unsurpassed language support for fast, accurate large language model (LLM) development, speeding time to market for products that range from functional verification, chip design to code development.

AI EDA providers PrimisAI and Silimate, founded by former chip designers, will be in the Verific booth (#1414) AI showcase at the 61st Design Automation Conference (DAC) June 24-26 at Moscone West in San Francisco.

“This new and exciting market segment is about to change the entire makeup of the EDA industry,” says Rick Carlson, vice president of Verific. “We are about to see a variety of tools, technologies and methodologies destined to change the way chip design and verification is done.”

Introducing the EDA Startups Ushering in the Era of AI EDA
PrimisAI and Silimate will be showcased in the Verific DAC booth and present their unique use of AI technology to eliminate error-prone repetitive tasks for efficient and more productive chip design.

PrimisAI offers a generative AI solution for chip design with advanced language-to-code and language-to-verification capabilities through its interactive AI assistant to address complex hardware challenges across the entire design stack from concept to bitstream/GDSII. RapidGPT, unveiled earlier this year, lets engineers interact with their design and the entire EDA ecosystem with a natural language interface, boosting productivity and accelerating time-to-market. Founded by serial entrepreneur Naveed Sherwani who serves as chairman and CEO, PrimisAI is backed by two early-stage investors.

“Verific’s front-end platform lived up to its well-earned status of industry standard as we implemented it in RapidGPT,” remarks Pierre-Emmanuel Gaillardon, CSO of PrimisAI. “The robustness and quality of the Verific front-end platform ensured we would deliver a tool that would give engineers a seamless and efficient workflow.”

Silimate, backed by Y Combinator, is building the co-pilot for chip designers to help build better chips faster. Silimate finds functional bugs, predicts power, performance and area (PPA) issues, and recommends real and accurate fixes in real time, and is already being used by chip teams building complex IP and SoCs. Co-founders Ann Wu and Akash Levy previously built chips and EDA tools at Apple, Stanford, NVIDIA, and Synopsys.

“Verific consistently produces quality products and offers exceptional quality support,” comments Wu. “Their parsers are fantastic and result in very quick tool bring-up times for our customers.”

Metalware co-founded by Ryan Chow and Andrew Nedea is another Verific front-end platform user. It was started with initial funding from Y Combinator with the mission to accelerate embedded development using AI technology after personally experiencing repeated bottlenecks in embedded software at SpaceX. The Metalware AI EDA tools help designers rapidly write HDL and embedded C/C++ by combining insights from manuals, datasheets and code, offering 10x faster development by automating low-level programming.

“Verific embodies our stated goals to reduce the time it takes to design chips and systems,” affirms Chow. “Verific and its team of experienced EDA engineers have shown repeatedly that its front-end platforms enable a project that would normally take days to be completed in hours.”

Another AI EDA startup in stealth mode is also a new Verific user. Details will be announced shortly.

DAC AI Showcase
Verific will demonstrate its SystemVerilog, Verilog, VHDL and UPF front-end platforms, while PrimisAI and Silimate will be in the Verific DAC Booth #1414 at various times of the day to give 10-minute presentations.

DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

To arrange a demonstration or private meeting, send email to [email protected]

DAC registration is open.

About Verific Design Automation
Verific Design Automation is the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effective worldwide. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry since it was founded in 1999.

Engage with Verific at:
Email: [email protected]
Website: www.verific.com
LinkedIn: https://www.linkedin.com/company/verific-design-automation-inc/
Facebook: https://www.facebook.com/Verific-Design-Automation-100448363329771/

• Read more about Verific’s Front-End Platforms Now Powering AI EDA Startups, Serving as Foundational Technology for a New and Emerging Market

Primarius Technologies will demonstrate its entire portfolio of EDA toolchain and one-stop design enablement solutions that integrate advanced parallelization technologies with industry-proven modeling and simulation engines at the 61st Design Automation Conference (DAC) June 24-26 at Moscone West in San Francisco.

Also announced today: Primarius acquired Magwel N.V., provider of 3D solver- and simulation-based layout analysis and design solutions for digital, analog/mixed-signal, power management, automotive and RF ICs, and launched ESDiTM, a chip-level human body model (HBM) analysis platform and power device design, and PTMTM, a layout verification tool family.

Demonstrations will highlight Primarius’ fast, accurate device modeling and cell library characterization and circuit simulation solutions based on its continuous innovation and R&D expertise, including:

• SDEPTM, the spec-driven extraction platform that builds auto model extraction flows for fast SPICE model extraction, a key engine enabling efficient Design-Technology Co-Optimization (DTCO), and an extended capability on top of the de facto golden-standard SPICE modeling platform, BSIMProPlusTM.
• NanoSpice XTM, the latest high-performance SPICE simulator addressing simulation capacity and accuracy challenges of big post-layout designs at advanced process nodes.
• NanoSpice Pro XTM, the latest FastSPICE simulator with simulation performance and accuracy needs tailored for SRAM, DRAM, Flash and big analog-on-top designs in high-performance computing, mobile, AI and other advanced applications.
• NanoCellTM, the latest standard cell library characterization solution employs advanced distributed parallel architecture technology and cell circuit analysis extraction algorithms embedded with a high-precision SPICE simulator, making it a fast, accurate and easy-to-use alternative to other commercial solutions.
• ESDi, state-of-the art HBM analysis, simulation and verification tool for on-chip ESD protection.

The Primarius Product Portfolio
IC company challenges designing and manufacturing high-end chips have increased sharply. Foundries and IDMs need to provide their design customers with more comprehensive and accurate SPICE models, more reliable and complete PDKs, and more coverage of standard cell library within shorter development cycles. Chip designers also require stronger COT capabilities to work with device engineers to customize process and devices, develop customized SPICE models, and perform re-characterization of cell libraries based on actual applications.

Primarius provides complete EDA toolchain and a one-stop design enablement technical development solutions. Innovations like these can shorten the SPICE model development cycle from several months to a few weeks or even hours for quick iteration addressing the efficiency bottleneck of DTCO. The advanced simulation technologies speed-up challenging circuit simulation by several times, and the latest cell library characterization solution provides the best throughput with near-linear scaling on thousands of x86 or ARM CPU cores on a computer farm or public cloud.

It aims to enable faster turnaround from technology development to advanced chip designs. Solutions include advanced analysis capabilities for high-sigma yield, aging, EM/IR, ESD, signal integrity and more targeting optimum yield and power, performance and area (PPA).

Primarius also provides the 9812 series, an industry-golden low frequency noise testing system used by most industry-leading semiconductor companies worldwide. Its latest release, 9812AC, is the only commercial low-frequency noise system under AC excitation and designed for the most advanced process development and chip designs.

Magwel N.V. Acquisition
Primarius acquired Belgian-based Magwel N.V. driven by broad market demand and technological evolution, integrating its chip-level HBM ESD analysis platform, the power device design and layout verification tool suite and other technologies into the Primarius portfolio.

“Primarius and Magwel share a common goal of enhancing the market competitiveness of overall analog and power semiconductor solutions,” states Dr. Lianfeng Yang, President of Primarius. “Magwel's integration will further advance our strategy to optimize DTCO, enhance our technology portfolio, expand our product coverage and further strengthen and consolidate our market competitiveness.”

Availability and Pricing
Primarius Technologies. Pricing is available upon request.

For more information, visit the Primarius website or send email to [email protected].

Primarius Technologies at 61st DAC
Primarius Technologies will be in DAC booth #1415 Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

To arrange a private meeting or demonstration of the Primarius Technologies product portfolio, send email to: [email protected].

DAC registration is open.

About Primarius
Primarius Technologies (688206.SH) is a global electronic design automation (EDA) company providing innovative DTCO-enabled EDA solutions for advanced technology development, and complex full custom designs including analog, mixed-signal and memory circuits. Primarius provides the industry’s de facto golden SPICE modeling solution adopted by most of the leading semiconductor companies for more than a decade, and leading SPICE/FastSPICE technologies proven by leading memory and SoC design companies worldwide. Its design enablement EDA solutions enable a full coverage of fab technology development and fabless COT flow development including device testing systems, SPICE modeling and PDK development solutions, and standard cell library characterization solutions. Built around an innovative SPICE/FastSPICE dual engine, Primarius provides a complete circuit simulation and analysis solution with comprehensive high-sigma yield and signal integrity analysis, aging and EM/IR, ESD simulation and advanced circuit checking capabilities. Primarius also provides a complete full custom design environment with advanced circuit design and optimization, layout automation and physical verification functions, and hierarchy design planning and timing analysis solutions for advanced SoC designs. Visit Primarius Technologies for more information.

• Read more about Primarius to Feature Fast, Accurate Modeling, Characterization, Simulation Solutions at 61st Design Automation Conference

Axiomise, a company noted for enabling formal verification adoption, today announced the formation of its Technical Advisory Board and its first two members, Dr. Vidya Chandran Darbari and Colin McKellar.

Dr. Darbari is an Axiomise co-founder and company director as well as Senior Lecturer in Structural Biology at Queen Mary University of London (QMUL). McKellar, formerly Vice President of Imagination Technologies, is currently Senior Director of Hardware at X-Silicon Inc.

“Vidya and Colin have long served as my unofficial advisers and confidants as I built Axiomise from the ground up,” remarks Dr. Ashish Darbari, founder and CEO of Axiomise. “Formalizing our relationships with Vidya and Colin will further strengthen the company and the expertise of our formal verification experts.”

“I have had the pleasure of watching Axiomise grow from early startup to a formidable verification provider and I couldn’t be prouder,” states Dr. Darbari. “I look forward to adding my voice as a member of the Technical Advisory Board.

My relationship with Ashish goes back to the early days of Imagination,” notes McKellar. “I watched with amazement and respect as he implemented a rigorous formal verification flow that caught bugs that would have forced costly respins and threats to the company’s good name and reputation.”

About Dr. Vidya Chandran Darbari
Dr Vidya Chandran Darbari, an Axiomise co-founder and company director, has a multi-disciplinary record combining medicine, life sciences, mathematics and technology. A leader and key contributor who leads from the front, Dr. Darbari helped steer Axiomise from its early stages to establishing it as a global leader in formal verification consulting and services, training and RISC-V solutions. She is a senior lecturer at the Queen Mary University of London with several impactful publications in high-end journals including Nature and Science. Dr Darbari received her Bachelor of Medicine, Bachelor of Surgery (MBBS) degree from Seth G.S. Medical College (KEM Hospital) in Mumbai, India, before completing her Master of Technology (MTech) degree from Indian Institute of Technology (IIT) Bombay. Dr. Darbari obtained her Doctorate degree from the University of Cambridge. She has been recognized for her innovative research through Biochemical Society Early Career Award, British Crystallographic Society Early Career prize and recently a Research Excellence Award by the Science and Engineering Faculty at QMUL.

About Colin McKellar
Colin McKellar brings the customer experience to the Axiomise team having been a key player in driving customer engagements in his previous roles with Apple, Intel, TI, SiFive and SEGA among others. He started his career in electronics 30 years ago in Sony Broadcast and Professional working on HD video encode and decode. Most of his career was spent working at Imagination Technologies as a key contributor to the graphics IP roadmap and was instrumental in bringing in and maturing a world-class verification infrastructure including simulation, formal verification and large FPGA, emulation and silicon farms. McKellar joined X-Silicon in 2023 with the responsibility to drive product and execution for bringing graphics and AI acceleration to the RISC-V ecosystem. He has a wealth of design and verification experience across GPU, CPU, AI and SoC chips successfully managing large multinational teams of more than 200 engineers.

About Axiomise
Axiomise is accelerating formal verification adoption through its unique combination of training, consulting, services and specialized verification solutions for RISC-V. Axiomise was founded by Dr. Ashish Darbari, FBCS, FIETE, DPhil (Oxford), who has been a formal verification practitioner for more than two decades with 60 patents in formal verification and over 70 publications.

Engage with Axiomise at:
Website: www.axiomise.com
Twitter: @axiomise
LinkedIn: https://www.linkedin.com/company/axiomise/
Facebook: https://www.facebook.com/axiomise

• Read more about Axiomise Names Two Executives to Newly Formed Technical Advisory Board

Sunnyvale, USA - Meylan, FRANCE – May 29, 2024 Numem - a leader in high-performance Memory IP Cores and Memory Chip/Chiplet based on its patented NuRAM (MRAM) and SmartMem technologies, and IC’ALPS - a leader in ASIC/SoC design and supply chain management, have pooled their expertise to meet the challenge of developing an ambitious integrated circuit with RISC-V processors, 2MBytes of NuRAM and a DSP/AI Custom Datapath Accelerator. The Custom SoC was developed in an advanced technology node.

This SoC has been designed and implemented to highlight the Numem high-performance, low power Memory subsystem with a RISC V Processor and AI Accelerator for ultra-low power applications. It has been developed through a close collaboration between Numem and IC’ALPS.

The physical implementation of this integrated circuit was made in a secure space (isolated location, network, and servers, encrypted exchanges, etc.) to meet with the stringent protection of sensitive data required by this program.

“We were very pleased with the collaboration and quality of service provided by IC’ALPS which made this on-time tape out possible and first time functional silicon,” said Jack Guedj, CEO of Numem. NuRAM with SmartMem is a high-performance memory subsystem which is 2-3x smaller and boast significant power reduction over SRAM,” he added.
 
Lucille Engels, COO of IC’ALPS indicated: “The challenges were numerous including: architecture, power domains, protection of the sensitive data, run times pushing improvement of EDA flow and the pressure of the tape out deadline.”

Numem and IC’Alps intend to extend their partnership to serve new customers SoC projects – feel free to contact us.

NUMEM/IC'ALPS with ultra-low-power SoC for Sensor and AI

About NUMEM
Numem, headquartered in Sunnyvale, California, is the leading provider of Memory Subsystem Chip/Chiplet and IP based on proven foundry MRAM process. Numem’s patented NuRAM technology enables best in class power/performance and reliability with 2.5x smaller area and 85x lower leakage power than traditional SRAM. Numem’s SmartMem subsystem technology significantly improves performance and endurance as well as ease-of-use and reliability for high-volume deployment and enables to reach ultra-high bandwidth.
Visit our website at https://www.numem.com or contact us at [email protected].

About IC’Alps
IC’Alps is your one-stop-shop ASIC partner. Based in France (HQ in Grenoble, two design centers in Grenoble and Toulouse), the company provides customers with a complete offering for Application Specific Integrated Circuits (ASIC) and Systems on Chip (SoC) development from circuit specification, mastering design in-house, up to the management of the entire production supply chain. Its areas of expertise include analogic, digital and mixed-signal circuits (sensor/MEMS interfaces, ultra-low power consumption, power management, high-resolution converters, high voltage, signal processing, ARM and RISC-V based multiprocessors architectures, hardware accelerators) on technologies from 0.18 µm down to 5 nm, and from multiple foundries (TSMC, Global Foundries, Tower Semiconductor, X-FAB, STMicroelectronics, etc.). The company is active worldwide in medical, industrial, automotive, IoT, IA, mil-aero and digital identity & security sectors. IC’Alps is ISO 9001:2015, ISO 13485:2016, EN 9100:2018 certified, Common Criteria on-demand, IATF16949-ready, member of TSMC Design Center Alliance (DCA), ARM Approved Design Partner and X-FAB’s partner network. More information on www.icalps.com and follow us on https://www.linkedin.com/company/ic-alps

• Read more about NUMEM & IC'ALPS Collaborate to Develop an ultra-low-power SOC for Sensor and AI applications