Competition in the semiconductor industry is becoming fiercer and advanced package technology has become important for achieving low-power and high performance computing. As the Moore’s law reach the limitation, Si fabrication process need extremely high cost solutions such as multiple patterning and EUV (Extreme Ultra-Violet) lithography. In spite of high cost Si fabrication process, chip size is increased over the reticle size limit by adding more and more functional blocks for high performance computing. In particular, with the continuous demand for higher performance and capacity in memory products, the amount of data created, processed, stored and transferred is increasing tremendously. In order to overcome these challenges, advanced package based on RDL (Re-Distribution Layer), flip chip bonding, and TSV (Through Silicon Via) have been actively used for heterogeneous integration in electronic packages since the past decade. The heterogeneous integration and chiplet has been attracting a lot of attention since it enables higher bandwidth with low power consumption at reduced cost. 2.5D Si interposer architecture has been widely used for horizontal interconnection between logic to logic and logic to high bandwidth memory integration. 3D stacking architecture is for vertical interconnections enabling small form factor, increasing signal speed, reducing power consumption and power dissipation. In this talk, recent advanced package technology and key roadmap in Samsung Electronics will be shared for mobile and AI/HPC product.

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Co-Packaged Optics is the combination of photonic integrated circuits and electronic circuits at a system packaging level. The essential need is to get light in and out of the system, usually from optical fibers, with the least losses and ease of manufacturing. Photonic integrated circuits (PICs) are fabricated in CMOS semiconductor fabrication facilities, which allows manufacturers to take advantage of the large installed base of tools and processes. However, electronic packaging is currently not equipped to handle the challenges associated with packaging advanced photonic devices. In this presentation we explore some of these challenges for optical coupling such as sub-micron alignment tolerances, sensitivity to temperature variations, optical losses, and a lack of standards. The end objective is to have optical coupling look like electronic coupling. At NYCREATES/AIM Photonics, we have learned that the best results are obtained when the PIC manufacturing and packaging processes are co-designed to better achieve low-loss coupling, particularly between photonic integrated circuits and other elements in the system. A complete “end-to-end” approach includes customizing the PIC process, wafer manufacturing including interposers and heterogeneous integration, electronic photonic design automation, and electronic-photonic test, assembly and packaging capabilities. A complete approach will lead to reliable and affordable solutions that will ensure the manufacturing-readiness of this critical technology for decades to come.

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Rapid growth of generative AI at this moment has never been experienced for a few decades and it makes surprising impact to human experience and semiconductor industry as well. High bandwidth memory (HBM) which started from memory solution for high-end graphic applications has being emerged as a key driver accelerating the growth of AI industry due to remarkable advantages on the smaller latency between memory and GPU.

SK hynix has been the pioneer of HBM in all of history and firstly wrote a new record by the world-first development of HBM package in 2013. More remarkable footprint in the HBM history was the world-first adoption of the mass reflow bonding and molded underfill (MR-MUF) technology to the HBM 4Hi and 8Hi in 201, which nobody has never tried due to its notorious difficulties of process and material technologies. In this effort, SK hynix is providing a state-of-the-art of HBM products with highest memory bandwidth and memory capacity, highest power efficiency, and superior thermal dissipation ability and its package technology is a core competency leading the memory renaissance in the post-pandemic era.

In align with HBM technology innovation, there are continuous changes in 2.5D system-in-package (SiP) in order to improve the memory bandwidth and accommodate higher memory capacity. There has been many different types of proxy package structure to assure the HBM quality and reliability but it is obviously not certain whether HBM package can guarantee all the possible quality and reliability risks due to many possible changes of HBM and SiP packages in the future. In this paper, we would like to introduce several ways to evaluate the thermal and electrical characteristics of HBM and its package reliability.

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The AI era has arrived and to enable and perpetuate it, the semiconductor advanced packaging (AP) industry needs to innovate in a torrid pace to keep in tandem the exponential growth of the Gen AI computing power.
Rising to the challenge, ASMPT has been leveraging its first mover market position in advanced packaging to continue innovating its end-to-end solutions to scale with the latest packaging architecture with the most demanding chiplet interconnects and heterogeneous integration formats.
Going forward, the AP industry shall undergo a “Power of N” transformation where interconnect pitch shall shrink rapidly along with thinner and bigger package formats, demanding new technologies in materials, process and equipment signaling a need for a complete and robust ecosystem to evolve for Gen AI to continue scaling.

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As artificial intelligence (AI) continues to advance, the demand for high-performance computing has never been greater. Advanced packaging technologies play a pivotal role in meeting these demands by enhancing the performance, power efficiency, and integration density. This presentation explores the impact of various advanced packaging solutions, including 2.5D with Si interposers, 2.3D with RDL interposers, and 3D packaging technologies, on the development and optimization of AI systems.
We will delve into the specifics of 2.5D packaging, where Si interposers enable the integration of heterogeneous dies side by side, allowing for high-bandwidth communication and reduced latency. The presentation will also cover 2.3D packaging with RDL interposers, which offer a cost-effective alternative by utilizing advanced RDL processes to achieve similar benefits as 2.5D, but with potentially lower manufacturing complexity and cost.
Furthermore, we will examine 3D advanced packaging technology, which stacks dies vertically to further enhance integration density and performance. This approach not only maximizes space efficiency but also minimizes interconnect lengths, leading to significant improvements in speed and power consumption which are critical factors for AI applications.
Through a comprehensive analysis, this presentation will highlight how these advanced packaging technologies contribute to the acceleration of AI innovation, enabling more powerful, efficient, and compact AI packaging solutions.

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Big data, artificial intelligence (AI), and high-performance computing (HPC) underscore the critical importance of advanced packaging technologies. Over the past decade, significant progress in 2.5D and 3D heterogeneous integration has led to notable improvements in I/O capacity, performance, cost efficiency, power consumption, and signal speeds for large-scale data processing. 

In particular, 2.5D semiconductor packaging technologies such as EMIB and CoWoS are crucial for increasing I/O connections while reducing the interconnect length between logic and memory components, thereby enhancing performance and reducing latency. 

However, FCBGA substrates used in AI/HPC packaging face considerable technical challenges. These substrates often need to be larger than 100mm x 100mm and consist of more than 20 layers. Furthermore, incorporating advanced technologies like silicon capacitor embedding and bridge integration into large-body FCBGA substrates presents additional hurdles as the industry moves towards next-generation packaging solutions. 

This presentation thoroughly explores the latest technology trends in FCBGA substrates. 

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As the demand for higher performance, greater miniaturization, and improved thermal management continues to grow in the electronics industry, advanced packaging technologies are becoming increasingly critical. Glass substrates are emerging as a key material in this domain, offering unique advantages over conventional organic and silicon-based substrates. This talk explores the present and future potential of glass substrates in advanced packaging, focusing on their electrical, thermal, and mechanical properties that make them suitable for next-generation semiconductor devices.
It will also highlight recent innovations in glass substrate manufacturing, such as through-glass vias (TGVs) and surface modification techniques, which enhance the performance and reliability of electronic components.

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The rapid growth of AI, big data, IoT, and 5/6G communication necessitates the sophisticated computing power and efficiency of semiconductor devices, driving demand for various components such as HPC, GPU, ASIC, FPGA, and HBM. Semiconductor device and equipment industries are also challenging various new technologies to accommodate such diversifying applications and proceed with sustainable development in the era of AI and ICT.
According to the roadmap over the next 10 years, semiconductor technologies are expected to develop into the scaling technologies to further extend the existing Moore's Law and hybrid device technologies that integrate legacy nodes and advanced nodes into one. Therefore, in this presentation, we will look at the latest logic technology roadmap and introduce new process technologies to implement it.

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Materials innovation within the Semiconductor industry has been a driving force since the planar 2D MOSFET to the current 3D gate-all-around (GAA) transistor architectures and will continue its criticality as we embark on 500-layer flash memory designs and Angstrom level critical interconnect dimensions. To achieve these once incomprehensible levels of lateral and vertical scaling, device design engineers and manufacturers are increasingly relying on disruptive materials innovation to enable the density and performance gains required at each successive technology node. As the performance requirements for the most advanced devices become more challenging, materials have shown to have an increased contribution to device performance over scaling and design. This has led to a greater portion of the periodic table being incorporated into semiconductor processing.

The integration of new materials, such as novel photoresists, interconnect metals & alloys, ultra-pure polymers, chemically modified polymer membranes, and formulated chemicals, into the chip fabrication increases process complexity and makes yield ramps more challenging. With more process steps in the overall device build, speed to yield and process integrity are more critical than ever to achieve technology qualification schedules. This presentation will focus on Entegris’ approach to materials innovation, the integration of these novel materials coupled with co-optimized solutions enabling industry technology roadmaps and yield requirements while preserving integrity of delivery and process control.

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Resonac has started Packaging Solution Center as new R&D center to propose one-stop solution for customers in 2018 and established the co-creative packaging evaluation platform “JOINT2” with leading companies to accelerate the development of advanced materials, equipment and substrates for 2.xD and 3D package in October, 2021.

2.xD and 3D packages require to connect chips and components in high density, therefore, both wiring pitch and vertical interconnect dimension must be finer and finer. At the same time, in order to achieve better performance, more and more chips are integrated together and thus the package size is increasing. To meet these requirement, we are developing fine vertical/lateral interconnect technology and the study of fabrication and reliability for the extremely large 2.5D advanced package.
The presentation will cover the significance and strengths of JOINT2, and updates on research and development.

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EUV lithography infrastructure has become the critical element of semiconductor industry to enable the device scaling down. It consists of not only light source, optical system but also masks, photoresist. The EUV stochastic effects present challenges to optimizing EUV resist resolution, line edge roughness, and sensitivity simultaneously. To overcome these challenges, Lam introduced the new dry resist combined with the new dry development technology.

Lam’s EUV dry resist, coupled with ASML’s EUV scanners and Lam’s holistic patterning solutions, will extend the patterning roadmap (Moore’s Law) for the next 10 years and beyond by offering a high-resolution, high-fidelity, defectivity-free, and greener solution for ≤32nm pitch L/S, and ≤40nm pitch pillar and contact hole EUV patterning in the fab. EUV dry resist technology also has been validated demonstrating superior dose-to-defectivity for <32nm pitch L/S, well suited for logic applications. Lam’s EUV dry resist is uniquely suited for future HiNA EUV patterning thanks to robust resist thickness scaling while maintaining high etch selectivity and high contrast.

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As demand for chips surge, the semiconductor industry is struggling to reduce its environmental footprint. While the environmental impacts of semiconductor (and electronic products that depend on them) have mostly been liked to ‘manufacturing’ and ‘use’ phases of products which consume a significant amount of water and energy, the attention is shifting to the 'material extraction’ and ‘end-of-use’ phases of products following concerns over the e-waste issue. In this presentation, I will focus on the latest findings of the global e-waste challenge, what this means from the materials perspective, and its implications to product design and manufacturing. I will also introduce SK hynix's strategy and targets towards improving the circularity of products, and our partnership with customers/vendors to achieve a common goal.

Fluorine compounds exhibit exceptional physical properties that set them apart from other organic materials. Consequently, they have been utilized as core materials to enhance the functionality, performance, and value of products across various key industries including electrical and electronics, semiconductors, displays, and automobiles.
However, on March 22nd of last year, the European Chemicals Agency (ECHA) issued a report imposing restrictions on the usage of over 10,000 types of per- and polyfluoroalkyl substances (PFASs) across all industries, sparking significant upheaval within the sector.
In this presentation, we will learn in detail about the definition of PFAS, and the content, progress, and schedule of PFAS regulations in Europe and the United States, and contemplate the direction of future technology development.

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As semiconductors become more advanced and the fabrication processing conditions more extreme, the essentiality of a sustainable and secure fluorinated material supply chain plays a vital role in the future of semiconductor manufacturing. The principles of developing this supply chain are directly aligned to support the sustainability and emission roadmaps of the semiconductor industry. Syensqo will introduce the following content:
1) Priorities when Specifying Materials for a Sustainable Supply Chain
2) The Key to Sustainability - Application Segmentation
3) Case Studies

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Growing scientific evidences suggest that certain per- and polyfluoroalkyl substances (PFAS) pose global environmental and health risks. In response, global governments are contemplating measures to limit the use of these chemicals in various industries. However, specific types of PFAS are indispensable and no substitutes are currently available for most chip manufacturing applications in the semiconductor industry. Aligned with the objective of Safer and Sustainable by Design, DuPont has launched a comprehensive program to reduce PFAS usage in photoresist and associated lithography materials. In this presentation, we will provide an overview of DuPont's innovative initiatives and technical challenges encountered in this endeavor.

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Solvents are used extensively in the semiconductor manufacturing process. Solvents are estimated to be responsible for around 7% of the Scope 3 emissions of the semiconductor industry. The typical solvents that are used are produced from fossil resources and with that not in line with net zero ambitions. For more than 20 years Corbion has been supplying biobased ethyl lactate to the semiconductor industry under it’s brand name PURASOLV® ELECT, meeting the stringent requirements of the industry. Typical applications are photoresist for i/g-line / KrF / ArF / EUV, RRC, Edge bead removal and as thinner. Biobased ethyl lactate is sustainable and safe by design: it is produced from renewable resources, non-toxic and safe to workers, biodegradable and offers a significant carbon footprint reduction compared to incumbent solvents. Switching to biobased ethyl lactate thus enables more sustainable semiconductor manufacturing.

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The technological advancement of semiconductor materials is a key factor along with the technological advancement of the process. And recently, the importance of Advanced PKG is increasing, and SK Hynix has achieved the result of improving product performance by developing MR-MUF materials. This proves the importance of materials. In the future, there are more packaging challenges for high-speed memory products such as HBM, and I plan to announce Need for material development to satisfy them.

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The number of transistors in semiconductor chip has been increased twice every two years for more than 50 years, following the famous Moore’s Law and somehow, it was taken to be granted. In reality, it was a big accomplishment with an unimaginable amount of efforts and collaborations, including the development of new materials.

New material has been developed and introduced to improve the performance and capacity of electronic devices through smaller design rules. New Photo Resists (PR) for higher resolution with smaller defects and higher uniformity were developed. And Precursors were also developed to meet the process challenges for the smaller design rules, such as higher aspect ratios. High etch selective Etchant and CMP Slurry with low scratch were requested. And the requirements in new materials are getting tougher and stronger with the evolution of AI, which needs more computing power than ever. Even materials that has never been expected in industry and has been studied only in academia are being actively considered.

Even the worse, the surrounding situation for material development and manufacturing is getting tougher. Environmental regulations are getting tighter. Gases with high global warming potential were begun to be replaced. Recently, EU announced banning PFAS materials in near future and US raised bars for PFAS materials. And carbon zero policy is coming to us slowly but firmly.

In this talk, we will discuss the current status and future direction of material research. We will discuss the development directions to improve the performance of devices and to consider environmental regulations. And we will discuss the virtue of working together as a big one-team to overcome all the obstacles mentioned above in the world of extreme technology.

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Welcome

Pushkar Apte, Smart Data-AI Lead and Strategic Technology Advisor, SEMI

SEMI Perspective

Ajit Manocha, CEO, SEMI

Accelerating Energy-Efficient Computing

Tristan Holtam, GVP, CEO Chief of Staff, Corporate Strategy and Development, Applied Materials

Future of Computing Landscape- Opportunities and Challenges

Jim Sexton, Fellow, IBM

Coffee Break

Chair/Moderator: Gity Samadi, Senior Director of R&D Programs, SEMI

David Fried, Corporate VP, Lam Research

Eric Pop, Pease-Ye Professor of Electrical Engg., Stanford University

Geoffrey Burr, Distinguished Research Scientist, IBM Research

Saif Islam, Professor, Dept. of Electrical & Computer Engg., U. of California, Davis

Ashonita Chavan, Distinguished Member of Technical Staff, Micron

Chair/Moderator: Melissa Grupen-Shemansky, SEMI

Steve Klinger, LightMatter, VP of Product

Jaesik Lee, VP of Package Engineering, SK Hynix

Debendra Das Sharma, Senior Fellow, Intel and Chair of UCIe & CXL Consortium

Boris Vaisband, Asst. Professor, UC Irvine

Chair/Moderator: Jim Sexton, IBM

Evgeni Gousev, Senior Director, Qualcomm; and Chair, Board of Directors, TinyML Foundation

Mirko Prezioso, CEO, Mentium

Wilfred Gomes, CEO, Mueon

Chloe Jian Ma, Vice President, Arm

Chair/Moderator: Pushkar Apte, SEMI

JP Fricker, Founder and Chief System Architect, Cerebras

Cliff Young, Software Engineer, Google DeepMind

Nuwan Jayasena, AMD Fellow

John Hu, Director of Advanced Technology, Nvidia