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26F, xLINK Marunouchi Eiraku Bldg.
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Japan

Standards

Flexible Hybrid Electronics Japan TC Chapter Meeting 

Date: Friday, July 10, 2026

Time: 3:00 PM - 5:00 PM (JST)

via Official Virtual TC Chapter Meeting + SEMI Japan (Hybrid)

Please note that the meeting venue might be changed due to room capacity.  If there is any change, we will inform you once it is confirmed.

 

AGENDA

 

Standards Contact Information:

Nahoko Koga

Coordinator, Standards & EHS, SEMI Japan

Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

 

Questions? Contact your local staff coordinator: Click here

3:00 pm - 5:00 pm Off Add to Calendar 2026-07-10 15:00:00 2026-07-10 17:00:00 Flexible Hybrid Electronics Japan TC Chapter Meeting Flexible Hybrid Electronics Japan TC Chapter Meeting Date: Friday, July 10, 2026Time: 3:00 PM - 5:00 PM (JST)via Official Virtual TC Chapter Meeting + SEMI Japan (Hybrid)Please note that the meeting venue might be changed due to room capacity.  If there is any change, we will inform you once it is confirmed. AGENDA Standards Contact Information:Nahoko KogaCoordinator, Standards & EHS, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today! Questions? Contact your local staff coordinator: Click here SEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi, Chiyoda-ku Chiyoda-ku, Tokyo 1000005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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SEMI Members:  $75

Use your corporate email address during log in to be recognized as a SEMI Member.

Non-Members:  $149

Students:  Free

Contact Basak Ulutas Ozturkler ([email protected]) with a picture of your student ID to receive your discount code.

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High-temperature materials are critical for applications in harsh-environment circuitry, where devices must operate reliably under extreme thermal, chemical, and mechanical stress. In this Master Class, Dr. Shenqiang (Shen) Ren will present a high-throughput ink materials development strategy enabled by non-equilibrium processing and hybrid additive manufacturing. This approach enables rapid synthesis, combinatorial screening, and direct integration of functional materials onto diverse substrates. The resulting materials exhibit strong electrical performance, robust adhesion, and long-term stability under harsh operating conditions. This high-throughput framework accelerates the discovery and deployment of printable materials for interconnects, heaters, and EMI shielding, providing a versatile pathway toward next-generation printed electronics designed for extreme environments.

ABOUT THE SPEAKER

Shenqiang (Shen) Ren, PhD
Dr. Shenqiang Ren is a Professor of Materials Science and Engineering at the University of Maryland, College Park, with research interests in emerging functional and structural materials. He received his Ph.D. in Materials Science and Engineering from the University of Maryland, College Park, and subsequently completed postdoctoral training at the Massachusetts Institute of Technology (MIT). 

United States

Shenqiang Ren
Shenqiang (Shen) Ren , PhD
Department of Materials Science and Engineering, Professor
University of Maryland, College Park
Gity Samadi
Moderator
Gity Samadi, PhD
Sr. Director, R&D Programs
SEMI
NBMC Smart MedTech FlexTech

Join us for a focused Master Class with Dr. Shenqiang (Shen) Ren, exploring the development of high‑temperature materials for harsh‑environment printed and flexible hybrid electronics (FHE). This session will examine how devices can be engineered to operate reliably under extreme thermal, chemical, and mechanical stress—conditions where conventional materials and processes often fail.

The Master Class will also highlight how this high‑throughput framework accelerates the discovery and deployment of printable materials for interconnects, heaters, and EMI shielding, offering a versatile pathway toward next‑generation printed electronics designed for extreme conditions.

10:00 am - 12:00 pm Off Add to Calendar 2026-08-26 10:00:00 2026-08-26 12:00:00 FEMC#30 High Throughput Material Development for Extreme Environment Printed Electronics Join us for a focused Master Class with Dr. Shenqiang (Shen) Ren, exploring the development of high‑temperature materials for harsh‑environment printed and flexible hybrid electronics (FHE). This session will examine how devices can be engineered to operate reliably under extreme thermal, chemical, and mechanical stress—conditions where conventional materials and processes often fail.The Master Class will also highlight how this high‑throughput framework accelerates the discovery and deployment of printable materials for interconnects, heaters, and EMI shielding, offering a versatile pathway toward next‑generation printed electronics designed for extreme conditions. United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles REGISTER NOW
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Registration

※ Early-bird Registration Deadline: July 8 (Wed), 2026, 17:00 PM (KST)  

 Early BirdOn-siteGroup
SEMI MemberKRW 308,000KRW 385,000KRW 275,000
Non-MemberKRW 363,000KRW 330,000

※ Group registration fee applies to groups of five or more from the same company.
※ For group registration inquiries, please contact SEMI Korea Program Team at [email protected].

Registration
South Korea APS 2026 Business Technical

OVERVIEW

  • Date: July 15(Wed), 2026
  • Time: 08:30 - 17:00
  • Venue: Convention Hall 1, 3F, Suwon Convention Center
  • Language: Korean/English (Simultaneous interpretation will be provided)
  • Organizer: SEMI Korea  

 

SPONSORS

  

 

NOTICE

  • The agenda is subject to change at the discretion of the speakers.
  • Presentation files agreed by speakers will be provided to attendees after the event through SEMI registration website.

 

CONTACT

Convention Hall 1, 3F, Suwon Convention Center South Korea
South Korea

8:30 am - 9:00 am

Welcome Reception

9:00 am - 9:30 am
Greg Roh
Greg Roh
Head of Research Center
Hyundai Motor Securities

2026 Outlook for the Advanced Packaging Industry

9:30 am - 10:00 am
Chee ping Lee
Chee ping Lee
Managing Director, Strategic & Technical Marketing, Advanced Packaging
Lam Research

Making 3DIC Manufacturable for AI: From Vertical Integration to Scalable Production

As AI systems push requirements for higher bandwidth, lower power, and increased integration density, 3D integrated circuits (3DIC) are moving rapidly from development to production. However, scaling 3DIC introduces complex application challenges across the manufacturing flow, where process interactions and control become critical.
This talk examines key 3DIC applications and process challenges, including high aspect ratio TSV etch, void free TSV fill, and dielectric deposition, required for reliable wafer and die level stacking. Emerging applications such as inter die gap fill for advanced chiplets integration and plasma dicing for improved yield, edge quality, and die strength further increase integration complexity and productivity demands.
The presentation highlights Lam Research innovations across etch, deposition and clean processes that enable tighter process windows, improved uniformity, and higher throughput. In addition, equipment intelligence and data driven control are increasingly essential to enhance yield learning and manufacturing productivity. Together, these advances are enabling scalable, high volume 3DIC manufacturing for next generation AI systems.

※ Biography

10:00 am - 10:30 am
Ingu Yin Chang
Yin Chang
ASE

Advanced Packaging: Enabling AI at Scale

The future of compute will not be defined by silicon alone. As AI reshapes industries and economies, advanced packaging has become the foundation of the next era of innovation, enabling unprecedented gains in performance, efficiency, and scale. During his keynote, Yin Chang will explore how breakthroughs in heterogeneous integration, chiplets, and advanced manufacturing are transforming bold AI ambitions into deployable systems, and why AI leadership will depend not only on compute power, but on the ability to integrate and manufacture at scale.

※ Biography

10:30 am - 11:00 am
Shinji Baba
Shinji Baba
Vice President / Head of ATJ R&D Center
Amkor Japan

Advanced Power Module Packaging Technologies

The rapid electrification of automotive and industrial systems is placing increasingly stringent demands on power semiconductor devices in terms of voltage capability, thermal performance, reliability, and system integration. This presentation reviews recent trends in power devices and power module packaging technologies aimed at improving performance while addressing cost and manufacturability constraints.
First, the fundamental differences between digital and power devices are outlined, followed by an overview of power device applications based on silicon (Si), silicon carbide (SiC), and gallium nitride (GaN) technologies, together with Amkor’s product portfolio.
Next, power module packaging technologies are discussed with a focus on key electrical and thermal challenges. Representative solutions, including advanced interconnects, cooling architectures, and embedded power modules, are introduced, along with a brief overview of Amkor’s technology roadmap.
Finally, the role of the Amkor Technology Japan R&D Center in supporting open innovation and global collaboration is briefly discussed.

※ Biography

11:00 am - 11:20 am

Networking Break

11:20 am - 12:30 pm

Panel Discussion

12:30 pm - 1:30 pm

Lunch

1:30 pm - 2:00 pm
minwoo rhee
Minwoo Lee
Master
Samsung Electronics

Advanced Packaging Technology for AI/HPC

The presentation explores advanced packaging technologies designed to meet the escalating performance and power efficiency demands of AI and High-Performance Computing (HPC). To overcome the limitations of traditional semiconductor architectures, System Technology Co-Optimization (STCO) is introduced as a critical framework for managing thermal crosstalk and enhancing heterogeneous integration. The discussion highlights key innovations, including Customized HBM (cHBM) for optimized base-die performance and Samsung's 2.xD packaging portfolio, which encompasses Cube S, Cube E, and Cube R. Specifically, the 2.3D Cube E leverages panel level packaging to enable larger interposers and increased HBM integration, significantly improving productivity and reducing silicon fab burdens. The technical achievements in PLP—such as precise warpage control and the realization of fine RDL patterns (2/2μm)—are detailed to demonstrate their viability for large-scale AI chips. Furthermore, the roadmap extends toward 3D integration and Co-Packaged Optics (CPO) to maximize bandwidth and energy efficiency. Finally, the importance of an ecosystem-wide collaboration is emphasized as the driver for future innovation in "More than Moore" technology. These advancements collectively provide a scalable path toward the next generation of AI hardware acceleration.

※ Biography

2:00 pm - 2:30 pm
YASUSHI ARAKI
Yasushi Araki
Corporate Officer, GM(General Manager) of R&D Div.
SHINKO ELECTRIC INDUSTRIES

Latest Development Status of Glass Core Build-up Substrate

Glass core substrates exhibit low CTE and significantly higher rigidity than conventional organic substrates and are therefore regarded as promising core materials for next-generation build-up packages. However, a major challenge lies in the occurrence of SeWaRe defects (delamination in glass), which arise from thermal stresses induced by the mismatch in the coefficients of thermal expansion (CTE) between the glass material and the build-up resin.
To mitigate this issue, we proposed a structure in which the corner regions of each individual piece are formed from resin. However, considering the thermal history during chip mounting, it became evident that the suppression effect was insufficient. Therefore, an edge‑protection material was applied to relieve the stress concentrated at the edges of each individual piece. As a result, it was confirmed that SeWaRe defects could be effectively suppressed even under thermal loading.
Through these efforts, we successfully developed a glass core build-up package substrate incorporating 11 layers of single‑sided copper wiring (22 layers in total).

※ Biography

2:30 pm - 3:00 pm
Sandeep Sane
Sandeep Sane
Vice President
Lightmatter

Beyond Moore's Law: How Silicon Photonics and Advanced Packaging Are Redefining HPC

AI and data-intensive workloads are outpacing what conventional semiconductor technology can deliver. Two innovations are stepping in to close the gap: Silicon Photonics, which brings optical-speed, low-power data transmission into the data center, and Advanced Packaging, which uses chiplets and 2.5D/3D integration to maximize performance and efficiency at the chip level.
This talk examines how these complementary technologies are reshaping HPC architecture—covering their current state, how they work in tandem, and the key technical and commercial barriers to large-scale adoption.

※ Biography

3:00 pm - 3:30 pm
Amit Oren
Amit Oren
Director CPO Packaging
NVIDIA

CPO Packaging: Challenges and Opportunities

Co-packaged optics (CPO) is emerging as a key enabler for scaling bandwidth while containing power and cost in next-generation AI and cloud infrastructure. By moving optical engines closer to the switch ASIC and shortening high-speed electrical reaches, CPO can reduce SerDes power, ease signal-integrity constraints, and increase overall front-panel bandwidth density. However, delivering these benefits at volume requires new approaches across package architecture, manufacturing, and system integration.
This presentation reviews the main packaging challenges that must be solved to industrialize CPO, including thermal management and heat spreading near high-power silicon, fiber attach and optical alignment tolerances, photonics/laser integration choices, high-density optical and electrical I/O, substrate and interposer selection, and reliability risks such as warpage, CTE mismatch, and contamination control. Test and rework strategy, yield learning, and supply-chain readiness (materials, assembly, and metrology) are highlighted as practical barriers to adoption.
The talk also outlines opportunities created by CPO packaging innovations—such as modular optical tiles, standardized fiber interfaces, advanced lid/heat-sink concepts, and co-design of electrical, mechanical, and optical domains—to unlock higher radix switches and lower system power. Attendees will leave with a structured view of technology tradeoffs, a roadmap of near-term versus long-term packaging options, and actionable considerations for bringing CPO from prototypes to deployable products.

※ Biography

3:30 pm - 3:50 pm

Networking Break

3:50 pm - 5:00 pm

Panel Discussion

Advanced Packaging Summit 2026, under the theme “Packaging the Future of AI – From Silicon to Photon,” will examine the evolution of packaging technologies in the AI era and their broader implications for the semiconductor industry. Featuring presentations by leading industry experts, the summit will explore market shifts driven by the growing demand for AI semiconductors, along with key technologies enabling advanced packaging. The program will also highlight the innovation journey from silicon-based integration technologies to photonics-based interconnects, which are essential to enhancing packaging productivity and scalability. Panel discussions in each session will further provide opportunities to exchange insights on real-world applications, technical challenges, and possibilities for cross-industry collaboration, while exploring new business opportunities and strategic perspectives created by advanced packaging technologies in the AI era.

8:30 am - 5:00 pm Off Add to Calendar 2026-07-15 08:30:00 2026-07-15 17:00:00 ADVANCED PACKAGING SUMMIT 2026 Advanced Packaging Summit 2026, under the theme “Packaging the Future of AI – From Silicon to Photon,” will examine the evolution of packaging technologies in the AI era and their broader implications for the semiconductor industry. Featuring presentations by leading industry experts, the summit will explore market shifts driven by the growing demand for AI semiconductors, along with key technologies enabling advanced packaging. The program will also highlight the innovation journey from silicon-based integration technologies to photonics-based interconnects, which are essential to enhancing packaging productivity and scalability. Panel discussions in each session will further provide opportunities to exchange insights on real-world applications, technical challenges, and possibilities for cross-industry collaboration, while exploring new business opportunities and strategic perspectives created by advanced packaging technologies in the AI era. Convention Hall 1, 3F, Suwon Convention Center South Korea South Korea SEMI.org [email protected] Asia/Seoul public Asia/Seoul
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26F, xLINK Marunouchi Eiraku Bldg.
1-4-1 Marunouchi,
Chiyoda-ku, Tokyo
1000005
Japan

Standards

Information & Control Japan TC Chapter Meeting 

Date: Wednesday, June 17, 2026

Time: 10:00 am - 12:00 pm JST

Venue: SEMI Japan Office Room 1 + OVTCCM (Hybrid)

 

AGENDA

 

Standards Contact Information:

Takeaki Hirabara

Standards & EHS, SEMI Japan

Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

Questions? Contact your local staff coordinator: Click here

10:00 am - 12:00 pm Off Add to Calendar 2026-06-17 10:00:00 2026-06-17 12:00:00 Information & Control Japan TC Chapter Meeting Information & Control Japan TC Chapter Meeting Date: Wednesday, June 17, 2026Time: 10:00 am - 12:00 pm JSTVenue: SEMI Japan Office Room 1 + OVTCCM (Hybrid) AGENDA Standards Contact Information:Takeaki HirabaraStandards & EHS, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click here 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi, Chiyoda-ku, Tokyo 1000005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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Belgium China France Germany India Ireland Italy Japan Malaysia Singapore South Korea Taiwan United States Vietnam Download the white paper Cost Benefit Calc cropped for events page Business Technical Training
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SEMI
United States

9:00 am - 9:15 pm
Peilun Sun headshot
Peilun Sun
Consortium Manager
SEMI

Setting the Stage: Industry Drivers & SCC Initiative Context

• Semiconductor Industry Decarbonization Challenges
• The Need for Quantified Business Cases
• SCC Initiative Background & Development Journey
• Vision for Industry Adoption & Collaboration

9:16 am - 9:34 am
Ben Gross Headshot
Ben Gross
Director DTMS - Sustainability
Applied Materials

SCC Cost-Benefit Calculator Overview & Walkthrough

• Tool Architecture & Methodology
• Key Inputs & Assumptions
• Understanding the Outputs & Metrics
• Live Demonstration & Example Scenario
• Current Limitations & Future Development Opportunities

9:36 am - 9:50 am
Jeff Rudnik Headshot
Jeff Rudnik
Director of Environmental Sustainability & Net Zero
ASM

Industry Use Cases & Practical Applications

• Evaluating Decarbonization Projects
• Comparing Alternative Mitigation Strategies
• Supporting Internal Investment Decisions
• Lessons Learned from Early Applications
• Opportunities for Industry Collaboration

9:51 am - 10:00 am

Open Discussion & Q&A

• Audience Questions
• Feedback & Enhancement Opportunities
• Next Steps & SCC Engagement Opportunity

Smart MFG Sustainability

The semiconductor industry is under increasing pressure to decarbonize its operations, particularly with regard to Scope 1 emissions — direct greenhouse gas emissions (GHG) from owned or controlled sources. Yet many companies face a persistent challenge: how to make a clear, consistent, and financially credible case for emissions reduction investments. To help address this need, the Semiconductor Climate Consortium (SCC) has developed a Cost-Benefit Calculator — a simplified and flexible tool that offers a structured starting point for evaluating carbon emissions reduction projects. The calculator enables users to estimate the Net Present Cost (NPC) per ton of CO₂ equivalent emissions reduction, helping to translate environmental impact into business-relevant terms.

Join SEMI's Semiconductor Climate Consortium (SCC) Scope 1 Working Group and document authors for a webinar discussing their journey creating the Cost-Benefit Calculator and outlining the use cases for this tool.  The Cost-Benefit Calculator is a functional spreadsheet with built in report creation tools. For business managers who need to calculate emissions for Scope 1.

SCC members can download the Cost Benefit Calculator Report here.

9:00 am - 10:00 am Off Add to Calendar 2026-06-16 09:00:00 2026-06-16 10:00:00 SCC: Cost Benefit Calculator Webinar The semiconductor industry is under increasing pressure to decarbonize its operations, particularly with regard to Scope 1 emissions — direct greenhouse gas emissions (GHG) from owned or controlled sources. Yet many companies face a persistent challenge: how to make a clear, consistent, and financially credible case for emissions reduction investments. To help address this need, the Semiconductor Climate Consortium (SCC) has developed a Cost-Benefit Calculator — a simplified and flexible tool that offers a structured starting point for evaluating carbon emissions reduction projects. The calculator enables users to estimate the Net Present Cost (NPC) per ton of CO₂ equivalent emissions reduction, helping to translate environmental impact into business-relevant terms.Join SEMI's Semiconductor Climate Consortium (SCC) Scope 1 Working Group and document authors for a webinar discussing their journey creating the Cost-Benefit Calculator and outlining the use cases for this tool.  The Cost-Benefit Calculator is a functional spreadsheet with built in report creation tools. For business managers who need to calculate emissions for Scope 1.SCC members can download the Cost Benefit Calculator Report here. SEMI United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register Today!
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Registration

SEMI Members: $25
Use your corporate email address during log in to be recognized as a SEMI Member.

Non-Members: $50

Students: Contact Paul Cohen ([email protected]) for student pricing.

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Designing functionally correct, high-performance, and provably secure system-on-chips (SoCs) has become a strategic imperative for modern computing infrastructure. Yet traditional design and verification methodologies are increasingly strained by escalating complexity, massive design scales, heterogeneous integration, and rapidly evolving security threats. Ensuring correctness, scalability, comprehensiveness, and adaptability across the full SoC lifecycle now exceeds the practical limits of conventional toolchains and human-centric workflows.

The emergence of large language models (LLMs) introduces a transformative opportunity for SoC design automation. Beyond natural language understanding and code generation, advanced LLMs demonstrate capabilities in architectural reasoning, specification refinement, vulnerability analysis, and design-space exploration. However, monolithic models alone are insufficient for the multidisciplinary and iterative nature of chip design. An agentic paradigm—where specialized LLM-driven agents collaborate within a coordinated framework—enables modular reasoning, cross-layer verification, security validation, and adaptive decision-making throughout the design process.

This talk will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification. The framework integrates design synthesis, threat modeling, formal reasoning, runtime monitoring strategies, and hardware–software co-verification into a cohesive workflow. Looking ahead, such agentic systems point toward a future of self-optimizing, security-aware, and continuously verified silicon—where AI-driven design environments not only accelerate innovation but also fundamentally redefine how we conceive, build, and trust next-generation microelectronic systems.

 

United States

9:00 am - 9:10 am
Warren Savage
Warren Savage
Researcher
University of Maryland Applied Research Laboratory for Intelligence and Security

Welcome and Introduction

9:10 am - 10:00 am
Mark Tehranipoor
Mark M. Tehranipoor
Distinguished Professor
Department of Electrical and Computer Engineering, University of Florida

Featured Presentation

ESD Alliance

This webinar will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification.

9:00 am - 10:00 am Off Add to Calendar 2026-09-10 09:00:00 2026-09-10 10:00:00 ESD Alliance Webinar: Gen-AI for Chip Design and Security This webinar will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification. United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register Now
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SEMI Japan
26F, xLINK Marunouchi Eiraku Bldg.
1-4-1 Marunouchi, Chiyoda-ku
Chiyoda-ku, Tokyo
1000005
Japan

Standards

Automation Technology Japan TC Chapter Meeting 

Date: Friday, June 19, 2025

Time: 1:30 PM - 3:00 PM (JST)

via Official Virtual TC Chapter Meeting + SEMI Japan (Hybrid)

Please note that the meeting venue might be changed due to room capacity.  If there is any change, we will inform you once it is confirmed.

 

AGENDA

 

Standards Contact Information:

Nahoko Koga

Coordinator, Standards & EHS, SEMI Japan

Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

 

Questions? Contact your local staff coordinator: Click here

1:30 pm - 3:00 pm Off Add to Calendar 2026-06-19 13:30:00 2026-06-19 15:00:00 Automation Technology Japan TC Chapter Meeting Automation Technology Japan TC Chapter Meeting Date: Friday, June 19, 2025Time: 1:30 PM - 3:00 PM (JST)via Official Virtual TC Chapter Meeting + SEMI Japan (Hybrid)Please note that the meeting venue might be changed due to room capacity.  If there is any change, we will inform you once it is confirmed. AGENDA Standards Contact Information:Nahoko KogaCoordinator, Standards & EHS, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today! Questions? Contact your local staff coordinator: Click here SEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi, Chiyoda-ku Chiyoda-ku, Tokyo 1000005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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SEMI Japan
26F, xLINK Marunouchi Eiraku Bldg.
1-4-1 Marunouchi
Chiyoda-ku, Tokyo
1010005
Japan

Standards

3D Packaging & Integration  Japan TC Chapter Meeting 

Date: Friday, June 5, 2026

Time: 2:00 PM - 4:00 PM JST

via OVTCCM/ SEMI Japan Office (Hybrid)

 

AGENDA

 

Standards Contact Information:

Akiko Yoshida

Manager, SEMI Japan

Email: [email protected]

 

NOTE:

Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.

If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!

Questions? Contact your local staff coordinator: Click here

2:00 pm - 4:00 pm Off Add to Calendar 2026-06-05 14:00:00 2026-06-05 16:00:00 3D Packaging & Integration Japan TC Chapter Meeting 3D Packaging & Integration  Japan TC Chapter Meeting Date: Friday, June 5, 2026Time: 2:00 PM - 4:00 PM JSTvia OVTCCM/ SEMI Japan Office (Hybrid) AGENDA Standards Contact Information:Akiko YoshidaManager, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click here SEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi Chiyoda-ku, Tokyo 1010005 Japan SEMI.org [email protected] Asia/Tokyo public Asia/Tokyo
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United States AI Techniques in Semiconductor MFG Business Executive Technical

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673 S Milpitas Blvd.
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Morning, Day 1: August 5th, 2026

9:00 am - 10:30 am
Surya Kalidindi
Multiscale

Emergent AI/ML Tools for Semiconductor Manufacturing Technology Optimization

Semiconductor manufacturing faces a broad set of complex challenges addressed through Yield Management Systems (YMS), Fault Detection and Classification (FDC), Run-to-Run (R2R) control, Design of Experiments (DOE), and Statistical Process Control (SPC). Existing machine learning approaches are predominantly scoped to individual process steps or short loops, leaving full-traveler analysis — essential for informed tool decisions such as hold, parameter adjustment, and recipe modification — largely unaddressed. Bespoke, step-specific models do not generalize across process nodes or design variants, and manually configuring analytical workflows for each new use case is time-intensive and error-prone as technology nodes diversify. General-purpose coding agents built on large language models (LLMs) partially close this gap by automating workflow generation, but they lack the semiconductor-specific domain knowledge required for robust, production-grade solutions: open-source ML packages carry no fab context, and proprietary data curation and signal-processing conventions are rarely captured in public training corpora.

This session shows how a fab-aware agentic approach closes that gap, focusing on three use cases: YMS, FDC, and Process DOE. It opens with a technical primer built on a common pipeline — preprocessing and feature reduction, uncertainty-aware imputation, regime-aware modeling (physics and virtual-metrology priors when data is scarce, data-driven as it grows), and interpretable attribution rather than black-box scores — instantiated differently across the three, with emphasis throughout on when a result can be trusted. YMS downselects high-dimensional metrology, imputes sparse measurements, and trains a tuned regressor ensemble (GPR, gradient-boosted trees, neural nets), with feature attribution (SHAP) mapped to process step and tool. FDC aligns traces, then layers univariate control limits (SPC) with multivariate anomaly detection (PCA, Hotelling T², MEWMA), per-sensor attribution, and alarm-budgeted limits that transfer across chambers. Process DOE designs experiments, fits uncertainty-aware surrogates (Gaussian processes), reduces dimensionality (PCA), and selects runs sequentially (single- and multi-objective Bayesian optimization). Attendees then see these techniques operationalized live by a domain-specific agentic platform and work directly with the agents on curated datasets.

By the end, attendees will understand how problem formulation, data characteristics, and method selection shape outcomes, and what distinguishes a domain-aware agentic workflow from a general-purpose coding agent. The session is interactive by design — participant choices steer the live analysis, and attendee input shapes how these capabilities evolve.

10:30 am - 11:00 am
Maryia Kurdina
AI R&D Group Leader
TEL and AI Design (TTAD)

Real-Time Equipment Health Monitoring Using Gaussian Process Regression on Sensor Signals

Will present a real-time health monitoring method for semiconductor equipment using multi-sensor time-series signals. From a small set of baseline runs (typically 5–20), Gaussian Process Regression is used to learn expected sensor behavior and associated confidence bands over repeatable operating segments. At runtime, deviations from these bands are aggregated into health scores per sensor and segment to identify abnormal behavior early. The system automatically reports anomalies and raises warnings to support proactive maintenance and reduce unplanned downtime and quality risk. To address the O(N^3) training cost of standard GPR, we use a split-training approach that achieves linear scaling, keeping computation practical for production use.​

11:00 am - 11:20 am

Break

11:20 am - 12:20 pm
Viraj Modak, Aditi Gautam, Saira Qureshi
Nvidia

Predict Before Failure: A Predictive Maintenance Blueprint with NV-Tesseract and NeMoClaw

Semiconductor fabs generate high-volume, multivariate sensor telemetry from process tools, ambient monitoring systems, sub-fab equipment, etc. Scheduling maintenance operations depends on more than just reacting to alarms/alerts: teams need to forecast how equipment will behave and detect abnormal trajectories/baseline shifts before failures occur.​

This session introduces an open Predictive Maintenance Blueprint that embeds NV-Tesseract as the core time series AI component. The pipeline performs multivariate forecasting on equipment sensor data, then runs diffusion-based anomaly detection on the forecasted window to flag emerging degradation patterns. ​

The blueprint is packaged as a reusable, deployable workflow with Hugging Face weight retrieval, configurable sensor channels, and structured outputs for downstream automation.​

We extend this blueprint with NVIDIA NeMoClaw, treating predictive maintenance as an always-on agent workflow: an autonomous agent ingests sensor streams, invokes the NV-Tesseract pipeline, interprets anomaly scores, and produces operator-ready summaries and recommended actions under OpenShell runtime guardrails. ​

Together, this shows how foundational time series models and agent orchestration can be coupled to build a production-style Predictive Maintenance stack for semiconductor operations.​

What the Audience Will Learn​:
Predictive maintenance is shifting from threshold-based SCADA alarms to forecast-then-detect workflows that catch drift earlier on multivariate equipment signatures.​

Foundational time series models (like NV-Tesseract) are increasingly deployed as components inside larger agent systems, not as standalone notebooks.​

Semiconductor and industrial teams are adopting blueprint + agent patterns (similar to NeMoClaw deployments in EDA, simulation, and factory ops) to move from prototype to governed, repeatable workflows.​

Practical lessons: multivariate sensor alignment matters; model weights and configs should be versioned and auto-retrieved; anomaly outputs must be explainable enough for maintenance engineers to trust and act on.​

Architecture takeaways:​
When to use multivariate forecasting vs. single-signal monitoring.​

Why diffusion-based anomaly detection fits correlated, high-dimensional fab sensor data better than univariate reconstruction approaches.​

How NeMoClaw can orchestrate the pipeline: data ingest → inference → thresholding → alert routing → human-in-the-loop review.

12:20 pm - 1:30 pm

Lunch

1:30 pm - 2:00 pm
Sean Tropsa & Kyle Clark
SEEQ

Practical Agentic AI at Scale for Manufacturing: Lessons Learned from Large-Scale Deployments​

Agentic AI is nearing mainstream adoption, yet many organizations still lack a clear strategy for deployments at scale. In order to bring LLM capabilities to manufacturing, companies need to go beyond what mainstream AI suppliers can deliver; they need AI deployments to be governed, reliable, repeatable, and scalable enough to earn trust and deliver measurable results. Most importantly, it must be grounded in and continuously integrate the knowledge of subject matter experts who understand the complexity of real systems and processes.​


In this session, we will share lessons learned from deploying large-scale agentic AI solutions in the semiconductor industry. We will explore how SME expertise and operational context can be embedded into Agentic AI systems to create trusted, high-value results. Specifically, we will show how an auto-Triage/RCA a Facilities Anomaly event workflow can be set up such that, as the event triggers, an AI agents completes a first pass investigation that is ready for consumption by the end user shortly after an event triggers with an optional integration with CMMS systems to ease the creation of a work order to drive faster time to resolution and greater consistency in event disposition. We will also demonstrate how engineers can build custom apps and AI agents on demand, without requiring an AI specialist or extensive coding skills, while maintaining the structure and scalability needed for enterprise adoption. Attendees will leave with practical insights for enabling better, faster decisions across engineering, technician, and operator workflows.

Afternoon, Day 1: August 5th, 2026

2:00 pm - 3:00 pm
Steven Sheets
Lam Research

Human-Machine Collaboration for Improving Semiconductor Process Development

One of the bottlenecks to building semiconductor chips is the increasing cost required to develop chemical plasma processes that form the transistors and memory storage cells1,2. These processes are still developed manually using highly trained engineers searching for a combination of tool parameters that produces an acceptable result on the silicon wafer3. The challenge for computer algorithms is the availability of limited experimental data owing to the high cost of acquisition, making it difficult to form a predictive model with accuracy to the atomic scale. Here we study Bayesian optimization algorithms to investigate how artificial intelligence (AI) might decrease the cost of developing complex semiconductor chip processes. In particular, we create a controlled virtual process game to systematically benchmark the performance of humans and computers for the design of a semiconductor fabrication process. We find that human engineers excel in the early stages of development, whereas the algorithms are far more cost-efficient near the tight tolerances of the target. Furthermore, we show that a strategy using both human designers with high expertise and algorithms in a human first–computer last strategy can reduce the cost-to-target by half compared with only human designers. Finally, we highlight cultural challenges in partnering humans with computers that need to be addressed when introducing artificial intelligence in developing semiconductor processes.​

What the Audience will Learn:
How Bayesian optimization can help enhance speed-to-solution for semiconductor manufacturing.

3:00 pm - 3:20 pm

Break

3:20 pm - 5:20 pm
Sainyam Galhotra
Third AI Automation

From Prediction to Action: Causal AI for Real-Time Root-Cause Analysis in Semiconductor Manufacturing

Semiconductor fabs generate massive volumes of data across tools, sensors, inspection systems, and process logs—yet most AI deployments remain predictive, identifying anomalies without explaining their root cause. This results in prolonged root cause analysis (RCA), costly downtime, and repeated trial-and-error fixes.​

In this talk, we present a practical approach to moving from prediction to action using causal AI. By unifying multi-modal data like images, time-series signals, and process metadata into a single intelligence layer, we enable systems that reason about cause-and-effect relationships rather than correlations.​

We will discuss how such systems can be trained efficiently using weak supervision and deployed at the edge to meet latency, privacy, and reliability requirements. We also highlight how continuous monitoring and model refinement in production ensure sustained performance in dynamic manufacturing environments.​

Drawing from real-world deployments, we show how this approach reduces RCA time from hours to minutes, improves diagnostic accuracy, and enables prescriptive actions for faster yield recovery and improved operational efficiency.​

What the Audience will Learn:​
1. Why predictive AI falls short for RCA and how causal AI bridges the gap​
2. How to build an “intelligence layer” on top of MES and traceability systems​
3. Practical methods for leveraging limited labeled data ​
4. How to integrate multi-modal data (inspection images + sensor logs + process flows)​
5. How to build AI agents that improve with more data​

How this AI technique is being used in industry today (real deployments, lessons learned, impact): In semiconductor manufacturing environments, causal AI systems are being deployed alongside existing inspection and MES infrastructure to accelerate and improve root cause analysis.​

In one deployment, defect patterns observed across multiple inspection stages were correlated with tool-level and process metadata. Instead of manual investigation across dozens of steps, the system identified a specific tool-stage interaction responsible for recurring defects. This reduced RCA time from 20–40 hours to under 10 minutes while improving diagnostic consistency.​

Demo: Yes​

Hands-on Session:
Yes,​ Applying weak supervision to label defect data with minimal manual effort​
Interpreting causal relationships across process steps​
Monitoring and updating models in a production-like setting​

5:20 pm - 7:20 pm

Reception

Morning, Day 2: August 6th, 2026

9:00 am - 10:00 am
Akhilesh Kumar​ ​
Synopsys/ANSYS

Get More from Your Sign-off Flow: Agentic AI That Makes Power & Signal Integrity Engineers Radically More Productive

Agentic AI is moving from research demos to production EDA flows, and the leverage is very clear in power and signal integrity sign-off, where engineers routinely write 1000+-API Python scripts, search for root causes through ~100 GB log files, and stitch results across half a dozen vendor tools. This talk presents our experiences with building, shipping, and supporting a multi-agent system for a production sign-off tool used on modern VLSI and 3DIC designs — covering what it took to move from a single LLM "wrapper" to a hardened agentic system that customers can actually trust with their IP.​

We will walk through the full stack: a multi-agent architecture (code-generation, log-debug, RCA/diagnostics) built on a Deep-Agent framework; an Agent Skills pattern that makes diagnostic workflows modular, composable, and customer-extensible; MCP used in both directions (the Copilot consumes vector-DB and API knowledge as MCP, and the tool itself is exposed as an MCP server so other EDA agents and customer orchestrators can drive it); and a governance layer covering tiered action approval, API-hallucination guards, prompt sanitization, audit trails, and on-premise / air-gapped local-LLM deployment. We will close on the next frontier: cross-vendor agent-to-agent flows, for example, place-and-route → parasitic extraction → power integrity → timing — orchestrated through MCP, with humans setting policy at well-defined checkpoints rather than copy-pasting between tools.​

The session is built for practitioners. A curated set of short demo videos recorded from real Agentic AI sessions on representative designs showing the agent generate scripts and run a multi-step RCA end-to-end, with explanations on what is happening under the hood at each step.​

What the Audience Will Learn​:
1. Reference architecture for a production EDA Copilot: Multi-agent decomposition (code-gen, log-debug, RCA), RAG over manuals/API catalogs, and tool execution inside the host EDA product.​
2. The Agent Skills pattern for RCA / diagnostics: Composable Agent Skills (IR-drop RCA, anomaly detection, comparative run analysis) the orchestrator plans over and that customers can extend without touching the core.​
3. MCP as a two-way integration framework: Consuming knowledge and tool capabilities as MCP and exposing the EDA tool itself as an MCP server so customer or partner agents can drive it.​
4. Governance and guardrails for production: Tiered action approval, API-validation against the catalog to block hallucinations, prompt sanitization for IP, audit trails, and runaway controls.​
5. A practical LLM strategy: Cloud frontier models, qualified open-weight local LLMs for air-gapped customers, and distillation + RL fine-tuning strategies with LLM-as-judge and production feedback.​
6. The feedback flywheel: What to instrument to drive weekly prompt fixes, monthly workflow updates, and quarterly model improvements.​
7. Cross-vendor agentic flows: Sequential chaining, parallel fan-out, and iterative loops across EDA tools over MCP.​

How This AI Technique Is Being Used in Industry Today​

The Copilot is a shipped, per-user binary that launches alongside a production sign-off tool, attaches to the user's interactive session, and runs entirely on customer infrastructure (cloud LLM or fully on-premise).​

Demo Session: Curated Videos (20 min)​

Rather than a live hands-on segment, the demo is a curated set of short, pre-recorded clips captured from real Copilot sessions on representative designs. This keeps the demonstration crisp and reproducible, and the speaker narrates each clip — calling out which agent, skill, or MCP call is firing and why.​

10:00 am - 10:20 am

Break

10:20 am - 11:20 am
Abhinav Kumar
Applied Materials

From Data Silos to Autonomous Discovery: Agentic AI in Semiconductors

Semiconductor manufacturing is increasingly challenged not by the availability of data, but by the difficulty of integrating and reasoning across fragmented, heterogeneous information sources spanning process data, metrology, and engineering knowledge. This session introduces a practical, system-level perspective on building agentic AI capabilities for semiconductor applications, beginning with foundational considerations in data definition, representation, and consistency across structured and unstructured domains.​

The discussion focuses on how these foundations enable a transition from isolated analytics toward more integrated, decision-oriented systems. Architectural patterns are explored for combining data-driven models, simulation, and domain knowledge into cohesive workflows, with emphasis on reliable orchestration, traceability of reasoning, and appropriate human oversight—elements that are critical for deploying AI in high-stakes manufacturing environments.​

The session concludes with an overview of how emerging approaches are extending these ideas toward more adaptive and semi-autonomous optimization systems. Attendees will gain a structured view of the end-to-end stack—from data preparation to decision support—and practical insights into considerations for adopting agentic AI methodologies in semiconductor manufacturing settings.

11:20 am - 11:50 am
Justin Hayes
VP of Field Engineering and Semiconductor SME
Vectara​

Building a Trustworthy Semiconductor Knowledge Base for Agentic Insight Generation

Semiconductor organizations face doubling advanced-node design costs, compressing design cycles, and scarce engineering talent while their most valuable asset, engineering knowledge, sits fragmented across schematics, waveforms, 8D reports, JIRA tickets, fab SOPs, and decades of tribal expertise. Generic search and AI tools routinely fail on this dense, technical content. ​

Drawing on real-world deployments at Broadcom, SanDisk, Altera, and Texas Instruments, Vectara will explore the solution architecture and real-world deployment of their domain-specialized Knowledge Hub and Agentic AI Platform designed specifically for the semiconductor lifecycle. ​

We'll walk through the multi-stage ingestion pipeline that preserves formulas, nested tables, and schematics natively; Vectara unified retrieval fabric that replaces fragmented, separately licensed point tools; and the agent layer that runs multi-hop, semantically deep queries across technical logs and historical failures - letting engineers surface root-cause indicators in plain language, no SQL required. ​

Crucially, the session will focus on what production-grade accuracy demands: grounded, citation-backed answers over complex IP for generating net-new insights, and streamline cross-team knowledge reuse that engineering teams, and agents can trust.

11:50 am - 1:00 pm

Lunch

Afternoon, Day 2: August 6th, 2026

1:00 pm - 2:30 pm
Garima Sharma
Mathworks

Making Sense of Equipment Time‑Series Data: From Signals to Insight

Modern semiconductor equipment generates vast amounts of time-series and inspection data, but much of it remains under-utilized. This session presents a practical, end-to-end workflow—from data preparation and AI modeling (including anomaly, defect, and drift detection) to validation and deployment—using familiar manufacturing data. It also highlights how synthetic data and generative AI can accelerate model development while maintaining robust validation and engineering control.​​

What the Audience will Learn:​
Attendees will learn how to turn equipment data into actionable insights using an end-to-end AI workflow—from data preparation to deployment. They will also see how multiple AI approaches, synthetic data, and generative AI can accelerate development while maintaining rigorous engineering validation.​

Demo / Hands-on Session: Yes

2:30 pm - 2:45 pm

Break

2:45 pm - 4:15 pm
Jon Herlocker
Cohu

Achieving Business Results from Air-gapped Agentic AI Automation in Semiconductor Manufacturing - Lessons from the Field

Agentic AI has crossed a capability line where it can now effectively automate non-trivial portions of work that previously was only done by factory engineers - process engineers, yield engineers, test engineers, maintenance engineers. At Cohu, we have been working closely every week with our customers to roll out agentic capabilities that are leading to significant automation, yield, and capacity improvements. Along the way, we have needed to overcome significant constraints - such as prohibitions on providing sensitive process data to cloud AI providers - and had to manage the more complicated issue of integrating agentic AI into legacy systems and processes. In this talk I can share some of ways that our customers are benefiting from agentic AI and talk about some of the learnings gained through these various deployments. ​

What the Audience will Learn:​
Key learnings for the audience a) real use cases of agentic AI in global semiconductor manufacturing companies; b) practical recommendations for how to prepare for and be successful with the deployment of agentic AI in semiconductor manufacturing. ​

Demo:​
FDC model creation, and fault analytics​
Yield analytics​
Tester Operations Management​
Test Engineering - lot disposition analytics ​
Maintenance optimization and predictive maintenance​
Line support optimization

- Smart MFG

 

The SEMI Smart Manufacturing Initiative is hosting a two-day workshop titled "AI Techniques in Semiconductor Manufacturing" at SEMI HQ in Milpitas, CA, on August 5–6, 2026. This event is part of a continuing series focused on integrating advanced AI into the semiconductor landscape. The workshop is designed to help participants understand: The real-world deployment, impact, and lessons learned from AI techniques. Strategies for building observable and scalable multi-agent workflows. The industry transition from restrictive data silos toward autonomous discovery. Methods for achieving tangible business results and automation through diverse AI applications.

8:00 am - 5:00 pm Off Add to Calendar 2026-08-05 08:00:00 2026-08-06 17:00:00 AI Techniques in Semiconductor Manufacturing  The SEMI Smart Manufacturing Initiative is hosting a two-day workshop titled "AI Techniques in Semiconductor Manufacturing" at SEMI HQ in Milpitas, CA, on August 5–6, 2026. This event is part of a continuing series focused on integrating advanced AI into the semiconductor landscape. The workshop is designed to help participants understand: The real-world deployment, impact, and lessons learned from AI techniques. Strategies for building observable and scalable multi-agent workflows. The industry transition from restrictive data silos toward autonomous discovery. Methods for achieving tangible business results and automation through diverse AI applications. SEMI HQ 673 S Milpitas Blvd. Milpitas, CA 95035 United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Register Now
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