Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.
If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!
Questions? Contact your local staff coordinator: Click here
10:00 am - 1:00 pm
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Add to Calendar2025-12-03 10:00:002025-12-03 13:00:00EHS Japan TC Chapter MeetingEHS Japan TC Chapter Meeting Date: Wednesday, December 3, 2025Time: 10:00 AM - 1:00 PM JSTvia Official Virtual TC Chapter Meeting + SEMI Japan (Hybrid)Please note that the meeting venue might be changed due to room capacity. If there is any change, we will inform you once it is confirmed. AGENDA Standards Contact Information:Akiko YoshidaSenior Coordinator, Standards & EHS, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click hereSEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi Chiyoda-ku, Tokyo 1010005 JapanSEMI.org[email protected]Asia/Tokyopublic
Asia/Tokyo
Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.
If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!
Questions? Contact your local staff coordinator: Click here
2:00 pm - 4:00 pm
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Add to Calendar2025-10-06 14:00:002025-10-06 16:00:003D Packaging & Integration Japan TC Chapter Meeting3D Packaging & Integration Japan TC Chapter Meeting Date: Monday, October 6, 2025Time: 2:00 PM - 4:00 PM JSTvia OVTCCM/ SEMI Japan Office (Hybrid) AGENDA Standards Contact Information:Akiko YoshidaSenior Cooordinator, SEMI JapanEmail: [email protected] NOTE:Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today!Questions? Contact your local staff coordinator: Click hereSEMI Japan 26F, xLINK Marunouchi Eiraku Bldg. 1-4-1 Marunouchi Chiyoda-ku, Tokyo 1010005 JapanSEMI.org[email protected]Asia/Tokyopublic
Asia/Tokyo
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Standards
8:00 am - 6:00 pm
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Add to Calendar2025-10-06 08:00:002025-10-09 18:00:00SEMICON West Standards Meetings 2025Phoenix, AZ United StatesSEMI.org[email protected]America/Phoenixpublic
America/Phoenix
Are We There Yet? Metrology and Inspection for Angstrom-Level Manufacturing
In the semiconductor industry where we routinely pattern sub-wavelength structures and require atomic-layer precision in our manufacturing processes, it’s easy to assume that we can simply measure everything we’re doing and all the structures we create. In reality, though, metrology and inspection have the challenging task of not just keeping up with device technology but staying far enough ahead that we can actually “see” our results and confirm the progress we’re making.
In this webinar, co-hosted with the Electronics business of Merck KGaA, Darmstadt, Germany; we will explore the metrology and inspection space to learn more about technological advances driving this vital segment of semiconductor manufacturing.
The webinar will feature presentations by Eric Beyne, PhD, Senior Fellow, VP R&D and Director of 3D System Integration Program for imec, and Dario Alliata, PhD, Senior Application Director for Metrology & Inspection at the Electronics business of Merck KGaA, Darmstadt, Germany.
Following the presentations, an interactive Q&A segment will allow attendees a chance to deepen their understanding of how materials innovation and advanced metrology intersect at the leading edge of manufacturing.
Join us to engage with peers and pioneers working at the forefront of materials science and semiconductor innovation!
United States
Dario Alliata, PhD
Senior Director of Applications
The Electronics business of Merck KGaA, Darmstadt, Germany
The Role & the Challenge of Metrology and Inspection in Advanced Packaging of AI Chips
The massive adoption of social networking and artificial intelligence has pushed the semiconductor industry to develop devices capable of supporting the required infrastructures. Increasingly powerful computer process units (CPU) are used to allow data centers to process trillions of information exchanges, while faster graphic process units (GPU) enable virtual and assisted reality.
Cost leveraging is now reachable with the integration of multiple dies in the same package, each one fabricated to handle specific functionalities with the most cost-effective technology node, which is a form of heterogeneous integration. This session highlights some examples of metrology and inspection solutions aimed at securing the manufacturability of devices for High Computing Power fundamental for AI applications. More in detail, it explores the challenge of the fabrication of chip-to-chip interconnections that are key for the heterogeneous integration of active components with vertical stacking like DRAM for High Bandwidth memories, where process tolerances are increasingly narrow and conditions to measure more and more extremes.
Biography
Dr. Dario Alliata joined Unity-SC, now part of the Electronics business of Merck KGaA, Darmstadt, Germany in the U.S. and Canada. In 2016 as product manager and is now Sr. Director of Applications with focus on Advanced packaging and Specialty substrates & devices.
He worked in the semiconductor industry for more than 25 years, initially in R&D centers and later in equipment makers. He spent his entire career developing process control solutions for securing the manufacturing chain in the semiconductor industry.
He received a MD in Physics from the University of Milan (Italy) and hold a Ph.D. in Physics & Chemistry from the University of Berne (Switzerland).
Eric Beyne, PhD
VP R&D / Program Director 3D System Integration Program / Senior Fellow
imec
Sub-Micron Pitch Scaling of Hybrid Bond Interconnects: Metrology Challenges
Advanced 3D integration technology will increasingly rely on hybrid bonding technology for both wafer-to-wafer and die-to-wafer bonding. This allows for micrometer and sub-micrometer pitch interconnects, resulting in very high 3D interconnect densities, compatible with the back-end-of -line interconnect layers of active logic and memory die. The results are “seamlessly” interconnected die. Off-chip interconnects become equivalent (or better) than on-chip interconnects.
These great system-level benefits however come at some challenges. Small overlay errors or surface imperfections can prevent defects, resulting in yield loss. Critical process, steps, such as CMP, wafer dicing and surface cleaning steps, need to be monitored with higher accuracy to maintain a good process. New parameters, such as wafer shape, distortion, surface profile slopes, and copper pad recess levels need to be measured and continuously monitored. This poses significant challenges to metrology related to hybrid bonding. The presentation will highlight these needs and show some practical solutions.
Biography
Eric Beyne obtained a degree in electrical engineering in 1983 and the Ph.D. in Applied Sciences in 1990, both from the Katholieke Universiteit Leuven, Belgium. Since 1986 he has been with IMEC in Leuven, Belgium where he has worked on advanced packaging and interconnect technologies. Currently, he is imec senior fellow, VP R&D and program director of imec’s 3D System Integration program.
Michael Weigand
Senior Application Manager
Brewer Science
Moderator
Biography
I'm a seasoned Senior Application Manager at Brewer Science with over two decades of experience in Semiconductor industry. I lead application teams at Brewer Science Inc, focusing on advanced materials for the semiconductor industry. With a background in Material Science, I enjoy tackling technical challenges, from optimizing critical processes to finding creative ways to characterize materials.
Sponsored by the Electronics business of Merck KGaA, Darmstadt, Germany
Are We There Yet? Metrology and Inspection for Angstrom-Level Manufacturing
10:00 am - 11:00 am
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Add to Calendar2025-09-17 10:00:002025-09-17 11:00:00Are We There Yet? Metrology and Inspection for Angstrom-Level Manufacturing Sponsored by the Electronics business of Merck KGaA, Darmstadt, Germany United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
WATCH NOW
As world leaders act to secure access to these minerals, companies come under pressure to follow due diligence guidelines to promote ethical sourcing of these materials for their supply chains. Regulations such as the US Dodd-Frank Wall Street Reform and Consumer Protection Act (Section 1502), EU Regulation 2017/821 and the EU Corporate Sustainability Due Diligence Directive require companies to trace materials through their supply chains and report to the public about their use of conflict minerals.
Several industry associations, including the Responsible Business Alliance’s Responsible Minerals Initiative, were created to help companies with their due diligence efforts. Reports such as those issued by the US Government Accountability Office on Conflict Minerals offer insights into the efficacy of these regulations and suggest improved approaches for industry engagement.
The SEMI Responsible Supply Chain (RSC) working group was recently formed to host discussions on these topics. This webinar will provide insights from speakers Jennifer Peyser, Responsible Business Alliance Senior Vice President of Responsible Sourcing, and Kimberly Gianopoulos, Managing Director for the International Affairs and Trade team at the U.S. Government Accountability Office (GAO).
United States
8:00 am
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8:05 am
Dr. Kimberly Harrison, Ph.D
Senior MEMS Engineer
AMFitzgerald & Associates
Welcome and Introductions of RSC working group
Dr. Harrison is a MEMS Engineer with AMFitzgerald & Associates, a design firm located in the Bay Area California. She has a doctoral degree in mechanical engineering from Stanford University, and has worked as a designer and process engineer in the semiconductor industry for 10 years. She was nominated as a 2022 MEMS & Sensors Industry Group Emerging Leader. As a founding member and leader of the SEMI Responsible Supply Chain Working Group, she hopes to bring SEMI members together to discuss solutions to human rights issues in the semiconductor supply chain.
Conflict Minerals Supply Chain Overview
8:05 am
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8:35 am
Kimberly Gianopoulos
Managing Director for the International Affairs and Trade
U.S. Government Accountability Office (GAO)
Report Review
Director Gianopoulos oversees a 140-person team that reviews a wide variety of federal government oversight issues, including International Security Assistance, Bilateral and Multilateral Foreign Assistance, International Trade and Finance, and U.S. Diplomatic Presence and Management. She serves as a facilitator in GAO’s Learning Center and participates in recruiting activities. Ms. Gianopoulos has received several awards, including a Distinguished Service Award, a Meritorious Service Award, a Client Service Award, and several Results Through Teamwork awards. Ms. Gianopoulos earned a Bachelor’s degree in Mathematics and a Master’s degree in Public Analysis and Administration from the State University of New York at Binghamton. She is a Certified Government Financial Manager and a member of Pi Alpha Alpha, the Global Honor Society for Public Affairs and Administration.
Jennifer Peyser
Executive Director
Responsible Minerals Initiative
RMI Activity Overview
“The RMI supports over 500 downstream, midstream, and upstream member companies with a suite of due diligence standards and tools, data, guidance, training, and other resources for global responsible sourcing and regulatory compliance. Our facility and supply chain due diligence standards are rooted in longstanding international norms while reflecting emerging corporate and stakeholder priorities for regulatory compliance, managing sustainability risks and impacts, and fostering responsible mineral supply chains.”
Critical Minerals, Due Diligence and the Semiconductor Supply Chain
8:00 am - 9:00 am
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Add to Calendar2025-07-09 08:00:002025-07-09 09:00:00Critical Minerals, Due Diligence and the Semiconductor Supply ChainUnited StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
Register for On-demand
Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend.
If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, completeanapplication form today!
Questions? Contact your local staff coordinator: Click here
10:00 am - 12:00 pm
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Add to Calendar2025-07-11 10:00:002025-07-11 12:00:00EHS Korea TC Chapter MeetingEHS Korea TC Chapter Summer Meetings 2025 Date: Friday, July 11, 2025 Time: 10:00-12:00 (KST) via Hybrid AGENDA (subject to change) Last updated: June 9, 2025 NOTE: Standards meetings are open to all, but you must be a SEMI Standards Program Member to attend. If you are not a Member, please register for the International SEMI Standards Program and start making a big contribution to the industry’s progress, complete an application form today! Questions? Contact your local staff coordinator: Click here Seoul South KoreaSEMI.org[email protected]Asia/Seoulpublic
Asia/Seoul
Early-Bird Registration Deadline: Wed, July 9, 5PM (KST)
Group Registration Deadline: Fri, July 4, 5PM (KST)
Registration fee includes a boxed lunch provided at the venue.
[Group]
SEMI Member : KRW 275,000
Non Member: KRW 330,000 * Group registration fee applies to groups of five or more from the same company. * For group registration inquiries, please contact SEMI Korea Program Team([email protected]).
Convention Hall 2, 3F, Suwon Convention Center South Korea
9:00 am
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9:30 am
Choon Lee
Intel
System Level Advanced Packaging
Rapidly evolving progress of AI and HPC has significantly increased computational and memory needs such as higher performance, lower power consumption, and wider memory bandwidth with reduced latency. An end application of AI/HPC comes down to Datacenter construction. Meeting the challenge of delivering this processing power in the datacenter requires systematic innovation from the device to the datacenter level. It starts with integrating highly optimized, domain-specific accelerators which should be integrated into advanced 2.5D and 3.5D packaging that minimize losses and power for high-speed communication while taking advantage of workload power management. AI computing introduces significant challenges for energy consumption and thermal management. Power delivery network is crucial for CPU, GPU and NPU power and performance of which solution can be DTC, IVR, mtal-insulator-metal (MIM) capacitor and thin film inductor, backside power rail, etc.. While Moore’s law has continued to yield transistor scaling necessary for these applications, the ever growing demand from models for AI training and inference pushes Si scaling in conjunction with the advent of advanced interconnects via disaggregation and reaggregation of chips in advanced packaging.
We will discuss with examples and the challenges of utilizing packaging elements to their full potential and discuss how co-optimization is crucial to achieving the best results for any given set of system requirements and constraints.
Advanced Packaging and Reliability: Technologies Shaping the Next Generation
Advanced semiconductor packaging is now central to enabling continued performance scaling as conventional transistor scaling slows. This seminar introduces cutting-edge trends in advanced packaging, including 2.5D and 3D integration, fan-out wafer-level packaging, chiplet-based architectures, and glass interposers for optical I/O in AI and HPC systems. These technologies offer enhanced performance, form factor reduction, and system-level integration capabilities critical for future computing platforms.
Leveraging prior industry experience, this talk highlights real-world applications and challenges in designing and qualifying advanced SoC packages. Examples include CoWoS-based AI chip packaging, hybrid bonding techniques, and thermal design optimization for high-power systems.
As packaging structures become increasingly complex, reliability emerges as a critical bottleneck. The seminar explores major failure mechanisms such as thermal-mechanical fatigue, electromigration, interfacial delamination, and Through Glass Via (TGV) degradation. Reliability analysis methods including FEA-based stress modeling, time-to-failure prediction, and advanced failure diagnostics will be introduced.
By combining packaging innovation with reliability engineering, the talk aims to provide a comprehensive perspective on the technological and practical issues that must be addressed to enable robust, high-performance semiconductor systems in the AI and data-driven era.
Pushing the Boundaries: Challenges and Opportunities in Panel-Level Packaging Technology
As the AI era progresses, semiconductor devices are increasingly adopting 3D architectures to boost performance and power efficiency. At the same time, system technology co-optimization (STCO) is advancing through the use of chiplets and advanced wafer-level packaging. As the industry integrates more chips into chiplets, the size of interposers continues to grow. However, wafer-level packaging faces limitations in accommodating large interposers due to the constraints of 300mm wafer shapes and temporary carriers.
This trend is driving a shift toward panel-level packaging (PLP) to support higher packaging unit counts. Despite its potential, PLP still faces significant challenges—particularly in terms of process development and process control.
This paper explores the technical trends in panel-level packaging, focusing on the current challenges and potential solutions related to process control.
Presentation New Innovations Enabling Fine Pitch D2W Hybrid Bonding
Heterogenous integration and advanced packaging is behind the technology that is enabling today’s AI and high-performance computing. This is done through complex architecture that utilizes platforms including microbumps, through silicon vias (TSV), high density fanout and hybrid bonding (HB). The integration of chiplets using any combination of these technologies is allowing the industry to extend the Moore’s law and overcome limitations of the Von Neumann architecture. Hybrid bonding is an especially appealing technology that helps improve power and performance (higher I/O density), as well as thermal management. Sub-10 ㎛pitch die-to-wafer (D2W) HB is already in production1) for 3DIC and the industry working on HB technology for High Bandwidth Memory as well2). However, there are continuous challenges for D2W that require new innovation in both processing and metrology & inspection (M&I), and also unique challenges for both logic and memory applications specific to its integration. The presentation will discuss how logic and memory HB technologies are different and what process and M&I technologies are needed to facilitate HVM of the HB technology across different applications. Process challenges including low temperature bonding, die warpage management and dicing will be discussed, while M&I challenges include the transition to e-beam technology for HB enablement.
1) R. Agarwal et al., “3D Packaging for Heterogeneous Integration”, IEEE ECTC, July 2022
2) Lee et al., “A Study on D2W Cu Bonding Technology for HBM Multi-die Stacking”, IEEE ECTC, May 2024
Design and Development of High Thermal Conductive Molding Compounds for Advanced Packaging Applications
The ongoing miniaturization and increased integration density in electronic circuit systems, particularly in advanced technologies such as DRAMs for Through-Silicon Via (TSV) and High Bandwidth Memory (HBM), have elevated thermal management to a critical challenge in microelectronic packaging. The functional performance, operational lifespan, and reliability of electronic devices fundamentally depend on efficient thermal dissipation. As power densities escalate, enhancing the thermal conductivity of EMCs has become imperative for effective heat removal from increasingly complex electronic components. Consequently, research efforts focused on developing epoxy resins with superior thermal conductivity and identifying appropriate high-conductivity fillers represent the most viable approaches to addressing thermal management challenges in contemporary microelectronic systems.
Recently, we have successfully developed a high-performance epoxy molding compound (EMC) that solves critical thermal management challenges in advanced microelectronic packaging applications. Not only do these compounds provide extremely safe protection of integrated circuits from moisture, mobile ion contaminants and adverse environmental conditions, including temperature fluctuations, humidity and mechanical stress, but the enhanced thermal and mechanical properties of EMC formulations address the heat dissipation requirements of advanced technologies such as small electronic circuit systems, especially TSV and HBM applications.
3:00 pm
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3:30 pm
Prof. Yunhyeok Im
Georgia Institute of Technology
Next-Generation Thermal Strategies: The Liquid Cooling Revolution for AI Chips
Next-generation semiconductor packaging technologies are advancing rapidly in response to the explosive growth of high-performance semiconductor markets, including AI chips and HBM. At the Advanced Packaging Summit 2025, industry leaders from top global companies will share the latest developments and insights in advanced packaging technologies. The morning session will spotlight core technologies such as SLP and PLP, while the afternoon session will feature in-depth presentations on essential next-generation packaging technologies including hybrid bonding, glass substrates, materials for heat control, and liquid cooling solutions. Each session will also include panel discussions to encourage broad and practical exchanges of technical experiences, offering valuable opportunities for networking. We invite you to explore the future direction of next-generation semiconductor packaging with global industry experts and expand both your insights and business horizons at this premier event.
ADVANCED PACKAGING SUMMIT 2025
9:00 am - 5:30 pm
Off
Add to Calendar2025-07-16 09:00:002025-07-16 17:30:00Advanced Packaging Summit 2025Next-generation semiconductor packaging technologies are advancing rapidly in response to the explosive growth of high-performance semiconductor markets, including AI chips and HBM. At the Advanced Packaging Summit 2025, industry leaders from top global companies will share the latest developments and insights in advanced packaging technologies. The morning session will spotlight core technologies such as SLP and PLP, while the afternoon session will feature in-depth presentations on essential next-generation packaging technologies including hybrid bonding, glass substrates, materials for heat control, and liquid cooling solutions. Each session will also include panel discussions to encourage broad and practical exchanges of technical experiences, offering valuable opportunities for networking. We invite you to explore the future direction of next-generation semiconductor packaging with global industry experts and expand both your insights and business horizons at this premier event.Convention Hall 2, 3F, Suwon Convention Center South KoreaSEMI.org[email protected]Asia/Seoulpublic
Asia/Seoul
Graphene, a two-dimensional material with extraordinary electrical, mechanical, and biocompatible properties, is emerging as a key enabler for the next generation of medical devices. In this presentation, we will explore how Graphenea, through its advanced Graphene Foundry services, is driving the integration of graphene into scalable device manufacturing for biomedical applications. Attendees will gain insight into our end-to-end fabrication capabilities, from graphene synthesis, wafer-scale CVD graphene growth to cleanroom device prototyping and packaging. We will showcase examples of graphene-based biosensors, flexible electronics, and neural interfaces developed through our foundry platform, emphasizing their potential impact in diagnostics, monitoring, and therapeutic applications. The session will also address the challenges of material integration, process scalability, and regulatory pathways for graphene in medical technologies, providing a practical roadmap for researchers and companies looking to bring graphene-enabled devices from lab to market.
INBRAIN: Pioneering Precision Neuroelectronics: From Materials to Scalable Therapies
The convergence of materials science, artificial intelligence, and neuromodulation is transforming the future of neuroscience. This talk explores how high-density graphene-based brain-computer interfaces are enabling real-time decoding and precision modulation of neural circuits. Carolina Aguilar, CEO and Co-Founder of INBRAIN Neuroelectronics, will present the technological and clinical journey behind the world’s first graphene neural interface in humans, and how this platform is designed to deliver adaptive, patient-specific therapies for neurological disorders such as Parkinson’s disease. The session will highlight the translational path from research to regulated medical devices, and the role of Europe in leading responsible innovation in neurotechnology
ABOUT THE SPEAKERS:
Jesús de la Fuente
Jesús de la Fuente is the founder and CEO of Graphenea, a leading graphene production company established in 2010. Before founding Graphenea, he served as a Manager at Arthur Andersen, Director at PricewaterhouseCoopers in advisory professional services, and Managing Director at an industrial materials distribution company. He holds a Bachelor of Science in Engineering from Deusto University and an Executive MBA from IESE Business School. Under his leadership, Graphenea has become a world-leading graphene producer, contributing to the development of graphene applications across various sectors in over 60 countries.
Carolina Aguilar
Carolina Aguilar is the CEO and Co-Founder of INBRAIN Neuroelectronics, a neurotechnology company pioneering the use of graphene-based brain-computer interfaces for precision neuromodulation. With over 20 years of experience in healthcare, including 13 years at Medtronic where she led global businesses in brain modulation and diabetes, she has built a career at the intersection of innovation, neuroscience, and impact. Under her leadership, INBRAIN achieved the first-in-human implantation of a graphene neural interface and received FDA Breakthrough Device Designation. Carolina is also a 2025 World Economic Forum Technology Pioneer and a strong advocate for responsible, human-centric deep tech in Europe for the world.
Join us for this exciting Master Class with Jesús de la Fuente, Founder and CEO of Graphenea, and Carolina Aguilar, CEO and Co-Founder of INBRAIN, as they showcase their pioneering efforts of integrating graphene into scalable medical devices highlighting advancements in various medtech applications including biosensors and neural interfaces.
Enabling Next-Generation Medical Devices: Graphene Device Manufacturing
Flexible Electronics Master Class #25
9:00 am - 11:00 am
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Add to Calendar2025-09-10 09:00:002025-09-10 11:00:00FEMC#25 Enabling Next-Generation Medical Devices: Graphene Device ManufacturingJoin us for this exciting Master Class with Jesús de la Fuente, Founder and CEO of Graphenea, and Carolina Aguilar, CEO and Co-Founder of INBRAIN, as they showcase their pioneering efforts of integrating graphene into scalable medical devices highlighting advancements in various medtech applications including biosensors and neural interfaces.United StatesSEMI.org[email protected]America/Los_AngelespublicWatch Now!
Dr. Sidhwa has over 25 years of innovative contributions to semiconductor device manufacturing and processing development. His expertise includes Mergers and Acquisitions, Semiconductor processing and characterization, Nanotechnology, R&D, Capital equipment sourcing, Devices Characterization and Yield Enhancement, Semiconductor Fab constructions, Semiconductor silicon wafer reclaim, Equipment parts cleaning using novel surface cleaning methods, Lean manufacturing, Quality control, Materials characterization, Sustainability, Design of Solar Cells and Composite Armor Manufacturing for the US government. In addition, he is proficient in technology development for strategic alliances and multiple joint ventures. Dr. Sidhwa has 7 U.S. patents issued, two pending applications in multidisciplinary fields, and over 100 publications.
Dr. Sidhwa has led teams to successfully deliver numerous technologies through a complete product development lifecycle, from early R&D to end customer deployment and qualification. He excels at troubleshooting endemic technical manufacturing process integration and reliability issues through systematic and thorough investigation. His hands-on problem-solving skills have repeatedly been demonstrated at startups and established companies by rapidly delivering qualified products to the market.
Innovative Lab to Fab Semiconductor Processes: Advancing sensing, smart manufacturing, and biomedical applications
Emerging MEMS and sensor technologies demand both advanced process capabilities and robust pathways to volume manufacturing. NOEL Technologies, a Silicon Valley MEMS foundry, brings decades of expertise in microfabrication – from state-of-the-art lithography and deep etching to thin-film deposition and multi-layer integration. Its versatile fabrication facility supports wafer diameters ranging from 50 mm up to 300 mm, enabling prototyping on small substrates as well as scale-up to full 300 mm production. NOEL’s engineers excel at integrating novel materials and processes to create structures that often lack a conventional manufacturing path, while handling complex builds with multiple mask layers with both wet and plasma etching of silicon, dielectrics, and metals. Through a proven “Lab-to-Fab” approach, NOEL serves as a vital bridge from R&D to high-volume fabrication, accelerating the transition of innovative designs from the laboratory to the fab floor.
Recent collaboration through Pure Wafer’s acquisition of NOEL Technologies has further expanded these capabilities. Pure Wafer, a leading U.S. provider of high-purity silicon wafer solutions, adds in-house supply of prime silicon substrates (50 mm–300 mm) and an extensive portfolio of exotic dielectric and metal thin films. By coupling NOEL’s proprietary MEMS processes with Pure Wafer’s materials expertise, the combined team delivers a “complete silicon solution” that enhances device performance and yield for next-generation sensors. This synergy is enabling cutting-edge sensor technologies in IoT, biomedical, and industrial applications, supported by faster prototyping cycles and a streamlined path to market. Equally important, the integration provides key business advantages – from cost efficiencies via comprehensive on-shore services (e.g., wafer reclaim and reuse) to improved supply chain resilience through a domestic source for critical materials and fabrication.
This presentation will showcase how the NOEL–Pure Wafer partnership supports next-generation sensor innovation in alignment with the key industry tracks driving future advancements in IoT, Intelligent Sensing, Advanced embedded system Technologies, Multi-Sensor capabilities, Smart Manufacturing, and biomedical applications. By leveraging Pure Wafer and NOEL Technologies' expertise, MEMS and sensor innovators can achieve superior device performance, faster prototyping, and scalable production solutions. This collaboration is paving the way for next-generation innovative sensing solutions that drive technological breakthroughs across industries.
Noel Technologies' Innovative Lab to Fab Semiconductor Processes
Advancing sensing, smart manufacturing, and biomedical applications
June 11, 2025
8-9am PT
8:00 am - 9:00 am
Off
Add to Calendar2025-06-11 08:00:002025-06-11 09:00:00Innovative Lab to Fab Semiconductor Processes: Advancing sensing, smart manufacturing, and biomedical applicationsHosted by SEMI MSIGInnovative Lab to Fab Semiconductor Processes: Advancing sensing, smart manufacturing, and biomedical applicationsEmerging MEMS and sensor technologies demand both advanced process capabilities and robust pathways to volume manufacturing. NOEL Technologies, a Silicon Valley MEMS foundry, brings decades of expertise in microfabrication – from state-of-the-art lithography and deep etching to thin-film deposition and multi-layer integration. Its versatile fabrication facility supports wafer diameters ranging from 50 mm up to 300 mm, enabling prototyping on small substrates as well as scale-up to full 300 mm production. NOEL’s engineers excel at integrating novel materials and processes to create structures that often lack a conventional manufacturing path, while handling complex builds with multiple mask layers with both wet and plasma etching of silicon, dielectrics, and metals. Through a proven “Lab-to-Fab” approach, NOEL serves as a vital bridge from R&D to high-volume fabrication, accelerating the transition of innovative designs from the laboratory to the fab floor.Recent collaboration through Pure Wafer’s acquisition of NOEL Technologies has further expanded these capabilities. Pure Wafer, a leading U.S. provider of high-purity silicon wafer solutions, adds in-house supply of prime silicon substrates (50 mm–300 mm) and an extensive portfolio of exotic dielectric and metal thin films. By coupling NOEL’s proprietary MEMS processes with Pure Wafer’s materials expertise, the combined team delivers a “complete silicon solution” that enhances device performance and yield for next-generation sensors. This synergy is enabling cutting-edge sensor technologies in IoT, biomedical, and industrial applications, supported by faster prototyping cycles and a streamlined path to market. Equally important, the integration provides key business advantages – from cost efficiencies via comprehensive on-shore services (e.g., wafer reclaim and reuse) to improved supply chain resilience through a domestic source for critical materials and fabrication.This presentation will showcase how the NOEL–Pure Wafer partnership supports next-generation sensor innovation in alignment with the key industry tracks driving future advancements in IoT, Intelligent Sensing, Advanced embedded system Technologies, Multi-Sensor capabilities, Smart Manufacturing, and biomedical applications. By leveraging Pure Wafer and NOEL Technologies' expertise, MEMS and sensor innovators can achieve superior device performance, faster prototyping, and scalable production solutions. This collaboration is paving the way for next-generation innovative sensing solutions that drive technological breakthroughs across industries.United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
Register
