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United States

United States Overview of Semiconductor Manufacturing
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Course Description

This course offers a solid foundation in semiconductor manufacturing, from basic concepts to advanced techniques, providing practical insights into the tools, processes, and technologies driving the industry.

Learning Objectives

  • Gain a comprehensive understanding of the semiconductor industry and manufacturing process, design, and eco-system of the semiconductor industry
  • Understand the jargon, tools, and materials used in the design and fabrication of an integrated chip
  • Effectively be able to communicate semiconductor manufacturing concepts with other associates and industry professionals

Course Topics

  • Basic Electronics and Microelectronics: Definitions of essential electronic terms/concepts and introduction to microelectronics and integrated circuits
  • Process Nodes: Process nodes and their impact on device performance and cost
  • Device Physics and Transistor Operation: Principles of device operation and transistor functionality
  • Crystal Growth and Wafer Preparation: Crystal growth techniques and wafer preparation processes
  • Advanced Transistor Technologies: FDSOI, FinFETs, and Gate-All-Around (GAA) transistors and their impact on device performance
  • Circuit Design and Layout: Introduction to circuit design, layout techniques, and tools
  • Wafer Processing:
    • Mask Making and Lithography: Techniques and materials used in mask making and various lithographic methods (DUV, Immersion, EUV)
    • Clean Room Environments: Importance of clean rooms in semiconductor manufacturing and contamination issues
    • Etching and Cleaning Processes: Plasma and wet etching processes
    • Ion Implantation and Diffusion Techniques: Methods for doping and controlling diffusion in semiconductor fabrication
    • Deposition Techniques: RTP, CVD, ALD, and ALE techniques and their effect on device performance
    • Electroplating and Sputtering: Metal deposition techniques used in manufacturing
    • Packaging and Testing: Techniques such as wire bonding, die stacking, flip chip, and chiplets packaging, semiconductor testing processes
    • Metrology and Measurement Tools: Tools and methods used for precision measurement in semiconductor manufacturing
  • Semiconductor Industry Ecosystem: The major players in the industry 

Who Should Attend

Anyone interested in understanding semiconductor manufacturing, including new employees, professionals in related industries, and those seeking to broaden their knowledge of the field.

Instructor

Denny Frye 

PT International, LLC

Biography

Embassy Suites by Hilton Scottsdale Resort
5001 N. Scottsdale Road
Scottsdale, AZ 85250
United States

- SEMI U

Gain a comprehensive understanding of the semiconductor industry and the integrated circuit (IC) manufacturing process. This course is designed for new personnel in the field or anyone seeking a well-rounded knowledge of the tools, materials, and terminology used in semiconductor manufacturing.

Pricing
  • Members: $1,295 
  • Non-Members: $1,395 
  • Students/Vets: $1,195 

* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected].

8:30 am - 5:00 pm Off Add to Calendar 2024-10-22 08:30:00 2024-10-23 17:00:00 Overview of Semiconductor Manufacturing Gain a comprehensive understanding of the semiconductor industry and the integrated circuit (IC) manufacturing process. This course is designed for new personnel in the field or anyone seeking a well-rounded knowledge of the tools, materials, and terminology used in semiconductor manufacturing.PricingMembers: $1,295 Non-Members: $1,395 Students/Vets: $1,195 * For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected]. Embassy Suites by Hilton Scottsdale Resort 5001 N. Scottsdale Road Scottsdale, AZ 85250 United States SEMI.org [email protected] America/Phoenix public America/Phoenix Register Now
Event format
United States Understanding Semiconductor Technology and Business
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Course Description

The first part of the course provides a brief overview of semiconductor design and fabrication steps, encompassing IC design techniques, all wafer processing steps, assembly, and packaging. It delves into semiconductor jargon in laypeople terms, and various substrate types such as Si, SiGe, FDSOI, GaAs, SiC, GaN. Additionally, it discusses different types of transistors like pMOS, nMOS, Bipolar, BiCMOS, CMOS, FinFets, and GAA and their evolution and what applications they are used in.
 
The second part of the course focuses on semiconductor business aspects such as silicon economics, wafer processing costs, semiconductor revenue forecasts, driving forces in the industry, top semiconductor IDMs, market competitors based on market share, OEMs, foundries, top tool vendors, and Fabless companies.  Addresses the fastest-growing semiconductor markets based on geographic locations and applications, identifies semiconductor competitors/customers, and discusses major semiconductor markets like Automotive, PC, Mobile, Memory, Wireless, Cell phones, Consumer, Gaming, AI, IoT, Digital TV, Radio, Automotive, MEMS, and Emerging Technology & Impact on Industry.

Learning Objectives

  • Understand the fundamental principles and theories semiconductor technology.
  • Communicate with other associates and understand wafer processing steps.
  • Understand semiconductor business aspects such as silicon economics, wafer processing costs, semiconductor revenue forecasts, driving forces in the industry, top semiconductor IDMs, market competitors based on market share, OEMs, foundries, top tool vendors, and Fabless companies.
  • Review the semiconductor eco-system as it relates to design and fabrication of a semiconductor device. 
  • Gain knowledge of major semiconductor markets like Automotive, PC, Mobile, Memory, Wireless, Cell phones, Consumer, Gaming, AI, IoT, Automotive, MEMS, and Emerging Technology & Impact on Industry.
  • Demonstrate effective communication skills through written reports, presentations, and discussions related to semiconductor subjects.
  • Collaborate effectively with peers in group projects or discussions regarding semiconductor subjects.
  • Analyze and evaluate research literature in semiconductor technology.
  • Develop critical thinking and problem-solving skills applicable to semiconductor technology.

Who Should Attend

This course is suitable for anyone seeking a better understanding of the semiconductor industry, market leaders, terminology, business, and the semiconductor ecosystem.

Instructor

 

Denny Frye 

PT International, LLC

Biography


Embassy Suites by Hilton Scottsdale Resort
5001 N. Scottsdale Road
Scottsdale, AZ 85250
United States

SEMI U

Embark on a journey through semiconductor design, manufacturing, and business in this illuminating course. Explore IC design techniques, transistor evolution, and market dynamics. Delve into substrate types and industry economics, discovering the fastest-growing markets and key players shaping the semiconductor landscape.

Pricing
  • Members: $1,095 
  • Non-Members: $1,199
  • Students/Vets: $895

* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected].

8:30 am - 5:00 pm Off Add to Calendar 2024-10-21 08:30:00 2024-10-21 17:00:00 Understanding Semiconductor Technology and Business Embark on a journey through semiconductor design, manufacturing, and business in this illuminating course. Explore IC design techniques, transistor evolution, and market dynamics. Delve into substrate types and industry economics, discovering the fastest-growing markets and key players shaping the semiconductor landscape.PricingMembers: $1,095 Non-Members: $1,199Students/Vets: $895* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected]. Embassy Suites by Hilton Scottsdale Resort 5001 N. Scottsdale Road Scottsdale, AZ 85250 United States SEMI.org [email protected] America/Phoenix public America/Phoenix Register Now
Event format
United States From Concept to Reality: Advancing Digital Twins in Semiconductor Manufacturing Business Executive Technical

Suggested Hotels:

Embassy Suites by Hilton Milpitas Silicon Valley

901 East Calaveras Boulevard

Milpitas, CA 95035

(408) 942-0400

 

Courtyard by Marriott Milpitas Silicon Valley

1480 Falcon Dr.

Milpitas, CA 95035

(408) 719-1966

 

Event Sponsors

AirV Labs
Dassault Systems
INFICON
PhysicsX
SEEQ
Sentient Cloud

Sponsorship Opportunities

Enhance your brand with our exclusive sponsorship packages. For details, contact:

Eric Rude
Tel: +1.408.943.7047
Email: [email protected]

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From Concept to Reality: Advancing Digital Twins in Semiconductor Manufacturing

Following up on the SEMI Digital Workshop 2023, this workshop will delve into the practical aspects of implementing digital twin technology in semiconductor manufacturing. The aim is to bridge the gap between theoretical concepts and real-world applications, providing participants with actionable insights and strategies to successfully develop and integrate digital twins into their operations. Further the workshop aims to address some of the future upcoming challenges in the areas of integration of multi-modal real time data sources, security, process complexity, scalability, and standards.

 

SEMI HQ
673 S Milpitas Blvd.
Milpitas, CA 95035
United States

Morning, Day 1: December 4, 2024

8:00 am - 9:00 am

Registration & Breakfast​

9:00 am - 12:30 pm

Session #1 - Data Needs for Digital Twins - Data Sources, Integration & Interoperability

This session will explore the critical data requirements for creating and maintaining digital twins. Integrating multi-modal data sources (sensors, enterprise systems, equipment, etc.) that feed into digital twins, ensuring that they accurately reflect their physical counterparts is a minimum necessity. This session will also cover data integration techniques (from various factory systems), and interoperability to support dynamic digital twins.

9:00 am - 9:10 am
Mark da Silva
Mark da Silva​
Senior Director, Smart Manufacturing
SEMI

Welcome Remarks

9:10 am - 9:35 am
Mike Neel
Michael Neel
Director of Marketing
Inficon

Keynote​ - Enabling Autonomous Operations Through Integrated Digital Twins

9:35 am - 10:00 am
Robert Baseman
Robert Baseman
Senior Technical Staff Member
IBM

Semantic Models for Microelectronic Manufacturing & Development

10:00 am - 10:25 am
David McKee
Technology Leader & Managing Partner
Counterpoint Tech/DTC

Journey to Twins: A toolkit for Capabilities & Data to Digital Twins

10:25 am - 10:40 am

Coffee Break - Sponsored by INFICON

Inficon Logo 170x65
10:40 am - 11:05 am
Rad Desiraju
Rad Desiraju
Director, WW Industry Advisory
Microsoft

Overcoming Data Interoperability Challenges for Effective Digital Twins

11:05 am - 11:30 am
Wei Zhao
Wei Zhao
Head of Process Integration
Athinia
Chris Han-Adebekun
Chris Han-Adebekun
VP, Business Development
Athinia

Building Process & Supply Chain Digital Twins through Integrated Data Assets and Secure Data Sharing

11:30 am - 12:30 pm
Dave Henshall
Dave Henshall
Vice President of Business Development and Government Relations
Semiconductor Research Corporation
Chris Ritter
CTO
Idaho National Lab

Special Session - SmartUSA – Semiconductor Digital Twin Manufacturing USA Institute

12:30 pm - 2:00 pm

Lunch

Afternoon, Day 1: December 4, 2024

2:00 pm - 5:00 pm

Session #2 - Data Standards for Digital Twins: Managing Unclean Factory Data

This session will focus on the importance of data standards for digital twins in semiconductor manufacturing, particularly in the context of dealing with unclean factory data. It will explore the challenges associated with unclean data and discuss strategies for cleaning and standardizing to ensure seamless ingestion into digital twins at various levels. Best practices for data validation, transformation, and integration as well as how to implement robust data standards to enhance reliability and accuracy of digital twins.

Sponsored by - Seeq

SEEQ
2:00 pm - 2:25 pm
Dr. Joseph Ervin
Dr. Joseph Ervin
Product Line Head of Semiverse Solutions Group
Lam Research

Keynote - Addressing Future Challenges in the Stochastics Era of Patterning with EUV Dry Resist

New patterning technologies will be needed to advance the device roadmap to 2 nm and beyond. Minimum pitch scaling will be exceptionally difficult to achieve at these advanced nodes, even with EUV patterning. Stochastic effects using wet resists during EUV patterning become problematic at the nanoscale, and can lead to line collapse, bridging, unacceptable line edge roughness (LER) and line width roughness (LWR). These stochastic effects present challenges when optimizing the tradeoffs between EUV resist resolution, dose, sensitivity, line edge / line width roughness, defectivity and cost.
In this talk, we will review the basics of dry resist technology, including dry resist equipment requirements, process flows and process integration modeling. In addition, we will present data that documents the advantages of dry resist technology over wet resist technology, demonstrating superior image quality, scaling and yield. We will conclude the talk by demonstrating a digital twin of the process integration and usage of optimization to achieve improved LER/LWR characteristics.

2:25 pm - 2:50 pm
Alan Weber
Alan Weber
Vice President, New Product Innovations
Cimetrix by PDF Solutions

Charting the Digital Twin Standardization Path: An Iterative Implementation and Abstraction Process

2:50 pm - 3:15 pm
Brett Brimhall
Deloitte

3:15 pm - 3:30 pm

Coffee Break - Sponsored by INFICON

Inficon Logo 170x65
3:30 pm - 3:55 pm
Andres Torres
Andres Torres
Engineer and Key Expert
Siemens

Feature Engineering as the bridge to Semantic Factory Data

3:55 pm - 4:20 pm
Michael Bowcutt
Michael Bowcutt
Director of Sales Engineering for Romaric products at camLine
camLine USA

Control Software Integration with Digital Twins: How Virtual Data Aligns with Physical Reality

4:20 pm - 5:20 pm
Kenneth Smith
Moderator
Kenneth Smith
VP Growth Markets
Seeq
Sean Tropsa
Sean Tropsa
Principal Analytics Engineer
Seeq

Panel: Harmonizing Standards for Semiconductor Digital Twins​ ​

5:30 pm - 7:00 pm

Networking Reception - Sponsored by Sentient Cloud

Sentient Cloud

Morning, Day 2: December 5, 2024

8:00 am - 9:00 am

Registration & Breakfast​

9:00 am - 12:30 pm

Session #3 - Modeling High Complexity Semiconductor Processes

This session will explore the integration of digital twin technology in modeling high complexity semiconductor processes. As the semiconductor industry advances, the need for precise and efficient modeling techniques becomes crucial. Digital Twins offer a transformative approach to simulate and optimizes these processes, though challenges exist. Cases studies and future innovations will also be covered in this session.

9:00 am - 9:05 am
Mark da Silva
Mark da Silva​
Senior Director, Smart Manufacturing
SEMI

Welcome Remarks

9:05 am - 9:30 am
Umesh Kelkar
Umesh Kelkar
Master/Vice President, Semiconductor Products Group
Applied Materials

Keynote: Key Enablers for Semiconductor Equipment and Process Digital Twins: Accelerated Computing (AC), Artificial Intelligence (AI) and Physics Modeling

9:30 am - 9:55 am
Prith Bannerjee
Prith Bannerjee
Chief Technology Officer
Ansys

AI Driven Digital Twins for Semiconductor Manufacturing

9:55 am - 10:20 am
Xi-Wei Lin
Xi-Wei Lin
Executive Director, Applications Engineering
Synopsys

AI and Physics-based Models for Technological Development with High Complexity Semiconductor Processes

10:20 am - 10:45 am

Coffee Break - Sponsored by PhysicsX

PhysicsX
10:45 am - 11:10 am
Amit Lal
Amit Lal
Professor, Cornell University
Cornell
Peter Doerschuk
Peter Doerschuk
Professor
Cornell University
Ben Davaji
Ben Davaji
Assistant Professor
Northeastern University

Digital Twin Flow Using AI/ML Applied to Ferroelectric Memory

11:10 am - 11:35 am
John Maculley
John Maculley
Semiconductor Industry Strategy Consultant
Dassault Systemes

Leveraging Virtual Twins and AI for Enhanced Fabrication Technology Co-Optimization in Semiconductor Manufacturing

11:35 am - 12:30 pm
Pushkar Apte
Strategic Technology Advisor and Global Data-AI Lead
SEMI

Panel Discussion

12:30 pm - 2:00 pm

Lunch - Sponsored by Dassault Systemes

Dassault Systems

Afternoon, Day 2: December 5, 2024

2:00 pm - 5:00 pm

Session #4 - GenAI & AI/ML Role in the Development of Digital Twins - Implementation Strategies for DT

Integrating AI/GenAI & Digital Twins - Explore the cutting-edge integration of Generative AI (GenAI) and Artificial Intelligence/Machine Learning (AI/ML) in the creation and evolution of digital twins. This session will delve into how GenAI & AI/ML technologies are revolutionizing the simulation, prediction, and real-time replication of physical assets in semiconductors through case studies and practical applications. 

 

2:00 pm - 2:25 pm
Kamaljeet Ghotra
Kamaljeet Ghotra
Senior Director, Go-To Market and Digital Strategy
PDF Solutions

Keynote - Accelerating Digital Twins with Gen AI

The rise of sophisticated AI tools, including generative AI, is revolutionizing the semiconductor industry by enabling the analysis of vast datasets to generate valuable insights. Executives in the sector see generative AI as a transformative force rather than just another tool. They believe it can deliver significant value, particularly in manufacturing, operations, and maintenance, its potential for process and equipment analysis, Predictive maintenance and smart diagnostics.

As fabs adopt smart manufacturing and virtual modeling it is pertinent for digital twins to leverage technologies like generative AI for data generation, Data Synthesis/Augmentation, Real Time Analysis, Model Optimization (AI enhanced physics models) , Rapid Prototyping and Accelerated Design and Development with data-driven model-based learning.

2:25 pm - 2:50 pm
Peter Lendermann
Peter Lendermann
CTO
D-SIMLAB

About Cross-Fertilization between Digital Twins and AI Techniques for Capacity Planning and WIP Flow Optimisation in Semiconductor Fabs​

2:50 pm - 3:15 pm
Kiran Karunakaran
Kiran Karunakaran
Chief Technology Officer
Via Automation

Developing Explainable Digital Twins for the Semiconductor Industry Using GenAI, Knowledge Graphs, and ML Techniques​

3:15 pm - 3:30 pm

Coffee Break - Sponsored by PhysicsX

PhysicsX
3:30 pm - 3:55 pm
Mark Huntington
Mark Huntington
Managing Director of North America
PhysicsX

Real-Time Digital Twins for Semiconductor Manufacturing: Accelerating Multi-Physics Optimization with Physics-Based AI

3:55 pm - 4:20 pm
Becky Kelderman
Becky Kelderman
Solutions Sales Manager
Rockwell Automation

Advancing Industrial Data Architectures & Models for AI in Process Digital Twins

4:20 pm - 5:20 pm
Mithun Kamat
Moderator
Mithun Kamat
Partner
McKinsey

Panel - Rewiring organizations for AI / Digital twin: a business-backed view of successful implementation and challenges in adoption of Digital twins in the semiconductor industry

-

Following up on the SEMI Digital Workshop 2023, this workshop will delve into the practical aspects of implementing digital twin technology in semiconductor manufacturing. The aim is to bridge the gap between theoretical concepts and real-world applications, providing participants with actionable insights and strategies to successfully develop and integrate digital twins into their operations. Further the workshop aims to address some of the future upcoming challenges in the areas of integration of multi-modal real time data sources, security, process complexity, scalability, and standards.

 

Given the exclusivity and richness of discussions, please note that seats are capped at 80 attendees. Don’t wait to secure your spot.

 

8:00 am - 5:00 pm Off Add to Calendar 2024-12-04 08:00:00 2024-12-05 17:00:00 From Concept to Reality: Advancing Digital Twin in Semiconductor Manufacturing Following up on the SEMI Digital Workshop 2023, this workshop will delve into the practical aspects of implementing digital twin technology in semiconductor manufacturing. The aim is to bridge the gap between theoretical concepts and real-world applications, providing participants with actionable insights and strategies to successfully develop and integrate digital twins into their operations. Further the workshop aims to address some of the future upcoming challenges in the areas of integration of multi-modal real time data sources, security, process complexity, scalability, and standards. Given the exclusivity and richness of discussions, please note that seats are capped at 80 attendees. Don’t wait to secure your spot.  SEMI HQ 673 S Milpitas Blvd. Milpitas, CA 95035 United States SEMI.org [email protected] America/Los_Angeles public America/Los_Angeles Purchase On-Demand

Registration

& Virtual Access

Registration is required whether you are attending IN-PERSON or VIRTUAL!

Virtual + Voting instructions will be sent to registered members the week prior to the meeting set.

PLEASE NOTE

  • In addition, you must be a SEMI Standards Program Member to participate in the meetings. 
  • Membership is FREE!
  • Fill out the Application Form to be a Standards Member.
United States standards-500w.jpg

SEMI HQ
673 South Milpitas Blvd
Milpitas, CA 95035
United States

- Standards

Registration is open!

Join us for the SEMI Standards Meetings

IN-PERSON + VIRTUAL!
 

SEMI Standards will host 8 committees + over 40 task forces engaged in various standardization activities, including:

  • Environmental, Health, and Safety (EH&S)
  • Facilities
  • Flexible Hybrid Electronics
  • Gases
  • Information & Control
  • Liquid Chemicals
  • MEMS/NEMS
  • Physical Interfaces & Carriers
  • 3D Packaging & Integration

Note | Some Technical Committees + Task Forces may meet virtually outside of this Meeting set.

FULL SCHEDULE | (PDF) or (Excel)

All meetings are in Pacific Time.
Subject to change, please check back frequently.
Last updated: November 4, 2024

Off Add to Calendar 2024-11-04 00:00:00 2024-11-07 00:00:00 North America Standards Fall Meetings 2024 Registration is open!Join us for the SEMI Standards MeetingsIN-PERSON + VIRTUAL! SEMI Standards will host 8 committees + over 40 task forces engaged in various standardization activities, including:Environmental, Health, and Safety (EH&S)FacilitiesFlexible Hybrid ElectronicsGasesInformation & ControlLiquid ChemicalsMEMS/NEMSPhysical Interfaces & Carriers3D Packaging & IntegrationNote | Some Technical Committees + Task Forces may meet virtually outside of this Meeting set.FULL SCHEDULE | (PDF) or (Excel)All meetings are in Pacific Time.Subject to change, please check back frequently.Last updated: November 4, 2024 SEMI HQ 673 South Milpitas Blvd Milpitas, CA 95035 United States SEMI.org [email protected] America/Los_Angeles public

Contact

Kevin Nguyen
Manager, International Standards Operations
(EH&S)

Laura Nguyen
Sr. Coordinator, International Standards
(Facilities, Flexible Hybrid Electronics, Gases, Liquid Chemicals, MEMS/NEMS, Physical Interfaces & Carriers, 3D Packaging & Integration)

Michelle Sun
Coordinator, International Standards
(Information & Control)

SAN FRANCISCO – July 11, 2024 – The EVG®880 LayerRelease™ system from EV Group (EVG) has won the 2024 Best of West award, SEMI and Semiconductor Digest announced today at SEMICON West 2024 at the Moscone Center in San Francisco. Presented by SEMI and Semiconductor Digest each year, the Best of West award recognizes innovative new products or services that are significantly advancing the electronics manufacturing supply chain or a particular manufacturing capability.

SEMICON WestThe EVG®880 LayerRelease™ system is the first high volume manufacturing (HVM) equipment platform incorporating EVG’s innovative LayerRelease™ technology. It enables nanometer-precision release of bonded, deposited or grown layers from silicon carrier substrates using an IR laser coupled with specially formulated inorganic release materials. As a result, it eliminates the need for glass carriers—enabling ultra-thin chiplet stacking for advanced packaging, as well as ultra-thin 3D layer stacking for front-end processing, including advanced logic, memory and power device formation, to support future 3D integration roadmaps.

“The EVG 880 LayerRelease system enables an important step forward for 3D integration,” said Pete Singer, Editor-in-Chief of Semiconductor Digest. By enabling 3D stacking of ultra-thin layers, the EVG880 LayerRelease system allows for shorter distances between stacked dies, which in turn allows faster data exchange from one die to another while reducing power consumption. “Congratulations to EV Group for again winning the Best of West competition.” The company previously won for its LITHOSCALE Maskless Exposure System in 2021.

EV GroupEV Group is a leading supplier of equipment and process solutions for the manufacture of semiconductors, microelectromechanical systems (MEMS), compound semiconductors, power devices and nanotechnology devices. Key products include wafer bonding, thin-wafer processing, lithography/nanoimprint lithography (NIL) and metrology equipment, as well as photoresist coaters, cleaners and inspection systems.

EV Group received the Best of West award in a ceremony today at SEMICON West 2024.

About Semiconductor Digest

Through a mix of news, contributed articles and staff-written articles, Semiconductor Digest (www.semiconductor-digest.com), is dedicated to providing global information about the design, manufacturing, packaging and testing of semiconductors and other types of electronic devices, including MEMs, LEDs, displays, power electronics, optoelectronics/photonics, biomedical devices, solar cells, thin film batteries and flexible electronics. Semiconductor Digest consists of a website, magazine and topic-focused newsletters.

About SEMI

SEMI® is the global industry association connecting over 3,000 member companies and 1.5 million professionals worldwide across the semiconductor and electronics design and manufacturing supply chain. We accelerate member collaboration on solutions to top industry challenges through Advocacy, Workforce Development, Sustainability, Supply Chain Management and other programs. Our SEMICON® expositions and events, technology communities, standards and market intelligence help advance our members’ business growth and innovations in design, devices, equipment, materials, services and software, enabling smarter, faster, more secure electronics. Visit www.semi.org, contact a regional office, and connect with SEMI on LinkedIn and X to learn more.

SEMI Contact

Samer Bahou
Phone: 1.408.943.7870
Email: [email protected]
 

Semiconductor Digest Contact

Pete Singer, Editor-in-Chief
Phone: 1.978.470.1806
Email: [email protected]

Rogue Valley Microdevices (RVM), an advanced manufacturing company specializing in microelectromechanical systems (MEMS), is set to participate in SEMICON West 2024, North America’s premier exhibition and conference for the semiconductor supply chain (July 9-11, 2024, San Francisco). This comes on the heels of the U.S. Department of Commerce’s recent announcement that the company has signed a non-binding preliminary memorandum of terms (PMT) for up to $6.7 million in proposed direct funding under the CHIPS and Science Act. See press release link below: U.S. Department of Commerce Announces Preliminary Terms with Rogue Valley Microdevices to Support the Construction of New Foundry (July 1, 2024).

RVM is the first pureplay MEMS foundry to secure proposed funding under the CHIPS Act. It is also the first woman- and minority-owned business to receive a proposed CHIPS Act investment.

The proposed CHIPS investment will support the construction of RVM’s pureplay MEMS and sensor foundry facility in Palm Bay, Florida. The new facility is especially significant because it will be the first MEMS foundry in North America capable of manufacturing 300mm wafers.

“We are passionate about microelectronics and are thrilled to expand our work with customers through the proposed CHIPS Act funding,” said Rogue Valley Devices Founder & CEO Jessica Gomez. “We are proud that the federal government has recognized our important role in the MEMS and sensors ecosystem. And we look forward to augmenting our role in the domestic supply of MEMS devices for automotive, agricultural, industrial and mil/aero applications — including those that require 300mm capability.”

“Increased American production of microchips and microelectronics is critical to meeting our nation’s supply chain needs, and Florida’s Space Coast is home to the best technological, aerospace and engineering workforces you can find,” said Congressman Bill Posey. “Rogue Valley Microdevices’ expansion in Palm Bay is much welcome news, and we look forward to working with them as part of our great community.”

MEMS, MedTech and SEMICON West
MEMS technology continues to make a significant impact on the biomedical space, with microneedles as a key emergent application. Ms. Gomez will explore this topic during her SEMICON West presentation, “MEMS as the Cornerstone of Microneedle Technology,” on Thursday, July 11, at 1:55 pm in the Smart MedTech Theater, Moscone South, Exhibition Level, Hall C.

About Rogue Valley Microdevices
Rogue Valley Microdevices is a full-service precision MEMS foundry that combines state-of-the-art process modules with the engineering expertise to go seamlessly from custom design to manufacturing. Specializing in MEMS and sensors manufacturing — including microfluidics and lab-on-chip platforms — Rogue Valley Microdevices offers a flexible equipment set and the ability for customers to start with smaller batch sizes, serving a key function in the commercial MEMS manufacturing ecosystem.
Rogue Valley Microdevices also maintains the broadest and most comprehensive set of wafer services commercially available — with over 50 unique dielectric and conductive thin films and all services performed in its own class 100 cleanroom. For more information, email: [email protected], visit: https://roguevalleymicrodevices.com, and follow us on LinkedIn.

To schedule a media briefing with Jessica Gomez during SEMICON West, please reach out to the media contact listed below.

Media Contact:
Maria Doyle
Doyle Strategic Communications
[email protected]
Tel: +781-964-3536

scia Systems’ high-precision ion beam process solutions are enabling the automotive, cloud computing, AR/MR, and mobile communications industries

Chemnitz, Germany, July 1, 2024 – scia Systems GmbH, an industry leader in advanced ion beam and plasma process equipment for microelectronics, MEMS, and precision optics industries, today announced that it will highlight key advances in ion beam processing for semiconductor, sensor and photonic integrated circuit (PIC) manufacturing at SEMICON West 2024. The premier microelectronics event will be held July 9-11, 2024, at the Moscone Center in San Francisco, Calif. scia Systems’ high-precision solutions are playing an essential role in enabling many of today’s high-growth consumer and industrial applications.

According to Dr. Michael Zeuner, CEO of scia Systems, “As semiconductors, sensors, and optical devices increase in complexity due to smaller features, new exotic materials, and more layers and complex structures, the processes used to manufacture them require higher levels of precision. Our advances in ultra-precision ion beam process technologies are enabling manufacturers’ success in producing these devices, which are driving cloud computing, augmented/mixed reality (AR/MR), automotive, telecommunications, and many other industries. A case in point, every modern cell phone has components that have been manufactured using a scia Systems product. We look forward to highlighting these solutions, as well as the many high-growth applications that they enable, at SEMICON West – the premier event for the semiconductor ecosystem.”

Ion beam etching solutions enable significant growth in photonic integrated circuits
Demand for PICs is growing rapidly in telecommunications and data centers due to their wide bandwidth, low transmission loss, and numerous other advantages over traditional electronic integrated circuits. Integrating new materials, material stacks, and designs requires new etching solutions. scia Systems’ advanced ion beam etching and trimming processes enable manufacturing of three-dimensional optoelectronic microstructures for PICs, such as waveguides and other optical components. Reducing microroughness by ion beam trimming is another promising application area that enhances the production of high-performance PICs. Further applications include nano-structured surface relief gratings for AR/MR systems, and surface form error correction for telescope mirrors, X-ray optics, lenses, and conventional optics.

Ion beam etching technology produces GMR/TMR sensors for mega markets
High-precision sensors that use magnetic storage, most notably giant magnetoresistance (GMR) and tunnel magnetoresistance (TMR) sensors, are used to detect any type of motion including proximity, rotations or vibrations. These have been rapidly adopted across a wide variety of industries and applications, including automotive electronics, industrial equipment, and cloud storage. However, the complex, multi-layer composition of these sensors creates significant challenges for traditional chemical and dry etching processes, which have difficulty processing magnetic materials. scia Systems overcomes these limitations with its high-precision ion beam etching technology, enabling the manufacture of high-performance GMR sensors for flexible and wearable electronics, including AR/MR headsets, and TMR sensors for Internet of Things (IoT), automotive, smart home, eMobility, and many other applications.

Ion beam etching solutions for precision reverse engineering of ICs
Reverse engineering is an essential step in semiconductor manufacturing. By conducting verification, failure analysis, and research of internal device structures, engineers can isolate and troubleshoot problems to improve manufacturing yields. Reverse engineering involves exposing internal components, delayering to analyze each layer of the device, imaging, and post-processing. Conventional delayering processes such as wet chemical etching, CMP or plasma etching are often expensive, error-prone, and limited in application. scia Systems’ ion beam etching technology enables precise processing within the micro- and nanometer-size range and atomic-level-thickness range for different materials at once.

See scia Systems at SEMICON West
SEMICON West attendees interested in learning more about scia Systems and its advanced ion beam and other thin-film process solutions are invited to visit the Moscone Center North Hall, Booth #553 on July 9-11 in San Francisco.

About scia Systems GmbH
Founded in 2013, scia Systems is a technology leader in thin-film process equipment based on advanced ion beam and plasma technologies. The systems are used for coating, etching, and cleaning processes with nanometer resolution and have been successfully implemented in various high-tech industries worldwide, including microelectronics, MEMS, and precision optics industries. For more information, visit the company’s website at www.scia-systems.com.

United States Register Now Stay Connected https://semiexpo.semi.org/ SEMIEXPO_Heartland Business Expositions

INAUGURAL EVENT FOCUSED ON SMART MANUFACTURING & SMART MOBILITY

Join us for a groundbreaking Midwest conference and tradeshow on April 1-2, 2025, focused on Smart Manufacturing and Smart Mobility with an emphasis on the semiconductor industry! Automotive electronics and smart manufacturing are two of the key end markets on the path to $1T in semiconductor revenue.  

A significant amount of both markets is concentrated in the Midwestern United States. SEMIEXPO in the Heartland will bring these two key markets together and provide an opportunity for collaboration and growth.

Smart Manufacturing

  • The program will focus on the deployment of Industry 4.0 or Smart Manufacturing tools, technologies, and methods for the semiconductors required for this growing market. 

Smart Mobility

  • The program will unite stakeholders in the semiconductors/sensors and mobility ecosystems to identify and address technical issues and supply chain dynamics that are best addressed collectively. 

Ways to Participate

  • Exhibit
  • Sponsor
  • Speak
  • Attend

MAKE YOUR MARK AT THE INAUGURAL SEMIEXPO HEARTLAND

Plan Now to Exhibit or Sponsor. Contact—
Shane Poblete | +1 202-847-5983  | [email protected]

 

STAY INFORMED: SEMIEXPO HEARTLAND—SEH Interest Form

 

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Verific Design Automation today affirmed its position as the leading provider of front-end platforms powering an emerging electronic design automation (EDA) space by collaborating with a group of well-funded artificial intelligence (AI) EDA startups.

These new AI EDA companies use Verific’s unsurpassed language support for fast, accurate large language model (LLM) development, speeding time to market for products that range from functional verification, chip design to code development.

AI EDA providers PrimisAI and Silimate, founded by former chip designers, will be in the Verific booth (#1414) AI showcase at the 61st Design Automation Conference (DAC) June 24-26 at Moscone West in San Francisco.

“This new and exciting market segment is about to change the entire makeup of the EDA industry,” says Rick Carlson, vice president of Verific. “We are about to see a variety of tools, technologies and methodologies destined to change the way chip design and verification is done.”

Introducing the EDA Startups Ushering in the Era of AI EDA
PrimisAI and Silimate will be showcased in the Verific DAC booth and present their unique use of AI technology to eliminate error-prone repetitive tasks for efficient and more productive chip design.

PrimisAI offers a generative AI solution for chip design with advanced language-to-code and language-to-verification capabilities through its interactive AI assistant to address complex hardware challenges across the entire design stack from concept to bitstream/GDSII. RapidGPT, unveiled earlier this year, lets engineers interact with their design and the entire EDA ecosystem with a natural language interface, boosting productivity and accelerating time-to-market. Founded by serial entrepreneur Naveed Sherwani who serves as chairman and CEO, PrimisAI is backed by two early-stage investors.

“Verific’s front-end platform lived up to its well-earned status of industry standard as we implemented it in RapidGPT,” remarks Pierre-Emmanuel Gaillardon, CSO of PrimisAI. “The robustness and quality of the Verific front-end platform ensured we would deliver a tool that would give engineers a seamless and efficient workflow.”

Silimate, backed by Y Combinator, is building the co-pilot for chip designers to help build better chips faster. Silimate finds functional bugs, predicts power, performance and area (PPA) issues, and recommends real and accurate fixes in real time, and is already being used by chip teams building complex IP and SoCs. Co-founders Ann Wu and Akash Levy previously built chips and EDA tools at Apple, Stanford, NVIDIA, and Synopsys.

“Verific consistently produces quality products and offers exceptional quality support,” comments Wu. “Their parsers are fantastic and result in very quick tool bring-up times for our customers.”

Metalware co-founded by Ryan Chow and Andrew Nedea is another Verific front-end platform user. It was started with initial funding from Y Combinator with the mission to accelerate embedded development using AI technology after personally experiencing repeated bottlenecks in embedded software at SpaceX. The Metalware AI EDA tools help designers rapidly write HDL and embedded C/C++ by combining insights from manuals, datasheets and code, offering 10x faster development by automating low-level programming.

“Verific embodies our stated goals to reduce the time it takes to design chips and systems,” affirms Chow. “Verific and its team of experienced EDA engineers have shown repeatedly that its front-end platforms enable a project that would normally take days to be completed in hours.”

Another AI EDA startup in stealth mode is also a new Verific user. Details will be announced shortly.

DAC AI Showcase
Verific will demonstrate its SystemVerilog, Verilog, VHDL and UPF front-end platforms, while PrimisAI and Silimate will be in the Verific DAC Booth #1414 at various times of the day to give 10-minute presentations.

DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

To arrange a demonstration or private meeting, send email to [email protected]

DAC registration is open.

About Verific Design Automation
Verific Design Automation is the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effective worldwide. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry since it was founded in 1999.

Engage with Verific at:
Email: [email protected]
Website: www.verific.com
LinkedIn: https://www.linkedin.com/company/verific-design-automation-inc/
Facebook: https://www.facebook.com/Verific-Design-Automation-100448363329771/

Primarius Technologies will demonstrate its entire portfolio of EDA toolchain and one-stop design enablement solutions that integrate advanced parallelization technologies with industry-proven modeling and simulation engines at the 61st Design Automation Conference (DAC) June 24-26 at Moscone West in San Francisco.

Also announced today: Primarius acquired Magwel N.V., provider of 3D solver- and simulation-based layout analysis and design solutions for digital, analog/mixed-signal, power management, automotive and RF ICs, and launched ESDiTM, a chip-level human body model (HBM) analysis platform and power device design, and PTMTM, a layout verification tool family.

Demonstrations will highlight Primarius’ fast, accurate device modeling and cell library characterization and circuit simulation solutions based on its continuous innovation and R&D expertise, including:

• SDEPTM, the spec-driven extraction platform that builds auto model extraction flows for fast SPICE model extraction, a key engine enabling efficient Design-Technology Co-Optimization (DTCO), and an extended capability on top of the de facto golden-standard SPICE modeling platform, BSIMProPlusTM.
• NanoSpice XTM, the latest high-performance SPICE simulator addressing simulation capacity and accuracy challenges of big post-layout designs at advanced process nodes.
• NanoSpice Pro XTM, the latest FastSPICE simulator with simulation performance and accuracy needs tailored for SRAM, DRAM, Flash and big analog-on-top designs in high-performance computing, mobile, AI and other advanced applications.
• NanoCellTM, the latest standard cell library characterization solution employs advanced distributed parallel architecture technology and cell circuit analysis extraction algorithms embedded with a high-precision SPICE simulator, making it a fast, accurate and easy-to-use alternative to other commercial solutions.
• ESDi, state-of-the art HBM analysis, simulation and verification tool for on-chip ESD protection.

The Primarius Product Portfolio
IC company challenges designing and manufacturing high-end chips have increased sharply. Foundries and IDMs need to provide their design customers with more comprehensive and accurate SPICE models, more reliable and complete PDKs, and more coverage of standard cell library within shorter development cycles. Chip designers also require stronger COT capabilities to work with device engineers to customize process and devices, develop customized SPICE models, and perform re-characterization of cell libraries based on actual applications.

Primarius provides complete EDA toolchain and a one-stop design enablement technical development solutions. Innovations like these can shorten the SPICE model development cycle from several months to a few weeks or even hours for quick iteration addressing the efficiency bottleneck of DTCO. The advanced simulation technologies speed-up challenging circuit simulation by several times, and the latest cell library characterization solution provides the best throughput with near-linear scaling on thousands of x86 or ARM CPU cores on a computer farm or public cloud.

It aims to enable faster turnaround from technology development to advanced chip designs. Solutions include advanced analysis capabilities for high-sigma yield, aging, EM/IR, ESD, signal integrity and more targeting optimum yield and power, performance and area (PPA).

Primarius also provides the 9812 series, an industry-golden low frequency noise testing system used by most industry-leading semiconductor companies worldwide. Its latest release, 9812AC, is the only commercial low-frequency noise system under AC excitation and designed for the most advanced process development and chip designs.

Magwel N.V. Acquisition
Primarius acquired Belgian-based Magwel N.V. driven by broad market demand and technological evolution, integrating its chip-level HBM ESD analysis platform, the power device design and layout verification tool suite and other technologies into the Primarius portfolio.

“Primarius and Magwel share a common goal of enhancing the market competitiveness of overall analog and power semiconductor solutions,” states Dr. Lianfeng Yang, President of Primarius. “Magwel's integration will further advance our strategy to optimize DTCO, enhance our technology portfolio, expand our product coverage and further strengthen and consolidate our market competitiveness.”

Availability and Pricing
Primarius Technologies. Pricing is available upon request.

For more information, visit the Primarius website or send email to [email protected].

Primarius Technologies at 61st DAC
Primarius Technologies will be in DAC booth #1415 Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

To arrange a private meeting or demonstration of the Primarius Technologies product portfolio, send email to: [email protected].

DAC registration is open.

About Primarius
Primarius Technologies (688206.SH) is a global electronic design automation (EDA) company providing innovative DTCO-enabled EDA solutions for advanced technology development, and complex full custom designs including analog, mixed-signal and memory circuits. Primarius provides the industry’s de facto golden SPICE modeling solution adopted by most of the leading semiconductor companies for more than a decade, and leading SPICE/FastSPICE technologies proven by leading memory and SoC design companies worldwide. Its design enablement EDA solutions enable a full coverage of fab technology development and fabless COT flow development including device testing systems, SPICE modeling and PDK development solutions, and standard cell library characterization solutions. Built around an innovative SPICE/FastSPICE dual engine, Primarius provides a complete circuit simulation and analysis solution with comprehensive high-sigma yield and signal integrity analysis, aging and EM/IR, ESD simulation and advanced circuit checking capabilities. Primarius also provides a complete full custom design environment with advanced circuit design and optimization, layout automation and physical verification functions, and hierarchy design planning and timing analysis solutions for advanced SoC designs. Visit Primarius Technologies for more information.