Digital Twins are no longer a futuristic concept in semiconductor manufacturing—they’re fast becoming the backbone of next-generation fabs. But here’s the challenge: without a robust, scalable data platform to unify, secure, and interpret the torrent of information flowing across design, manufacturing, packaging, and test, digital twins cannot deliver their transformative potential. At SEMICON West in Phoenix, Arizona on October 6, 2025 from 1–5 p.m., join us for a high-impact technical workshop that explores how advanced data platforms are fueling the next wave of innovation—enabling smarter, faster, and more precise decisions across the semiconductor lifecycle.What You’ll Learn – Gain insights on proven reference architectures for scalable data platforms, integration patterns that support digital twin ecosystems, real-world use cases from fabs and OSATs applying AI/ML at scale, best practices in managing governance and security across complex data pipelines.Modern Data Platform Architectures – Designed for speed, scale, and semiconductor precisionBreaking Down Silos – Leveraging shared ontologies and data fabrics for seamless interoperabilityAI-Enhanced Digital Twins – Real-world deployments across fabs and OSATsFederated Learning in Action – Secure, multi-party collaboration without compromising IPData Security Governance – Proven practices for high-stakes manufacturing environments Distinguished Speakers – Hear directly from leaders advancing digital twin and federated learning initiatives at the SmartUSA Institute and across the semiconductor ecosystem. Anshu Bahadur, Senior Program Manager, Technology Communities at SEMI, will open the workshop and introduce speakers who will share how they’re building these next-generation platforms and deploying them across fabs, OSATs, and the full manufacturing flow. Following individual presentations, the session will close with a panel discussion featuring these executives. Ross Kunz, Director of Technology, SmartUSA Institute (Keynote Speaker)Dr. Adam Schafer, CEO, Athinia TechnologiesDhara Vaishnaw, Head of Solution Architecture, AWSDr. Gautham Unni, Head of Solutions and Business Development, Semiconductor, AWSJonathan Holt, Senior Director, Product Management, PDF SolutionsDr. Surya Kalidindi, CEO, Multiscale TechnologiesWho Should Attend? This workshop is designed for: Data Platform Architects building the next-gen semiconductor backboneSmart Manufacturing Engineers integrating fab and test dataAI/ML Practitioners scaling models into production workflowsInnovators shaping digital twin systems for complex, high-precision manufacturing Why Attend? Because the future isn’t waiting. Digital Twins, powered by scalable data platforms, are redefining how the semiconductor industry innovates, collaborates, and competes. Don’t just keep up with the future—build it. Anshu Bahadur is Senior Program Manager, Technology Communities at SEMI

As the volume of regulations grows across all levels of government, both in the U.S. and abroad, the semiconductor industry is increasingly struggling to keep up with its reporting obligations. Potential consequences include shipments delayed by customs, existing stocks of materials, parts, and components unexpectedly being made obsolete, and disruptions to multiple tiers of the supply chain that persist over time.To minimize the burden of numerous, varied reporting expectations, the SEMI PFAS Transparency Working Group, led by Intel and Tokyo Electron, is working to:Enable standardized communication on the presence of Per- and polyfluoroalkyl substances (PFAS) in chemical formulations, materials, tools, parts, and fab infrastructure to minimize the burden of varied reporting expectations;Enable traceability; andProtect confidential business information. While the initial focus of the effort is on PFAS, the intent of the group is for the methodology to be applicable to other substance reporting requirements.The group will be holding a working session at SEMICON West in Phoenix, Arizona on Wednesday, October 8 from 10:30 a.m.-12:00 noon at the North Building, 200 Level, Room 229A of the Phoenix Convention Center. All segments of the semiconductor manufacturing supply chain are invited to join the meeting and contribute to this critical effort. This session is intended for individuals involved in: Data management and reportingSupply chain managementMajor business continuity planning and crisis managementRisk assessment and mitigationEHS/regulatory complianceSub-supply chain visibility challengesThe PFAS transparency effort will also be introduced during the SEMI EHS Summit and SEMI Global Standards Summit, both scheduled on Tuesday, October 7.For additional resources, download the PFAS Explainer or SEMI PFAS Position Paper. Contact [email protected] for questions or more information about the working group session.James Amano is Senior Director of EHS at SEMI.

The SEMI Startups for Sustainable Semiconductors (S3) program announced 15 startups chosen as finalists for pitching to the industry at SEMICON West 2025 in Phoenix, Arizona. The finalists were chosen from a field of 35 semifinalists after a virtual pitch event over 2 days. Startups were evaluated by the organizing committee on five factors: the sustainability impact on our industry, commercial viability of product, company value proposition, the quality of the pitch and the startup team.The committee, made up of experienced Corporate Venture Capitalists (CVCs) from the global semiconductor industry, initially received 145 submissions in all three categories identified for 2025:Sustainable Semiconductor ManufacturingSustainable Data CenterGen AI for Sustainable DesignNow in its 4th year, the program features strong exposure to semiconductor industry CVCs, through the personal mentoring each startup receives. Mentoring topics are tailored to align with the needs and strategic positioning of the startup business plan, and can range from basic introduction to semiconductor manufacturing, to connections to new funding sources. A full analysis of the program over the past 3 years is available here.The SEMI Startups for Sustainability Semiconductor pitch event will take place at the Sustainability Pavilion Stage on Wednesday, October 8 starting at 1:00 p.m. Program lead John Wei of Applied Ventures will open the session and introduce a fireside chat featuring Dr. Om Nalamasu, CTO of Applied Materials and Chair of Applied Ventures and Dr. Melissa Grupen-Shemansky, CTO of SEMI, and moderated by Saifi Usmani, SEMI Vice President of Sustainability. These executives will discuss the role of startups in semiconductor sustainability, along with a variety of related topics. The finalist pitches are scheduled from 2:00 to 4:40 p.m., with each presenter given a 10-minute time slot.Investors are welcome to attend the session at SEMICON West and to register their interest here to learn more about the 2026 program.2025 S3 FinalistsActasys Inc.Brooklyn, NY, USA Actasys has developed a precision cooling solution designed for thermal bottlenecks in semiconductor-driven systems such as networking cards (NICs), DPUs, switches, and optical transceivers. Instead of cooling entire racks or server rooms ActaJet™ targets localized hotspots at the device level, delivering scalable, high-efficiency airflow through a compact, adaptive, and electronically controlled actuator system. AlixLabs ABLund, Sweden AlixLabs AB is developing a disruptive semiconductor manufacturing technology based on Atomic Layer Pitch Splitting (APS). It enables cost-effective and environmentally sustainable scaling of transistor architectures by doubling pattern density without requiring advanced lithography. The core product includes both the APS process and customized etching equipment that integrates into existing semiconductor fab workflows, reducing complexity, cost, and environmental impact.AllonniaBoston, MA, USA Allonnia delivers on-site PFAS treatment with SAFF® (Surface Active Foam Fractionation), a modular system that uses air to naturally separate long- and short-chain PFAS from water. SAFF concentrates PFAS up to 100,000x, minimizing waste and enabling cost-effective, closed-loop management alongside any destruction technology. This plug-and-play solution helps fabs meet strict regulations while advancing sustainability goals with low OPEX and seamless integration into existing operations.AlsemySeoul, South Korea Alsemy is building an AI-powered platform that bridges Manufacturing Execution Systems (MES) and EDA domains enabling fabless engineers to reflect manufacturing data characteristics in their chip designs, while process engineers can make data-driven decisions to optimize manufacturing processes for maximum chip performance. By connecting these traditionally siloed areas, a feedback loop is created to drive efficiency and innovation across the semiconductor value chain.Arieca IncPittsburgh, PA, USA Arieca's adaptable Liquid Metal Embedded Elastomer (LMEE) technology, which blends liquid metal and polymer, delivers both thermal performance and mechanical reliability. LMEEs are a cost-effective, dispensable emulsion that is compatible with existing high volume manufacturing tools and allows for low pressure spreading and excellent wetting. CuspAICambridge, UK CuspAI is building an engine that combines Gen AI models, virtual twins, and active learning pipelines for simulation to develop sustainable materials solutions that address critical environmental challenges, including, environmentally-friendly etching reagents, specialized sorbents for emissions capture, and novel catalysts for manufacturing waste remediation. The engine has already proven successful in designing metal-organic frameworks (MOFs) for carbon capture and PFAS removal from water.FlexiramicsEnshede, The Netherlands Flexiramics® is a breakthrough flexible, 100% ceramic fiber material designed as a drop-in replacement for glass fiber in PCBs. By enhancing thermal conductivity and reducing signal loss, it enables semiconductor manufacturers to build faster, cooler, and more reliable devices. This translates into higher performance, longer lifetimes, and greater efficiency for next-generation chips and advanced electronic systems.icspiKitchener, ON, Canada icspi has developed the microAFM, a scalable atomic force microscope (AFM) on a 1 mm^2 MEMS scan head, 1,000,000x smaller than conventional AFMs. MicroAFM technology enables parallel arrays of thousands of devices for sub-nanometer metrology and inspection with unprecedented throughput, accelerating time-to-yield and reducing scrap.Mixx Technologies, Inc.San Jose, CA, USA Mixx Technologies is a deep-tech startup building next-generation optical interconnect solutions to deliver non-blocking, energy-efficient data movement. The advanced 3DS platform enables petabit level end-to-end connectivity for AI workloads resulting in sustainable, efficient, and cost-effective scaling. The 3DS platform comprised of the engine, package and system, enables seamless deployment of the optical IO chiplet.Point2 TechnologySan Jose, CA, USA Point2 designs and manufactures mixed-signal interconnect SoCs for terabit data transmission, to overcome the barriers of copper and optical cabling to accelerate AI interconnect in GPU cluster scale-up. e-Tube technology uses an RF Transmitter SoC to convert data from the electrical to the RF domain for transmission over plastic waveguides, with the RF Receiver SoC converting the data from the RF domain back to the electrical domain.PROUDLausanne, Switzerland PROUD's patented diamond-layer technology with the highest heat dissipation capacity ( 1000 W/m.K) of any existing material, deposited on chips, allows a direct upgrade in heat extraction, power output and efficiency.SKYRE, Inc.East Hartford, MA, USA SKYRE, Inc. is a pioneer in hydrogen technology, developing innovative solutions to support a clean energy future. From hydrogen recycling, purification and compression, to sustainable energy systems, we deliver environmentally responsible innovations in high-efficiency, zero-waste hydrogen and carbon transformation technologies—cutting costs, boosting industrial productivity, and reducing environmental impact.SyentaSydney, Australia Syenta has developed LEM - Localized Electrochemical Modelling - a process for depositing metal patterns using a local electrochemical process. The pattern is created on a stamp, which then prints the pattern on the substrate in an additive process.Vionano Innovations IncSt. Paul, MN, USA VioNano Innovations is building a patterning platform to enable advanced feature scaling using self-assembling polymer brush materials. The system enables polymers over 193 nm DUV lithography patterns to double feature density without requiring ALD/CVD or etch steps. The result is a low-energy, high-resolution process for sub-20 nm features using existing infrastructure.XLYNX MaterialsVictoria, BC, Canada XLYNX designs and manufactures a revolutionary family of polymer crosslinkers. These reagents are uniquely able to cure virtually ANY aliphatic polymer, by harnessing high-yielding insertions to carbon-hydrogen bonds. Curing can be triggered thermally (at temperatures as low as 80°C) or photochemically (using either UV or blue light). Heidi Hoffman is Senior Director, Marketing Sustainability at SEMI. Saifi Usmani is VP, Global Industry Sustainability Programs at SEMI.

This year, the Women in Semiconductor (WiS) program takes a huge step growing nationally — hosting events in New York, Michigan, Ohio, California, and Arizona. Managed by the SEMI Foundation, the WiS program aims to highlight women’s contributions and leadership in the semiconductor sector and actively address the gender gap to support inclusive workplaces.Over the years, WiS has shifted from an abstract discussion to actionable strategies—focusing on skills like negotiation, strategic decision-making, storytelling, and career advancement. WiS also promotes allyship, inviting and including men to participate as advocates and supporters of women in the industry.Building on the program’s strong momentum, this year highlights the initiative’s growth and impact through expansion across multiple regions – focusing on the theme “Empowerment in Action: Real Strategies for Women’s Success” dedicated toward impactful, actionable programming.The first 2025 WiS program was held in Albany, NY, in conjunction with ASMC on May 8. New WiS programs are scheduled in the following locations:Ann Arbor, Michigan on September 16, 2025Willoughby, Ohio (date to be announced)San Jose, CA on November 20, 2025Phoenix, Arizona on December 11, 2025The WiS is supported by grants from the Kellogg Foundation and the David Lucile Packard Foundation. The programming is also aligned with SEMI Foundation’s Chips Childcare program, which supports childcare-access solutions to strengthen workforce participation—particularly for parents and caregivers. Learn more in our blog: Affordable, Accessible, and Quality Childcare: A Critical Workforce Development Strategy for the Semiconductor Industry.The WiS initiative has evolved into a powerful platform that blends strategic programming, mentorship, allyship, regionally accessible events, and support systems like childcare advocacy. It’s an inspiring example of how consistent focus and innovation can build meaningful change over nearly a decade. If you’re interested in getting involved, contact Bia Hamed at [email protected]. Bia Hamed, Ph.D., is Program Manager for Global Education Initiatives at the SEMI Foundation, focusing on educational programming that supports workforce pipeline building nationally and internationally.

As the Department of Commerce explores options to adjust patent fees, these changes will have important implications for the semiconductor industry, where thousands of patents are filed each year to protect groundbreaking technologies. At SEMI, we understand the complexity of getting this right for our member companies. The fee proposal is not only about rates, but also about how fees are structured, applied across different types of filers, and administered in practice. Designing a system that is fair and workable is a significant challenge and one that requires close collaboration between government and industry. The SEMI Global Advocacy team is consistently engaged with the Trump Administration and Congress as a resource. We want to ensure the unique needs of the semiconductor sector are understood and that any adjustments to the fee schedule strengthen U.S. innovation without creating unintended barriers. By working together, SEMI members with U.S. operations can help shape an approach that supports the U.S. Patent and Trademark Office's mission and U.S. competitiveness. Next Steps: SEMI will continue to provide technical insight from across our membership as this process develops and looks forward to partnering with policymakers. We will also share updates as information on new patent fees become available beyond the initial reporting by the Wall Street Journal and other news outlets.Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Scarlett Bickerton, Manager, Federal State Affairs at SEMI.

John Kibarian, CEO and co-founder of PDF Solutions and a member of the ESD Alliance (ESDA) Governing Council, will deliver a keynote during the CEO Summit at SEMICON West in October titled, “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms.” He recently shared with me a summary of what his talk will cover and his perspective on why collaboration is the key to growing the semiconductor industry to $1 trillion and how we will get there.Smith: What is the major industry evolution or dynamic that's making collaboration essential today?Kibarian: The semiconductor industry has dramatically evolved from a simple, linear process to a complex, collaborative ecosystem. Previously, everything happened at the wafer fab. Testing occurred at wafer sort, package yields were high, final testing was straightforward, and products were shipped. Collaboration was mainly between foundries and fabless customers, intensive during early qualification and test chip stages, then evolved to routine yield monitoring once production stabilized.Today's advanced packaging puts multiple chiplets into single packages, creating an explosion of test insertion points. This has driven up both test complexity and costs significantly. Front-end fabs now house the most complex machines, while test and assembly facilities, once relatively simple, now feature sophisticated system-level testers with integrated robotics. Assembly tools have become highly complex, with die-attach processes requiring increasingly tight tolerances. Success now requires collaboration across the entire chain, from system companies to equipment vendors, both for new product launches and ongoing production maintenance.Companies are adopting AI and machine learning (ML) to manage these complex production flows, whether for testing or equipment control. This demands even broader collaboration since AI requires combining data from multiple sources across foundries, fabless companies, OSATs, equipment vendors, and more, data that no single entity controls. What was once a straightforward handoff between two parties has become an intricate web of interdependent relationships requiring continuous coordination.Smith: Chiplets and chiplet-based architecture is in the news and seems to be a key solution or practical solution in response to the slowing down of Moore's Law. This demands incredible levels of collaboration and coordination across the whole value chain. Is this doable at scale where it starts to move into the mainstream?Kibarian: The semiconductor industry will need unprecedented collaboration to make chiplet manufacturing work at scale. But this can be done! Consider EUV lithography: Initially expected during the 65nm generation, it took years longer than anticipated despite being an incredibly complex technology. Extraordinary engineering was needed but it also required extensive collaboration between ASML, suppliers, customers, and the broader fabless community.If the industry achieved this level of coordination for EUV, it can do the same for chiplets. However, chiplet manufacturing will require even greater collaboration as more companies will build systems using chiplets from multiple suppliers.Today's chiplet-based systems typically source all components from one manufacturer, making standards like UCIe less critical since companies control their entire supply chain. This will change as companies increasingly use third-party components for cost-effectiveness.More and more, we will see systems using components from multiple players to get to market more cost-effectively. Consequently, future production flows will be significantly more complex, requiring coordination of substrates and base dies, third-party dies and interposers, OSAT and specialized testers with specific configurations.This orchestration must work not just for initial bring-up but for the ongoing production as well, and when reconfiguring chiplet combinations for different products, all requiring rapid, automated responses.All of that must be automated for quick reaction. Considering the complexity of the manufacturing flow, people will want to apply AI/ML to anticipate what is going on in each individual product built.Manual oversight of every chip and package during manufacturing isn't feasible at scale. Automated AI agents must handle this monitoring and quality control. Expanding this automation will require close collaboration between the manufacturing entity and engineering teams at the product companies.This will also require a different level of alignment and orchestration across all the software packages managing this complex multi-company process. The financial enterprise resource planning (ERP) systems know where material is going, what the demand is, and what the forecasts are. While separately, the manufacturing execution systems needs to know which tools are going to be available when. Most often, these manufacturing systems operate in factories the product company doesn't own. The product company’s PLM systems control the bill of materials and test flows, but these tests will be conducted at the OSAT requiring complex coordination between the software systems of multiple companies controlling different process domains. This orchestration spans organizational boundaries and must be able to take data from upstream test results and make decisions on what tests to run downstream. This is required to get the right chiplets put together into a package in an efficient manner within a short cycle time and not require a Formula 1 pit team to keep everything running.Smith: The volume of data is staggering, especially now with design data. What will it take to enable this vision, at scale, where everything's connected? Kibarian: It’s a marriage of the human establishing the bounding box within which the systems operate that employ agents to do a lot of the work on a day-to-day or hour-by-hour basis. A good example is how manufacturing execution systems (MES) connect to ERP systems to share data. When a company sets up an orchestration, it creates rules that govern how information flows between systems. These rules tell the ERP system: "To calculate costs for each process step, here's the recipe information you should use."Once these rules are in place, they work like guidelines that control daily operations. An AI agent automatically creates insights based on actual data collected from the MES and moves data between systems according to these rules. The ERP AI agent will use this data to spot when costs are rising and send alerts, to notice when production yields drop, to calculate what lower yields mean for costs, and will take action to fix problems.This same process happens between equipment suppliers and manufacturing facilities. They share data automatically based on pre-set rules, and AI helps identify issues and take corrective action. Fabs determine who can access which machines and when, what types of data can be transmitted and through which channels, and how frequently these transmissions occur. When new software or AI models are introduced to run equipment, the systems specify what virus scanning and security checks must be completed before installation.Human operators primarily configure these control systems by determining the most effective collaboration protocols. However, the day-to-day execution is handled by automated agents due to the enormous scale involved, both in terms of data volume and the sheer number of transactions that occur continuously throughout operations.A human will not go through and review that data. I'll give two examples of this. One outside of our industry and one in our industry. At our 2019 user conference, board member Marco Iansiti, a Harvard Business School professor, shared insights from his book on AI in business. He compared traditional banks with Ant Bank, Alibaba's banking arm, which was experiencing explosive growth before Chinese government intervention.Ant's AI wasn't particularly sophisticated, but its process was revolutionary. While traditional banks require customers to fill out loan applications that then go to human loan officers for review, Ant's system would automatically scrape the internet and social media to verify applicant information. Within seconds, an algorithm would approve or deny the loan.The crucial difference is that Ant could scale exponentially because its only constraint was computing power. Traditional banks need to hire more loan officers to double their business, a human bottleneck that limits growth.I invited him to speak because I believed in this principle six years ago, and I'm even more convinced now.For the semiconductor industry, to build a trillion-dollar industry with complex, integrated systems, we need to minimize human intervention in data intensive processes. Despite the trust issues between stakeholders in our sector, collaboration remains essential. The solution requires establishing systematic principles that allow AI agents to operate autonomously. This is a way forward to achieving exponential growth.The Ant Bank example perfectly illustrates what our industry needs. At PDF, we believe this approach is crucial for industry advancement. Consider this: We manage petabytes of data, yet humans only examine 5-10% of it. This shows AI's potential to handle the vast majority of operations without human oversight.The reality is that our customers build millions of chips a week, billions a year. They cannot look at every dataset. Algorithms can, AI can. We launched a product called Guided Analytics last year. An engineer spoke about it during our user group last year. Her company has a couple of thousand products. Her group could not keep track of them every day, but Guided Analytics could. When her group came in the morning, the daily report noted 90% of the chips were fine or alerts pointed to where issues are. It's a simple AI bot crawling over data and identifying where the root cause seems to be.Our industry will require more agents to scale. Those agents will span the industry, and yet we as humans need to set up the governing principles under which they can operate. That's how we're going to deal with the massive amounts of design and manufacturing data to get the velocity the industry will need, and to benefit from the AI that we create for our businesses.Notes: Kibarian’s keynote, “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms” is scheduled for Wednesday, October 8, at 10:20 a.m.SEMICON West adds design to its program with “The Convergence of Semiconductor Manufacturing and Design” to highlight the collaboration between semiconductor manufacturers and chip design teams to bring advanced systems to market. The three-hour session will be held Tuesday, October 7, from 1 p.m. until 4 p.m. Learn more about the design program in our latest blog. SEMICON West 2025 will be held in Phoenix, Arizona from October 7-at the Phoenix Convention Center. SEMICON West’s homepage has links to the full program, including more details about “The Convergence of Semiconductor Manufacturing and Design,” special features, sponsor and exhibits. Registration is open. About John KibarianJohn K. Kibarian is President, Chief Executive Officer and Co-Founder of PDF Solutions. He has served as President since 1991 and CEO since 2000. Dr. Kibarian received a Bachelor of Science degree in Electrical Engineering, a Master of Science and PhD degrees in Engineering Computer Science from Carnegie Mellon University.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

This year’s SEMICON West has new dates, a new location in a new city and a new addition to the program—design! “The Convergence of Semiconductor Manufacturing and Design” will highlight the collaboration between semiconductor manufacturers and chip design teams to bring advanced systems to market. The three-hour session during SEMICON West will be held Tuesday, October 7, from 1-4 p.m. at the Phoenix Convention Center in Phoenix, Arizona.Five 20-minute presentations will describe successful collaborations and address challenges and opportunities about design and manufacturing security, long-term reliability, system performance issues, and modeling and verification that encompass the entire system. Attendees can expect to learn about the key drivers behind the need for collaboration that range from heterogeneous integration to advanced packaging technologies and applications such as automotive and medical.Session moderators are Ming Zhang, PhD, Vice President of Fabless Solutions of PDF Solutions, and me. “As design and manufacturing complexity continues to grow, driven by applications like AI, it is becoming increasingly difficult to account for every manufacturing variation during design and at sign-off or to fully anticipate the entire design space at chip and system levels during manufacturing technology development,” said Zhang. “Achieving tighter integration between design and manufacturing through broader and deeper data and methodology collaboration will be critical to improving predictability, accelerating time to market and enabling the next generation of semiconductor innovation.”It’s within this context that we selected the presenters who include:“Revolutionizing Silicon to Systems Design: Unlocking the Future with 2.5D and 3D Multi-Die Innovations” by Sutirtha Kabir of Synopsys.“Manufacturing to Development to Manufacturing for Circular Collaboration Leveraging AI and Other EDA Advances” with David Kelf from Breker Verification Systems.“Bridging the Silicon Divide: Converging Chip Design and Manufacturing in the Era of High Integration” from Lu Dai at Qualcomm Technologies.“3D and Chiplets Driving Moore’s Law into the Future” with Joe Kwan of Siemens EDA.“Multiphysics Multiscale Challenges and Solutions for 3D Heterogenous Integration” by Sudarshan Mallu from Ansys, part of Synopsys.The program concludes with a panel moderated by Zhang titled “The Convergence of Semiconductor Manufacturing and Design” and features the session presenters.Join us to learn how the semiconductor manufacturing and design communities are collaborating to deliver advanced systems based on chiplets and rapidly emerging packaging technologies including 2.5D and 3D ICs and MCMs. Audience participation will be encouraged.Also of interest to attendees is a SEMICON West keynote from John Kibarian, CEO, President and Co-Founder of PDF Solutions who is also co-chair of SEMI’s ESD Alliance Governing Council. Kibarian will address “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms” during the CEO Summit keynotes on Wednesday, October 8 at 10:20 a.m.SEMICON West 2025 makes its debut in Phoenix, October 7-9 at the Phoenix Convention Center. This milestone event gathers global leaders across the microelectronics supply chain to explore transformative technologies, develop the future workforce and drive strategic collaboration. Moving SEMICON West to Phoenix highlights Arizona as a key hub for innovation and industry growth. Visit the SEMICON West homepage for more details on full program, including “The Convergence of Semiconductor Manufacturing and Design” session, special features, sponsors and exhibits. Registration is open. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

SEMI members span the entire semiconductor manufacturing supply chain, representing diverse industry segments, product offerings, geographic regions, company sizes, and ownership types. The SEMI Member Directory serves as a key resource that showcases companies across the microelectronics value chain while helping to amplify their brands. We’re excited to announce recent enhancements to our member directory that include a refreshed design, improved search functionality, and more up-to-date company information.WHAT’S NEWClean Look FeelDefault “tile view” display of member companiesCompany profile pages with English and optional local-language contentAbility to display up to 48 companies per page viewSmart Search Functionality Searches scan all company profile descriptions, keywords, and location detailsSearches support all languagesIndustry-focused results limited to the semiconductor manufacturing supply chainMember Company Access Primary member contact can instantly update their company’s directory information, including:Business overviewCompany logo uploadAdditional search keywordsWHY IT MATTERSThe Member Directory averages 15,000-20,000 active viewers each month, providing a powerful platform to boost your company’s visibility within the industry. Combined with SEMI’s reputation and reach, it’s an effective way to be seen by the right audience.LOOKING AHEADWe’re not done yet. SEMI will continue to improve and enhance the directory with additional upgrades in the coming months. Check out the new directory and see the latest improvements. If your organization isn’t yet among our 3,000+ member companies, now is the perfect time to join our global community. Learn more by submitting a membership inquiry form or contact a regional office.Eric Thoe is Senior Director, Member Services at SEMI.

The semiconductor industry is grappling with a critical talent shortage, both globally and within the United States. At the same time, the workplace landscape for high school and college graduates is changing. These dual pressures present an opportunity: to cultivate early career awareness by introducing K–12 students to dynamic, real-world learning experiences that open their eyes to emerging industries—like semiconductors—and the meaningful roles they could play in them.Investing in this early exposure strengthens the long-term talent pipeline for the semiconductor industry and prepares students to meet the demands of a rapidly evolving workforce. However, realizing this vision requires intentional, cross-sector collaboration among educators, industry leaders, workforce boards, and policymakers.One example of this type of collaboration is the ChipWorks Series in Idaho. Boise State University partnered with Micron, the Idaho Workforce Development Council, and the Idaho Digital Learning Alliance to design, develop, and launch the learning experience for middle and high school students in 2024. The ChipWorks Series consists of three courses: Chip, Chip, Hooray!; Introduction to Electrical and Computer Engineering; and Materials Science and Engineering. With the first course launching in Fall 2024, the program has already reached over 220 learners across Idaho – and it’s just getting started. Camille Platts-McPharlin is the Project Manager at the Microelectronics Education and Research Center helping Boise State prepare to expand their programming to a national audience in 2025.The origin of the ChipWorks Series began through a grant with the Idaho Workforce Development Council. “The Council and Boise State University saw an opportunity to address the growing workforce gap by building a pipeline that begins in middle school and goes through adulthood,” said Platts-McPharlin. Development began in 2023 and was shaped by more than 300 voices from industry, academia, and K–12 education. This cross-sector group of stakeholders worked collaboratively to ensure that the lessons were responsive to real-world industry needs and compatible with classroom delivery best practices. Furthermore, the courses are aligned with State and National learning standards as well as ABET standards. Overcoming logistics challenges around open-source resources and existing structures in formal education led to two of the programs being dual credit, setting high school students up for early success in post-secondary. There has been an enthusiastic response from learners across Idaho, and more learners are expected to engage this year, as the third and final course is launched in the fall. Students enroll at their home school, have the support of local teachers, and receive online instruction synchronously from a dedicated teacher through the Idaho Digital Learning Alliance. This model enables a broader group of learners to access the training, regardless of educator understanding of the content. Students learning ChipWorks Series lessons at Micron Chip Camp.The ChipWorks Series is now expanding its reach beyond Idaho. In collaboration with Micron, Platts-McPharlin and the MERC team are working to bring the courses to students in New York. Educators from Syracuse and surrounding districts participated in a week-long professional development event to learn the curriculum and begin the work of bringing it into their local school districts. Teacher training for educators from Idaho and New York. Platts-McPharlin offered words of wisdom for other educators, training providers, or partners who are trying to create industry awareness opportunities earlier in the learning journey. “The key to success is listening closely to stakeholders and balancing the various perspectives. This will result in a quality product,” she said. Her other suggestion: trust the process. While it was challenging to build entirely new programs, the impact it is having on students, their teachers and their families to make them aware of their potential is immense. Programs like ChipWorks offer a powerful solution to the semiconductor industry’s workforce crisis, but they cannot stand alone. For sustained progress, industry leaders, workforce development councils, and educational institutions must work together to co-design scalable, inclusive solutions. This means sharing expertise, investing in infrastructure, and championing long-term talent development—starting in the earliest years of education. For more information on the ChipWorks Series, or to learn how to bring it to your students, please contact Camille Platts-McPharlin: [email protected]. To learn about what the SEMI Foundation is doing to bring together cross-sectoral groups for similar projects, contact Anissa Hamdon-Morison: [email protected] Hamdon-Morison is Training and Curriculum Manager at SEMI Foundation.

The semiconductor industry faces an unprecedented paradox: AI demand is booming, fab investments are rising, yet wafer shipments remain stubbornly flat. What's driving this disconnect, and when will it break?As of mid-2025, the global silicon wafer market appears calm on the surface, but underlying structural tensions are quietly mounting. The demand for AI semiconductors remains resilient, and certain high-value supply chains continue to operate near capacity. Yet wafer shipments have shown little sign of meaningful recovery—a divergence that raises questions about the conventional supply-demand playbook.SEMI's latest Silicon Wafer Market Monitor Report begins with a structural hypothesis: that the current market dynamics cannot be explained solely by weak demand or delayed orders. Instead, we propose that the demand pattern of fab operations itself has fundamentally changed.The Hidden Constraint: Time ExtensionOne critical metric has emerged as a structural bottleneck—fab cycle time, or the average duration for a wafer to complete its full process flow. Our quantitative analysis reveals that since 2020, fab cycle times have grown at a compound annual growth rate of 14.8%. This represents a fundamental deceleration in fab throughput, meaning that even with the same number of tools and consistent utilization rates, the volume of wafers that can be processed is now structurally constrained.Why is this happening? Rising process complexity, increased equipment density, and tighter quality control requirements are absorbing more capital per wafer while paradoxically slowing production. Equipment spending per wafer area has surged over 150% since 2020, yet this investment translates into longer processing times rather than higher throughput.The High Bandwidth Memory (HBM) Economic ThresholdSimultaneously, the market is approaching a new inflection point driven by the rapid rise of HBM. HBM wafers consume over three times more wafer area per bit compared to standard DRAM, creating potentially significant wafer demand. However, HBM currently accounts for just 16% of total memory revenue—still below a critical economic threshold.Our analysis identifies that when HBM reaches 25% of total memory revenue, the trade ratio rises to 1.5. This is the structural breakeven point where CapEx per wafer for HBM-dedicated lines aligns with standard DRAM economics. At this threshold, memory makers gain clear incentives to expand wafer input, and customers become more willing to pay premium prices.The Quantitative FrameworkInstead of relying on conventional forecasts, we model the interaction of four critical variables—HBM penetration, DRAM bit growth, fab utilization, and cycle time—using a quantitative simulation framework. Under current conditions (16% HBM revenue share, 15% annual bit growth, 95% fab utilization, and 14.8% cycle time increase), wafer input would need to increase by 23.9% annually to meet projected demand.Yet no fab is scaling wafer input to that extent today. This suggests the market isn't demand-constrained but operating within a conditionally responsive system—one that won't activate until key thresholds align.Beyond Economics: Technical and Operational ReadinessThe slow pace of HBM expansion isn't solely about investment timing. Technical constraints including low yields, delayed customer qualification, and process stabilization challenges also play critical roles. These preconditions—investment readiness, yield optimization, and qualification completion—haven't yet aligned, keeping the market in strategic latency despite robust underlying demand.Additional factors compound this delay. Backend bottlenecks in Chip-on-Wafer-on-Substrate (CoWoS) packaging are causing semi-finished wafers to accumulate as inventory, constraining upstream wafer input. At the fab level, companies prioritize efficiency gains through process conversions over new construction. Meanwhile, macroeconomic uncertainty, geopolitical tensions, and foreign exchange volatility continue suppressing capital execution.The Three-Tier Response ModelThis structural shift creates a three-tier demand response across the supply chain:Wafer demand: Conditionally responsive, awaiting economic threshold alignmentEquipment investment: Process-transition driven, already responding to complexity increasesMaterials demand: Directly tied to cycle time extensions, with potential for early bottlenecksFor certain process-critical materials like EUV photoresists and TSV chemicals, supply constraints may emerge even before wafer input fully ramps, preceding equipment expansion.Strategic ImplicationsFor industry stakeholders, this analysis suggests three key actions: wafer suppliers should prepare scenario-based capacity plans around the 25% HBM threshold; equipment makers should anticipate process-transition driven demand regardless of current wafer volumes; and materials suppliers should prepare for potential bottlenecks as extended cycle times increase consumption per wafer.Crucially, the current stagnation shouldn't be interpreted as structural decline. Rather, the market exists in a state of strategic readiness, with key conditions not yet aligned. Once they are, wafer demand will likely respond nonlinearly—and momentum is already building in that direction.The structural inflection point (≈25% HBM penetration) and cycle time increase (+14.8%) serve as forward-looking indicators not just for wafer producers, but for the entire upstream supply chain. The question isn't whether this inflection will occur, but when. Companies that understand these structural dynamics and prepare accordingly will be best positioned to capitalize on the nonlinear demand response when it arrives.These key insights are from the market update section of the Q2 2025 Silicon Wafer Market Monitor Report. This quarter's analysis models structural inflection points using scenario-based projections across nine core charts and tables, offering data-driven perspective on the industry's readiness for the next demand shift. Download your free sample report today.For more information on the report or to subscribe, please contact the SEMI Market Intelligence Team at [email protected]. Details on the complete SEMI market data portfolio are available at our Market Intelligence website. Sungho Yoon is a Principal Analyst in the Silicon Wafer Market Research at SEMI Market Intelligence.