Lu Dai, Vice President of Technical Standards at Qualcomm, presented “Converging Chip Design and Manufacturing in the Era of High Integration” at SEMICON West in October 2025, offering an insightful look at how design and manufacturing are collaborating effectively.I had an opportunity to talk at length with Dai and asked him to define collaboration. His thoughtful answers, perspective on industry trends and what it will take for a seamless automated flow between design and manufacturing made for a great discussion.In addition to his role at Qualcomm, Dai, who lives in San Diego, is Chairman of Accellera Systems Initiative, Chairman of RISC-V International and Director of Silicon Integration Initiative (Si2).Smith: Qualcomm is a fabless company. How do you define what collaboration is between design and manufacturing? Dai: When we talk about design and manufacturing collaboration, we need to consider how a design is optimized for a certain manufacturing process. For example, will an advanced manufacturing capability help designers simplify designs or allow them to bypass traditional actions?I compare it to the way software was optimized to hardware because of hardware limitations. We had to make sure the C code was compact and that the variable types we specified wouldn’t waste memory. We also had to write the code in a certain sequence to speed up the execution of the code. As hardware capability grows, we can write dirty code and it isn’t as critical. We understand the manufacturing process capability. That allows us to be more flexible about where to focus the chip design effort based on needs for power, performance, area, and schedule. We want to make sure we know the chip size and how big the silicon space is for certain features. For example, low power is often a key feature of today's designs. As manufacturing process nodes improve, power goes down and area shrinks. We can therefore focus more on optimizing performance.This is the kind of collaboration we use with foundries. Libraries need to be optimized for the design and tweaked for yield. This collaboration is critical for foundries pushing leading-edge nodes in the design house—they have to work closely with the design team.Smith: And how about collaboration with packaging suppliers? Dai: I'm not a packaging expert. Traditionally, packaging is one of the important steps and even more so because of the push toward the use of chiplets. Packaging becomes really important when dealing with multi-chiplet types of design. Traditionally, IP vendors sell a license to use the register transfer level (RTL) code, which is subject to IP theft. With a chiplet approach, they sell a netlist, which often becomes a hard coded chip as a bundled service instead of a single IP. The subsystem sales approach makes more money, creating another opportunity or a new landscape. SoC companies may get into the IP business and conversely, IP companies are getting into the SoC business by selling the bundled subsystem. Smith: The margins are getting blurred. It sounds like there is collaboration and it’s between designers, but also the foundries, process and the packaging.Dai: And partially between EDA tools because both the design side and the manufacturing side are speaking two different languages. EDA is somewhere in between, helping the translation.Smith: What are the trends and challenges that make it hard or even prevent a fully integrated flow?Dai: The extremely high costs of doing the implementation for an advanced node, especially for the first tape out. If we are the first to use the newest node, we know there is a tremendous benefit in the long run. But we are also the pioneers that have to work out the tough challenges. Few companies have the technical capability and deep financial resources to be the pioneers for a new process node. We’re starting to see high-flying semiconductor companies use leading-edge nodes. On the design side, they are challenged and trying to run faster by adopting a newer node. Cost is probably the biggest challenge for this collaboration. If their margins get challenged or they need to be a little bit more careful, they adapt by becoming fast followers.Another challenge comes from more specialized designs. There has been a long period where general-purpose chips are used for many different applications. But, we are now seeing designers increasingly focus on more specialized chips with custom designs.Custom IP and ASICs are becoming trendy. Designers are trying to figure out how to make a general baseline and then differentiate on certain IP and the best possible manufacturing process for the application. Doing a custom chip on an advanced node is quite expensive. We may be challenged if we don’t have sufficient data to clean up a process because every chip and process combination is unique. Lessons learned from this chip may or may not apply to everyone, while a general-purpose design tends to be a good baseline for lessons learned.Smith: How do you envision an integrated automated flow between design and manufacturing? Dai: In today's environment, we would like an RTL design to be fully portable to any kind of manufacturing process or foundry. Based on our architectural and business, we could then pick and choose the fab and the process. How do we port a design into a new process? That's difficult because we need to consider special constraints required by the new process that didn’t apply to the previous process. There's also the reverse case for porting a new design into an old process.Let’s say we have a chip designed for a 3-nanometer process and we want to port it back to a 28-nanometer process. Why would we want to do this? Imagine a COVID type of situation—a supply chain constraint and/or a geopolitical flare up with no access to the advanced fab, but an older local fab is still available. In this case, we need the chip for the feature it provides. Perhaps a car needs that chip and it was designed to be produced in a three-nanometer process but is suddenly unavailable. A 28-nanometer chip that runs at half of the speed might do the job for a few years. Unfortunately, this is somewhat wishful thinking because of the challenge of the flow. We didn’t think about it but we have to do it now and need to consider whether we have sufficient time to work out the challenges.Smith: How do you make that decision for making chiplets? Dai: Porting to another process is not a small job. It's labor intensive going from a same design in one process to another process.The project lead presents a process porting non-recurring engineering (NRE) cost budget to management. The questions span resources and time needed that boil down to how much money will need to be invested to achieve the porting. It should be simple. It’s not. It’s a lot of work.For many companies, the strategy is to offload the porting to a low-cost geographical team with a cheaper NRE that matches management expectations for the costs of process porting. History often shows that the company is not reducing that much time and manpower by offloading the porting. Smith: What about the EDA tool side? Is there typically a team from the EDA vendor? Dai: For advanced nodes, we involve the EDA and in-house EDA experts when certain parts of our design don't work out as expected.Back-end tools need experts involved in the debugging. And if we don't have an in-house expert, we need our EDA vendors to send engineers to work on the project.Smith: I have a generic question about AI. We talked about reporting. Where would it fit in collaboration?Dai: Sooner or later, we're going to be asked for a proper supply chain tracking or hardware bill of materials (BOM). Conceptually easy, but difficult in practice because it goes from logic design to physical design all the way to manufacturing. How do we carry that type of information through each step with EDA tool providers and manufacturing equipment providers? Their credentials need to be registered and they can’t alter any of the existing flow credentials.Supply chain tracking can ensure that if there's any kind of natural disaster or geopolitical issues, the hardware BOM is properly categorized, and the chip can be made. Security is another reason for supply chain tracking. Collaboration between design and manufacturing is important because once a netlist is sent to the foundry, our job is to make sure it is done correctly. We wait for our silicon to come back. Then we do testing. But during manufacturing, the chip comes back and it doesn't work. How do we know if somebody tampered with it? Supply chain tracking could help.Smith: How can you know that someone didn’t tamper with a chip design after it was handed off to manufacturing? This could cause big issues for end markets such as medical, automotive, defense and aerospace applications.Dai: The solution is EDA heavy because EDA tooling can help on the traceability at every step. It’s all automated through some kind of tool. If we need to have a proper format, we need to have proper encryption. And we know when we use this tool to run it, we check to show we are using the real tool not a hacked version that doesn't have the security credentials.Smith: Will this drive supply chain tracking or drive new standards?Dai: I hope so. Once upon a time, there was an initiative by the Department of Defense to track the supply chain. It was a mandate and no one liked it. It’s much better for the industry to proactively come up with a standard for a global economy.A mandate tends to come from one government. It may be a good mandate if we do business only within one country or within a small region. What if we have to do business with another government that may not like our mandate? Say a certain part of our design stage is done in a different country and we need this level of detail. Who's doing the work and what's the tool version? Per local government rule they may not be willing to give the information to us. This might be sufficient. We don't know the details of the risk, but we know there is a risk. We could simply add to our tracking that a portion of design is done in a foreign country with foreign EDA. It's important to have an industry standard and an international standard so that we can procure our tools and the services around the world instead of being limited.Smith: How can we encourage companies and people to want to cooperate and sign on to a project like this?Dai: With lessons learned, we can go deeper. Maybe the first level is a meeting in the U.S. About Lu DaiLu Dai is Vice President of Technical Standards at Qualcomm Technologies, Inc., spearheading semiconductor standards efforts and relationships with industry organizations. Lu was previously Senior Director of Engineering and led Qualcomm’s SoC design verification team and front-end methodologies and initiatives. He was also the Design Verification Lead responsible for multiple generations of premium tier platforms at Qualcomm, including the Snapdragon 8 series and products that power the Mars Perseverance rover and Ingenuity helicopter. Prior to Qualcomm, Lu was the Design Verification Lead for Cisco’s Gigabit Switching Business Unit where he worked on multiple generations of Cat4k ASICs. Lu is the current Chair of Accellera, Chairman of the RISC-V International Board of Directors and serves on the Board of Directors at Si2. Lu holds a Master of Science degree in Electrical Engineering from Cornell, and a Bachelor of Science in Electrical Engineering and Computer Science from UC Berkeley.Robert (Bob) Smith is an independent consultant who has been involved directly in multiple roles in the EDA industry over the past 38 years. His career experience spans analog engineering, marketing, sales, business and strategy development and others including numerous c-suite roles. He holds a Master of Science degree in Electrical Engineering from Stanford University.
