Aki Fujimura has been at the forefront of chip design innovations from the beginning of his career and his technology leadership continues today. He serves as Chairman and CEO of D2S, co-founder of the eBeam Initiative, President of BACUS, and a Governing Council member of the ESD Alliance, a SEMI Technology Community. At Tangent (now Cadence), Fujimura and Steve Teig (a chip designer for the last 20 years and now Vice President and Distinguished Engineer at Amazon) built the first commercial over-the-cell routing system dedicated to fully synchronous designs with timing assurance and automated test-scan insertion. Fujimura and Tom Kronmiller developed LEF/DEF for efficient representation of Manhattan routing, both used as standards in the automated place and route (P R) flow to this day. He again teamed with Teig and Kronmiller to develop the X Architecture, an interconnect architecture based on the pervasive use of 45o diagonal routing. I was thinking about his background as I called him to chat about his evolution from chip design before focusing on chip manufacturing via eBeam technology at D2S.Smith: Let’s talk about your journey from focusing on how to do physical design of chips to chip manufacturing. How did this happen?Fujimura: GPUs weren’t a thing until late 1990s. With CPUs, Manhattan design was the obvious choice for computational efficiency. Largely gridded metal n that went up and down, and metal n+1 that went left and right with vias to connect the line segments were how all automated layout worked. PCB routing and packaging (even back then) used diagonal routing and even curved routing. But chip P R was all Manhattan. That was still true when we worked on the X Architecture at Simplex Solutions (now Cadence). ATi (now inside AMD), NVIDIA and several other GPU companies started in the late 1980s to 1990s, but they were targeting video and gaming more than scientific computing at the time. It’s when Teig came up with the idea for the X Architecture that he wanted to know if 60-degree routing was possible “because a hexagon tessellates a plane.” A good question. I set out to try to find out what the actual limits were in manufacturing that create the limitation to Manhattan shapes. I got introduced to the late Bill Arnold of ASML, who then introduced me to a lot of people in manufacturing who helped me get the answer. Naoya Hayashi of DNP was instrumental in helping me understand that mask making is where the limit exists. Hayashi-san kindly explained to me about the two mask writers. I had to dig around a lot more to make sure that that was the only barrier, but that’s how I came to understand that before masks, everything is data, and after masks, everything is physical. Mask making is the key that enables 45 degrees, but not 60 degrees. The lessons I learned then are still very important to me today. That’s when I saw and appreciated the opportunity there is for software for semiconductor manufacturing.Smith: But you still couldn’t use GPUs for the X Architecture work?Fujimura: Right. Way too early. The idea that GPU-accelerated gaming machines can be connected together to do video editing, or that large scientific simulations can be done on a connected set of gaming machines, was being explored in the 1990s already. It was only 20 years ago (2006) when Jensen Huang announced his bet with the CUDA software stack for general purpose GPUs (GP GPUs) for nodes in racks of CPUs, GPUs, memory and communication to create the modern scientific computer. Six years later in 2012, AlexNet won the ImageNet Large Scale Visual Recognition Challenge (ILSVRC) with CUDA, and the rest is history. But no, we didn’t use GPUs at Simplex. But we did help design GPUs, including with the X Architecture.Editor’s Note: ILSVRC evaluates algorithms for object detection and image classification at large scale. Smith: Now, everything you do at D2S is with GPU acceleration. When and how did that change come about?Fujimura: It was back in 2009, two years after D2S was founded. An extraordinary engineer, Harold Zable, noticed that simulation-based manipulation (rather than rules-based manipulation) of mask shapes, both for wafer manufacturing and for mask manufacturing, would be the ideal application for GPU acceleration. Fast-Fourier Transforms (needed for lithography simulation and optical proximity correction (OPC)/inverse lithography technology (ILT)) and Gaussian manipulations (needed for eBeam mask simulation and mask process correction (MPC) are nearly “free” in terms of compute time on GPUs. You still have to get the data in and out efficiently, but you can do pretty sophisticated computing without much overhead. At the same time, multi-beam based eBeam writing was getting momentum, first in wafer direct write applications. In 2007, at the BACUS conference in Monterey, Calif., IMS—then a well-respected research organization in Vienna—published a paper saying that multi-beam for mask writing is what they’d like to do. The wafer market is much bigger, but this technology is more suited for mask writing, where write times are measured in hours per mask. “Wafers Per Hour” is the measure in wafer manufacturing, so mask writing gets to flip the division. We were looking at a mask design and mask manufacturing world that should be doing simulation-based manipulation rather than rule-based. That’s better with GPUs. On top of that, maybe the world is going to go to multi-beam writing, going away from four decades of variable-shaped beam (VSB) writing. And I knew from the X Architecture experience that VSB was the only thing in the eco-structure that restricted mask shapes to be Manhattan or 45 degrees. In fact, with multi-beam, any curvilinear shape within the limits of resolution of a given pixel size can be freely written on the mask. The only barrier then to having curvilinear masks would be the software stack and trying to compute it with CPUs only. We knew GPU acceleration was the answer. Smith: Was it just totally an accident that multi-beam and GP GPUs happened at the same time?Fujimura: Yeah, it was. However, just as when multiple people simultaneously invent the same thing without knowing about each other, the environment and times in which we live have a lot to do with this. So, I guess, it’s not really just “luck.” But GP GPUs in 2006 and IMS Multibeam in 2007, I think that’s luck.Anyway, D2S became the GPU-acceleration partner for the semiconductor manufacturing industry and decided to work only on things that can be accelerated by GPUs in 2012.Smith: What trends do you see going forward in the next three to five years?Fujimura: A move toward curvilinear mask features, as well as an increased interest in curvilinear wafer targets as designers become aware that the manufacturing side has established a solid path for curvilinear mask shapes. We’re leaving a lot of margin on the table to accommodate gridded Manhattan assumptions, and that’s really no longer necessary from a manufacturing standpoint. I think electronic design automation (EDA) should be working on enabling curvilinear designs, because the door is open for the design world to explore curvilinear chip design and to reap compelling benefits in terms of power/performance and reliability.Editor’s Note: While Manhattan geometries are rectilinear shapes aligned to vertical and horizontal axes, curvilinear design introduces smooth, continuous curves into layouts and masks, leveraging advanced computational lithography and mask-writing technologies. This improves pattern fidelity, electrical performance and manufacturability at advanced technology nodes.About Aki FujimuraAki Fujimura is chairman and CEO of D2S, Inc., and managing company sponsor of the eBeam Initiative. Previously, Fujimura was CTO at Cadence Design Systems, President/COO and inside board member of Simplex Solutions, and VP and inside board member at Pure Software. He co-founded Tangent Systems (acquired by Cadence).Fujimura, made a SPIE fellow in 2023, serves as President of the SPIE BACUS Technical Group. He serves on the governing council of the ESD Alliance, a SEMI Technology Community. Fujimura was on the board of HLDS, RTime, Bristol, S7, and Coverity, Inc.Fujimura received his BSEE and MSEE degrees from MIT.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

Presentations from SEMICON West’s “The Convergence of Semiconductor Manufacturing and Design” offer great insights into the collaboration between the two, as I was recently reminded by presenter Sutirtha Kabir, R D Engineering, Executive Director at Synopsys.Reviewing his talk “Revolutionizing Silicon to Systems Design: Unlocking the Future with 2.5D and 3D Multi-Die Innovations” was a good kick-off for our discussion that covered the continuous need for collaboration and where AI fits. Kabir, as I quickly learned, is a technical innovator and articulate communicator passionate about ongoing collaborations between design and manufacturing. Today’s blog post is the second in a four-part series featuring presentations from the SEMICON West design program, organized by the ESD Alliance, a SEMI Technology Community. The first blog, with Dave Kelf, CEO of Breker Verification Systems, appeared on January 6 (“Circular Collaboration Leverages EDA Advances”).Smith: How do you define collaboration between design and manufacturing?Kabir: Multi-die design and advanced packaging are a big focus of high-performance computing (HPC) and AI chips. Engineers are trailblazing and foundries are coming up with new stacking combinations. For this reason, design and manufacturing teams need to be closer than ever. Solutions must be made available to give ample visibility to manufacturing from the very start of the design process. Single die design has been done for 15 to 20 years with a continuity of power, area, and performance (PPA). Design flows, methodologies and the ecosystem between design houses, EDA vendors and foundries are mature and stable. The conundrum is that it's a different situation with multi-die designs. Not only is multi-die emerging rapidly, but the types of design innovations are different.We have been working closely with our foundry partners to move multi-die innovation forward by enabling more advanced process and packaging technologies. I don't see this slowing down as they are coming up with different ways of doing designs. Design teams are collaborating closely with the foundries to take advantage of the benefits of these new multi-die designs.Smith: You mentioned new stacking combinations and collaboration with the foundries. What about collaboration with the OSATs? Kabir: Generally, it’s both silicon foundries and OSATs. With advanced packaging, both play a significant role depending on the types of applications being targeted. Design house targets may shift from the traditional silicon foundry to several OSATs. For example, if an organic interposer is required, the collaboration could be with an OSAT in conjunction with the silicon foundry. There are many possible collaborations that may be required. The point I’m trying to make is that there is a strong need for collaboration between EDA and the foundries during design that continues through manufacturing and test.Smith: What trends in general are driving the need for this collaboration?Kabir: The trends are performance and scalability and the need for high-performance compute. Look at some of the mega-chip systems coming out today compared to the bigger systems from five years ago. HPC was not driving that much in 2.5D. The big interposers used to be on silicon, maybe 1.2 to somewhere around less than three reticle sizes. Today, the reticle limit is more than 5X. Leapfrog to today, and the configuration has changed where the state of the art is to use an organic interposer with multiple embedded bridges (up to 20 or more) buried inside the interposer to support high-speed interconnect. The organic interposer with multiple layers on the front side and back side communicates with bridges and the SoC and HBM that sit on top of that interposer.3D architectures stack dies with GPUs and a large amount of HBM such as an HBM4 memory stack. The memory stacks may be 8 or 16 high. All of this memory needs to be as close as possible to compute for scalability. In terms of the high-power demand, the designer needs to make sure that the voltage that is pushed from the bottom of the stack can feed the power hungry SoC blocks on top of the 3D stack. At the end of the day, EDA is all about giving design and manufacturing houses the capability to predict how a design is going to perform in all different kinds of scenarios. EDA must keep up with this trend and that requires collaboration.Smith: What about the verification side, specifically system verification? Kabir: Let’s say I am using a spreadsheet and doing back-of-the-napkin calculations, a technique that used to work well for single die or design blocks. Multi-die doesn't scale since multiple heterogeneous dies in a single package must be considered. Design planning must include directional changes to measure the effects with key performance indicators. The challenge is to correlate signoff and verification. Signoff engineers can no longer just verify at the end of the design cycle. Instead, it has become a continuous process that transcends the flow from design planning through implementation and signoff and release to manufacturing.The industry is repeating a pattern from about 20 years ago, when single-die design evolved from relatively naive approaches to much more sophisticated EDA-flow-driven methodologies.Smith: As you drive the tools forward, who are your counterparts on the manufacturing side? Kabir: It depends on the different stages of design—design planning, implementation or signoff. It starts at the architecture stage from the left when architects and physical design engineers are doing floorplanning. The term design technological co-optimization (DTCO) has evolved into S (system)TCO now because we are trying to co-optimize system design and technology. I'll give you a simple example. A working chip manufactured in a certain technology node is going to be used in a multi-die design. Is the existing chip technology good enough to support the design or will it require a new chip at a different node? In either case, how does an engineer work with the manufacturing house to make sure it has the right metal layers or a different number of metal layers or a different metal width or some other property on the technology side? Designers need to make data-driven decisions based on the configuration and technology numbers to meet power budgets.In the past, what was once managed through designer-ASIC house-manufacturing interactions are now increasingly being handled by EDA flows as part of design implementation.Smith: Ultimately, it's driven by business. The hard work and decisions are made by two teams of knowledgeable technical people who must come together.Kabir: And then of course it has to be rolled into program management, business development and all this needs to be supported by data. We all recognize that the design window is not increasing. It’s always about trying to get more out in less time with less people. That doesn't help the equation.Bob Smith: How does AI fit into this and how is it best leveraged? Kabir: I’m hearing, learning, and reading about the tremendous advantages AI could bring. AI has a huge role to play, but it won’t eliminate the need for savvy design and verification engineers.Multi-die design brings together different users from different tool backgrounds. Even the language between a packaging person and a silicon person is different. The terminologies they use are different, as are the ways they have done design over the last 15-20 years. The same applies to thermal, power or signal integrity engineering. Bringing them together requires that EDA will provide platforms where the whole system design, including chip design, is managed. That’s a tall ask for people from all different backgrounds to come in, learn different technologies and tools within a short time. This is where ChatGPT or Microsoft’s Co-Pilot can be applied in the EDA world today to quickly find solutions by reading through manuals, application notes, forums and the like to find solutions. This use of AI agents can save tremendous amounts of time for designers. Another aspect that can be positively impacted are roles. We have customers coming to us and brainstorming on the use of workflows and methodologies, instead of the design aspect. Scalability from the human perspective has become difficult because of the need to closely guide engineers to get them up to speed on new technologies and workflows. This is where Agentic AI can deliver a huge productivity boost. It's not replacing anyone. It's getting them to decisions and end results faster.Smith: Can Agentic AI play a big role? Kabir: Current AI is like the person who, when asked a question, has to give an answer even if it’s the wrong answer. The same thing is going to happen when we bring in all these EDA technologies with AI capabilities.The point I'm trying to make is how do we verify that AI is doing the right thing? In EDA, one of the biggest questions and concerns is if a result or outcome or design can be verified. If it can't be verified accurately, verification engineers will not trust what AI is telling them no matter how fantastic the algorithm is. The verifiability of AI solutions is important for EDA. The key question is: Why would I trust what your tool is telling me to do?EDA flows that are more mature rely on decades of expertise, thorough documentation, and various scenarios to train AI algorithms. Those are the AI-powered EDA flows that I trust the most. About Sutirtha KabirSutirtha Kabir, an Executive Director of R D for Synopsys’ 3DIC Compiler, has over 20 years of product engineering experience, driving, building, and inspiring teams across companies in the EDA industry. In his role at Synopsys, he supports construction and analysis of multi-die systems including stacked ICs plus Interposer configurations. Prior to joining Synopsys, Kabir was a Group Director of Engineering at Cadence. Kabir has a Master of Science degree in Electrical Engineering. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

2025 was a fast-paced, exciting, and impactful year for the SEMI Standards team. We developed 14 new standards on crucial topics like supply chain traceability, defect mitigation, compound semiconductor materials, and so many more. In addition, we introduced the SEMI Global Standards Summit (GSS) in North America, where we created new standardization roadmaps and continued pertinent sustainability conversations from the inaugural GSS at SEMICON Japan 2024. We’re also excited to announce that we closed out 2025 with an impactful Q4. From December 17-19, we held our SEMI International Standards Meetings during SEMICON Japan. More than 15 Task Force meetings and 5 Technical Committee meetings were held, followed by an award ceremony. The brand-new Digital Twins in Manufacturing Task Force was also established to define and standardize a digital twin framework that supports consistent and scalable implementations. We published the new SEMI T27 standard in Q4, and we celebrated several outstanding volunteers for their contributions to the SEMI Standards Program at both SEMICON West and SEMICON Europa. As we reflect on Q4, it’s apparent how important collaboration is to the success of SEMI Standards. By working together, we lay the foundation for groundbreaking innovations in microelectronics manufacturing. The SEMI Standards team would like to extend a warm and sincere thank you to everyone who donated their time and expertise to define the future of our industry. These efforts would not be possible without your commitment and support.Still, it’s never too late to join the SEMI Standards Program. Learn more about membership and how you can help influence the next phase of semiconductor manufacturing. Q4 2025 HighlightsTakeaways from the International Standards Meeting at SEMICON JapanIn Q4, the SEMI Standards team held its International Standards Meeting at SEMICON Japan, where several task forces convened to set standards for compound semiconductor materials, information and control, traceability, and more. From December 17-19 at Tokyo Big Sight, the SEMI Standards team supported these technical committees in advancing several key standards revisions, including SEMI E181, Specification for Panel FOUP for Panel Level Packaging, and SEMI E182, Specification for Panel FOUP Loadport for Panel Level Packaging. In addition, a new Maintenance Robot Communication (MRC) Task Force was established with the objective of defining communication protocols and data exchange specifications between maintenance robots and equipment.The next SEMI International Standards Meeting will take place from May 11-14 in Albany, New York, during the SEMI Advanced Semiconductor Manufacturing Conference (ASMC). Digital Twins in Manufacturing Task Force Although the terms “digital twins” and “digital twin frameworks” are becoming more prevalent in the semiconductor industry, there’s still much debate on what they cover. To develop concrete, standardized definitions for each, the SEMI Standards team established the Digital Twins in Manufacturing Task Force in Q4. After the task force defines these crucial terms, it will then create definitions for internal digital twin components outlining baseline capabilities, discovery mechanisms, prediction quality metrics, unified model interfaces, and lifecycle management. Eventually, the task force will outline a framework for Digital Twins compatible with existing guidelines like SEMI Standard E133 or ISO 23247. The SEMI Digital Twins in Manufacturing Task Force is open to industry stakeholders. To participate, join the SEMI International Standards Program or learn more. Standards Awards at SEMICON West and SEMICON Europa SEMICON West honoreesQ4 was also a time to celebrate some of the talented individuals who make a difference in the SEMI Standards Program. At SEMICON West and SEMICON Europa, we honored 25 accomplished industry leaders across the following five award categories for their commitment and participation. Merit Award winners led projects to successful completion at the task force level. SEMICON Europa honorees: Judith Wittmann, Cristina Sanna, Peter Wagner, Friedrich Passek, Frank Riedel SEMICON West honorees: Dave Dunne of Applied Materials, Kirsten Smith of UCT/ChemTrace, Tommaso Orzali of ASML, Dr. Tyler Harrison of Teledyne MEMS, and Dr. Mary Ann Maher of SoftMEMSSEMICON Europa honorees: Christian Kranert of Fraunhofer IISB, Enrica Cela of Soitec, Hans-Christian Alt of the Munich University of Applied Sciences, and Ulrich Kretzer of Freiberger Compound Materials GmbHLeadership Award winners bolstered the SEMI Standards program through member recruitment, mentoring, and training efforts. SEMICON West honorees: Michael Potts of Arcadis, David Kandiyeli of KINETICS Equipment Solutions Group, and Per Nelson of Daikin AmericaSEMICON Europa honorees: Frank Riedel and Judith Wittmann of Siltronic, Cristina Sanna of GlobalWafers, and Jochen Ruth of Pall CorporationHonor Award winners have demonstrated long-term dedication to advancing SEMI Standards.SEMICON West honorees: Steve Martell of Nordson Test Inspection Americas, Lucian Girlea of Nikon Precision, and Dave Huntley of PDF SolutionsSEMICON Europa honorees: Peter Wagner of SEMI Standards, Fritz Passek of Siltronic, Arnd Weber of SiCrystal GmbH, and Frank Petzold of trustsec IT solutions GmbHCorporate Device Member Award winners are participants from the user community who act as corporate representatives for the SEMI Standards Program from the device manufacturer side. Stefan Radloff of Intel was honored with this award at SEMICON West. Technical Editor Appreciation Award winners are adept at translating complex technical information into clear and precise language. Dr. Alissa M. Fitzgerald of A.M. Fitzgerald Associates became the award recipient in 2025. Workshops at SEMICON WestOn October 8, the SEMI Voltage Sag Immunity Task Force hosted its Enhancing Voltage Sag Immunity workshop to address fab downtime caused by voltage sags. The workshop convened more than 20 industry professionals to review the limitations of SEMI Standard F47. They found that while 20% of downtime instances can be attributed to three-phase events, SEMI Standard F47 does not require testing for such occurrences. As a result, the Voltage Sag Immunity Task Force is developing a draft revision of SEMI Standard F47, scheduled for balloting in March 2026. If you missed this workshop, you can access the recording and presentation here. October 8 also saw the exciting return of the Analytical Workshop, hosted by the SEMI Liquid Chemicals Committee after a multi-year hiatus. This year’s workshop addressed near-term challenges and advancements identified by the International Roadmap for Devices and Systems (IRDS). It covered chemical quality and consistency, trace metallic impurities and improvements in ICPMS instrumentation, automated instrumentation for online measurements, detection for particle precursors and sub-10nm particles in liquids and on-wafer, and organic particle precursors identification using FTIR-ATR, SERS and AFM-IR. If you missed this workshop, you can access the recording and presentation here. The 2026 call for abstracts will be announced soon. Lastly, the SEMI Standards and SEMI University teams worked together to host Semiconductor Device Manufacturing in a Cleanroom, a workshop meant to introduce best practices for overcoming contamination problems in the cleanroom. By reviewing different sources of contamination, reviewing analytical techniques for quality control, and performing cleanliness testing, the course aims to help cleanroom facilities improve production reliability and yield.New and Revised Standards Released in Q4October 2025November 2025December 2025Get InvolvedSEMI Standards development activities take place throughout the year in all major manufacturing regions. To participate, join the SEMI International Standards Program.SEMI Standards are available through individual download purchases or online via SEMIViews. Watch this video to learn more about how SEMIViews offers a cost-effective and streamlined way to access 1,110+ SEMI Standards. Sign up for a 30-day SEMIViews trial.For more information, please visit the Standards website and events page. For any questions regarding SEMI Standards activities, please contact your local SEMI Standards staff.Paul Trio is Director of Standards at SEMI.

Cybersecurity vulnerabilities within the semiconductor supply chain are a growing concern, ranging from individual threats to whole supply chain cyber resilience. It is imperative that the semiconductor industry addresses these risks. Last year, the Semiconductor Manufacturing Cybersecurity Consortium (SMCC) at SEMI introduced Semiconductor Supplier Cybersecurity Assessment (SSCA), providing a streamlined framework allowing suppliers to complete one standardized questionnaire to comply efficiently. The assessment process involves suppliers presenting evidence to support their claims of security controls and measures put in place. Such a body of evidence is critical to establish confidence in the suppliers’ ability to manage risk and comply with standards. The SSCA is a free, open-access resource for the semiconductor industry. This is intentionally made openly available to support SMCC’s mission to strengthen cybersecurity across the semiconductor manufacturing ecosystem. The questionnaire aligns with the six functions of the National Institute of Standards and Technology (NIST) cybersecurity framework 2.0: Govern, Identify, Protect, Detect, Respond and Recover. A recent project led by Swansea University’s Systems Security Group (SSG), in close collaboration with SEMI SMCC, is mapping the evidence requirements necessary for SSCA assurance. The project is funded by the UK Research and Innovation (UKRI) as part of seed funding to support UK/US/Germany collaborative research and innovation projects in the field of semiconductor security. UKRI supports such collaboration in the interest of “maintaining confidence in security throughout the design and manufacturing processes,” and particularly to support research addressing “what tools and techniques could help to reduce the risks associated with third-party hardware design and manufacturing services?”.The project ensures that the global ecosystem is engaged so that evidence requirements developed are acceptable, cost-effective, in line with the latest standards and practice, and ultimately suitable for adoption. As part of this project, two workshops are being organized, one in Germany at Bavarian Chip Alliance, Nuremberg on Tuesday, March 10 and one in the UK at Swansea University on Thursday, March 12, aiming to introduce SSCA and the evidence requirements, gather feedback and inspire early adoption. Join either of these workshops to help shape the evidence requirements and help prepare for effective supply chain security assurance. Participants must download the SSCA framework prior to the workshop.Register for the Germany Workshop on March 10Register for the UK Workshop on March 12Key TopicsIntroduction to Semiconductor Manufacturing Cybersecurity Consortium (SMCC)Standardized Semiconductor Cybersecurity Assessment (SSCA)Supply chain assurance and evidence mappingGroup discussion to feedback on evidence requirementsOpen Q A with cybersecurity and compliance expertsWho Should AttendCybersecurity and compliance professionalsSemiconductor suppliersLegal and regulatory affairs professionalsFabless chip designers and foundriesTesting, packaging, design software, R D tools and IPManufacturing/assembly equipment and ancillary fab servicesIntegrated device manufacturersAbout the authors:Siraj Shaikh is a Professor in Systems Security at Swansea University (UK). His research interests lie at the intersection of cybersecurity, systems engineering, and computer science addressing cyber-physical systems security for automotive and transport systems. He is also Co-Founder and Chief Scientist at CyberOwl, which is dedicated to risk analytics and security monitoring for the maritime sector.Mayura Padmanabhan is a Technical Project Manager at SEMI who manages the Cybersecurity Technology Coalition and Traceability activities.

Every time a transistor switches, it generates heat. Pack enough transistors together and you hit a wall: the chip melts before it computes. This thermal ceiling is why Splunk notes that "as physical and economic limitations are reached, the pace predicted by Moore's Law is slowing."Light solves this problem. Photons carry information without generating heat. Semiconductor Engineering details how heat dissipation and bandwidth bottlenecks make optical solutions the only viable path forward.But photonics introduces a different problem. Silicon has an indirect bandgap, which means it cannot emit light efficiently enough to produce lasers. Building photonic systems requires III-V compound semiconductors like indium phosphide (InP) and gallium arsenide (GaAs). These materials come with manufacturing constraints: InP substrates remain limited to 150mm, and GaAs wafers top out at 150mm, while silicon runs at standard industrial diameters of 200mm or 300mm. You cannot build a complete photonic system on silicon alone, so heterogeneous integration becomes mandatory. The result is that chief technology officers (CTOs) now manage two incompatible material systems, doubling technical complexity and supply chain risk.How Different Regions Are RespondingUnited States Intel has shipped 8 million photonic chips with 32 million integrated lasers. But the move that matters most is NVIDIA adopting TSMC-Broadcom co-packaged optics in its 2025 GB300 chips. When the dominant AI hardware company makes an architectural choice, competitors either follow or lose relevance.EuropeEuropean companies are solving their scale problem through consolidation. The market grew from €124.6 billion (2022) to a projected €175 billion (2027). Between January and June 2025, EPIC recorded 125 transactions worldwide, with European companies leading 50 of them. ZEISS established a new strategic business unit with €200 million in annual revenue across 6 countries. The strategy is to build on existing strengths in materials science and precision manufacturing.ChinaChina is building a parallel system designed for self-sufficiency. CHIPX produces 6-inch lithium niobate wafers with 110 GHz bandwidth, built despite U.S. export controls. This aligns with national policy: Xi Jinping chaired a February 2023 Politburo session focused on "basic research for self-reliance in science and technology." Optics Valley now hosts 5,000+ high-tech companies, targeting self-sufficiency within 4 years.Asia-PacificJapan, Taiwan, and India are combining strengths rather than building everything domestically. Japan committed $25.7 billion to semiconductor development between 2022 and 2025, and TSMC opened its first overseas R D facility there. India offers up to 50% capital support for photonics fabs and contributes 20% of global chip designers.The Next DecadeMarket projections vary wildly because the category spans everything from mature LED lightbulbs to emerging quantum computing systems. Mordor Intelligence projects growth from $1.75 trillion in 2025 to $2.39 trillion by 2030, while MarketsandMarkets forecasts $1.09 trillion to $1.48 trillion. This uncertainty matters because executives must commit billions in capital to technologies with decade-long development cycles.2025-2026The near-term focus is power efficiency. Traditional pluggable optical modules create 22 decibels of signal loss, requiring 30W per port to compensate. Co-packaged optics cuts power consumption by 3.5x. Ayar Labs' TeraPHY will deliver 8 Tb/s using UCIe standard packaging. In automotive, entry-level LiDAR drops to $200.2027-2032Quantum photonics moves from laboratory to commercial deployment. The market grows from $850 million in 2025 to $3.78 billion by 2030, with PsiQuantum partnering with GlobalFoundries to develop million-qubit systems by 2027. Unlike superconducting qubits requiring near-absolute-zero cooling, photonic qubits function at room temperature.2032-2035+The quantum market reaches $17.4 billion by 2035. Architectures combining analog, digital, quantum, photonic, and neuromorphic computing will require new transducer technologies, which means CTOs can no longer specialize in a single computing paradigm.Energy demand accelerates all of this. Data center electricity consumption will reach 945 TWh by 2030, and photonics can reduce that by over 50% by 2035.What This Means for LeadershipEach executive role faces a distinct version of the same problem: making decisions now about technologies that won't mature for years.Chief Executive OfficersCEOs face timing decisions with no clear answer. Adopt co-packaged optics in 2025-2026 and risk immature technology. Wait until 2028 and watch competitors capture market share. Japan's $25.7 billion commitment means smaller firms now compete against sovereign capital.Chief Technology OfficersCTOs must hold technical depth across incompatible domains. Silicon photonics, III-V materials, and thin-film lithium niobate each require different knowledge bases and supply chains. Most engineers specialize in one; photonics CTOs need working knowledge of all three while balancing 15-year development cycles against 2-year product roadmaps.Chief Financial OfficersCFOs must model returns on infrastructure that doesn't exist yet. The 50% power reduction from photonics changes total cost of ownership calculations, but boards need convincing before savings materialize.Corporate Boards Boards face a knowledge gap that affects governance quality. Most members don't understand why quantum-neuromorphic-photonic convergence matters at the business level. Leadership transitions signal consolidation is underway: IPG Photonics replaced its CEO in June 2024, Lumentum in February 2025.The Leadership ProblemFinding people who can run photonics companies is difficult because the field barely existed a decade ago. The technical knowledge lives in research labs. The business experience lives in traditional semiconductors. The people who combine both are rare.The broader market reflects this scarcity: over 330 R D vacancies appeared in the first half of 2025 alone. When technical roles are that hard to fill, executive searches require a global reach that most firms lack. In our searches, we regularly build single leadership teams by recruiting across China, Romania, Russia, the U.S., Germany, France, the UK, and India.The companies that figure out leadership first will have an advantage that compounds over years.About the AuthorsJan-Bart Smits is a Managing Partner at Stanton Chase Amsterdam. He serves as Global Subsector Leader for the Semiconductor industry and holds an M.Sc. in Astrophysics from Leiden University. David Harap is a Managing Director at Stanton Chase Austin with over 25 years of executive search experience. A Cornell University graduate and Father Kelly Scholar, he lectures at the University of Texas at Austin.

On December 13, SEMI submitted its response to a Request for Information (RFI) from the U.S. Department of Commerce (the Department) regarding the newly launched American Artificial Intelligence (AI) Exports Program. The intent of this program is to position U.S. firms as global leaders in AI by connecting them with international buyers, leveraging the Department's export promotion tools and supporting industry-led consortia through targeted government backing. By issuing this RFI, the Department intends to solicit input on the development of industry-led consortia capable of delivering full-stack American AI export packages under the American AI Exports Program. Working with member companies, the SEMI Public Policy and Advocacy (PP A) team developed a response highlighting the importance of the semiconductor supply chain to the AI ecosystem, and offering various recommendations for consortium formation, federal support, strategic objectives, and proposal evaluation. The response was informed by direct discussions between SEMI PP A and Department officials implementing the program. Some of the key aspects of SEMI's response include the following:Broader AI Tech Stack Definition: The Department should recognize semiconductor manufacturing technologies, mature node semiconductors, and energy/environmental control systems as foundational elements of the AI technology stack. Evaluation Framework: Evaluation criteria for consortium proposals should align with CHIPS for America requirements and guardrails, focusing on national security, economic competitiveness, and commercial viability, as well as infrastructure needs.Consortia Governance: Consortia should be industry-led and feature: honest brokers capable of coordinating commercial actors while advancing national interest objectives; modularity to ensure that the various technology layers function as distinct yet interoperable units; and clear frameworks for intellectual property protections and regulatory compliance. Foreign Participation: Vetted foreign entities should be allowed to participate in the program in order to reflect the global nature of the AI ecosystem and to strengthen allied and partner nation supply chain resilience.Federal Support Mechanisms: The Department should leverage the unique capabilities of the National Institute for Standards and Technology, Center for AI Standards and Innovation, Bureau of Industry and Security, Export-Import Bank, Development Finance Corporation, and others, including expedited licensing, financing tools, tax incentives, and interagency liaisons to accelerate exports. National Security Compliance: SEMI's comments emphasize robust compliance programs, cybersecurity, supply chain security, and risk-based licensing to prevent misuse or diversion of AI technologies. Global Competitiveness and Standards: SEMI urges rapid implementation, international promotion of U.S. AI technologies, and leadership in global standards to ensure interoperability and trusted adoption worldwide.SEMI is grateful for the feedback provided by our member companies in developing this comprehensive response to the Department's RFI. Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Ben Kallen is Sr. Manager, Public Policy Advocacy at SEMI.

2025 was a milestone year for the Semiconductor Manufacturing Cybersecurity Consortium (SMCC). Across standards development, industry collaboration, and community engagement, the SMCC major advancements strengthened cybersecurity across the global semiconductor supply chain.From new guidance documents to standing-room-only conversations at SEMICON West, the past year demonstrated what’s possible when industry, government, and technology leaders come together with a shared mission: protecting one of the world’s most critical industries.More Than Just Standards: 2025 SMCC Created Key Assets One of the most significant accomplishments of the year was the release of the SEMI E187 Compliance Guidance Document. This new resource provides supplemental guidance, rationale, and example artifacts for all twelve E187 Standards requirements, helping organizations more clearly understand what good cybersecurity practice looks like in real-world semiconductor environments.In September, SMCC introduced the Semiconductor Supplier Cybersecurity Assessment (SSCA), a streamlined framework that allows suppliers to complete one standardized questionnaire showing their level of cybersecurity and share results with multiple customers thereby reducing compliance burden and improving efficiency. With the SSCA, suppliers can complete one standardized questionnaire and share results with multiple customers, cutting down on redundant requests while improving consistency and efficiency.Both the SEMI E187 Compliance Guidance Document and the SSCA are free resources for anyone in the industry. These assets were intentionally made openly available. SMCC’s goal is to strengthen cybersecurity across the ecosystem, not to profit from it. By enabling broad adoption, these resources are designed to deliver collective benefits and accelerate progress for everyone.SMCC also collaborated with NIST through the development of the NIST CSF 2.0 Semiconductor Manufacturing Profile. The profile completed its public comment period in July and helped align semiconductor manufacturing needs with the latest version of the NIST Cybersecurity Framework.Cybersecurity Takes Center Stage at SEMICON WestJennifer Lynn from IBM shares her insights about the NIST CSF 2.0 semiconductor manufacturing profile during the Cybersecurity Forum.Cybersecurity was front and center at SEMICON West, where SMCC’s Cybersecurity Forum drew more than 100 attendees from across the semiconductor ecosystem. The program featured a strong lineup of speakers from device makers, equipment suppliers, cybersecurity firms, and government agencies, covering topics such as supply chain assurance, fab equipment security, vulnerability management, and regulatory trends.Poster Presentations at the Cybersecurity ForumThis year also marked a first for SMCC with the inaugural Cybersecurity Poster Presentation, showcasing innovative work from more than 10 companies and academic contributors. The session created space for deeper technical conversations and highlighted the breadth of thinking across the community.The event would not have been possible without the generous support of the Cybersecurity Forum sponsors: Applied Materials, Fasoo, PEER Group, Seclore, Tokyo Electron, and TxOne Networks. Their commitment underscores the growing recognition that cybersecurity is a shared responsibility.Celebrating the People Behind ProgressAt the heart of SMCC’s success are the volunteers who dedicate their time and expertise to advancing the consortium’s mission. A special Leadership Excellence Award was presented to Doug Suerich (PEER Group) in recognition of his exceptional contributions and lasting impact on SMCC’s work.During the forum, we awarded several Working Group members for their outstanding contributions:SZ Lin (Sun Square) receiving a certificate of merit for his contributions to SMCCAnu Machavarapu (ASML)Anusha Annapareddy (Applied Materials)Donato Kava (Advanced Energy)Jared Buckley (Texas Instruments)Mashiro Supika (Tokyo Electron)Pradeep Kumar (Lam Research)Ryan Daniel (PEER Group)SZ Lin (Sun Square)TxOne NetworksWe also honored the leadership and commitment of our Working Group Chairs, whose guidance and persistence continue to shape SMCC’s direction:Albert Fuchigami (PEER Group), Andrew Seward (Tokyo Electron), Bill Higgs (ASML), Daniel Platea (ASML), Dave Dunne (Applied Materials), Eiji Hagio (Tokyo Electron), Jennifer Lynn (IBM), Kim Daich (PDF Solutions), Konstantinos Papapanagiotou, Leon Chang (TSMC), Lori Kessler (Applied Materials, Retired), Mike Tanori (Intel Foundry), Quentin Ellis (PEER Group), Ryan Bond (Intel Foundries), Sukwon Kang (Applied Materials), Wilko Baks (ASML), and Youngwoo Son (SK Hynix).Looking AheadAs we close out 2025, we extend our sincere thanks to all SMCC volunteers, Working Group Chairs, forum speakers, poster presenters, sponsors, and the SMCC Governing Council. Your dedication continues to move the industry forward and strengthen cybersecurity across the semiconductor landscape.If you’re interested in getting involved in SEMI’s cybersecurity activities, we’d love to hear from you. Please contact Mayura Padmanabhan at [email protected] to learn more.

Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain.At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth trajectory of this critical sector and Europe’s potential to lead in next-generation packaging solutions.Market Momentum Fueled by AI and HPCRomain Fraux, Chief Research Officer at Yole Group, forecasted that global revenues for advanced packaging will grow from $46.1 billion in 2024 to $79.4 billion by 2030. “Everything is linked to AI and high-performance computing (HPC),” said Fraux, while also emphasizing the growing relevance of automotive applications in driving demand.Romain Fraux, Chief Research Officer, Yole GroupThis demand is accelerating innovation across the supply chain. One emerging area is panel-level packaging, which breaks away from traditional round wafers. As Andreas Wocko, Sales Manager at Lam Research, observed, “Since the 1970s, the semiconductor industry has built on wafers. Now we are not just scaling, we are reshaping, building in a square format for the first time” – an innovation which substantially increases area efficiency and reduces device cost. Andreas Wocko, Sales Manager Europe, Lam ResearchTechnology Transformation from Lab to FabEurope is already investing in the foundational technologies that will power tomorrow’s packaging systems. Rolf Aschenbrenner, Deputy Director of Fraunhofer IZM, the home of the European Union’s APECS advanced packaging pilot line, discussed ongoing research into functional interposers, routing density, and organic interposers. “Our goal is to show how a new design philosophy incorporating chiplets can be brought to the industrial systems level,” said Aschenbrenner.Rolf Aschenbrenner, Director Deputy, Fraunhofer IZMThese breakthroughs are essential, as pitch sizes shrink and new materials emerge. Dr. Jessica Stubbe, Global Application Manager at MKS Atotech, described how interconnect densities have doubled in the past two years, with the industry moving to pitch sizes of less than 10µm. Stubbe said this new technology “will be enabled by a move from traditional solder-based interconnects to copper-to-copper hybrid bonding to provide higher density I/Os and lower resistance.” Jessica Stubbe, Global Application Manager, MKS AtotechInnovation Meets Real-World IntegrationThis increased density carries thermal risks with it. As Ram Trichur, Global Head of Semiconductor Packaging at Henkel Corporation, said, “New architectures enabled by advanced packaging are putting power devices on the backside, interposer or substrate, and this addition of more power delivery components in the package creates more local hotspots.”The reduced feature sizes inside the latest packages make it more difficult than ever to apply thermal interface materials. “At Henkel, we are now making 1µm-level fillers which enable the effective filling of gaps as small as 7µm,” said Trichur.Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationOne of the applications which stands to gain the most from the development of advanced packaging technology is silicon photonics. Dr. Himani Kamineni, Director for Advanced Packaging at GlobalFoundries, described how co-packaged optics (CPO) brings photonics directly inside the package, reducing connection lengths from centimeters down to millimeters, and providing higher bandwidth and lower latency at lower power. “Advanced packaging and CPO are foundational elements for AI and data centers to enable scalability to the next generation of compute,” said Kamineni. “But it will need a lot of packaging innovation: silicon interposers, copper-to-copper interconnects, and fiber-attach units for precise alignment.” Himani Kamineni, Director, Advanced Packaging, GlobalFoundriesReliability and Test Under PressureIn the transition to new packaging technology, it is crucial that the industry does not lose sight of the reliability standards which have made semiconductors so valuable in sectors such as automotive and aerospace. Amar Mavinkurve, Director of Materials and Labs Package Innovation at NXP Semiconductors, warned the finer spacing and smaller feature sizes in the latest packages posed a problem for reliability and long-term performance. He said, “We are dealing now not just with one failure mechanism, but with multiple. So, the way that we are used to describing behavior in models will not necessarily hold in future. Even industry standards might not hold.”Discussing new technologies such as copper-to-copper interconnects, Mavinkurve pointed out that failure would not be due to a single event, but to processes such as electromigration, corrosion, and thermomechanical effects. To model reliability properly in future, he said, “we need to move from a physics of failure to a physics of degradation.” Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP SemiconductorsFabio Pizza, Business Segment Manager at Advantest Europe focused on quality and failure. With geometry scaling toward 1nm, early identification of known-good dies is essential to optimize cost and test coverage. Pizza said that, while device manufacturers need to keep time-to-market and the cost of test under tight control, they are also trying to figure out how to increase test coverage. “In a modern GPU, even a 100 DPPM quality process leaves 20 million transistors untested,” he said. Fabio Pizza, Business Segment Manager, Advantest EuropeEurope’s Position in the Global EcosystemThe conference concluded with a panel discussion about the prospects for Europe in the global advanced packaging market. According to Yole’s Romain Fraux, there is a strong ecosystem in Europe: “Europe’s strengths include specialized packaging service providers in the photonics and power market segments, as well as many packaging equipment manufacturers,” said Fraux. This resonated with the instincts of NXP’s Amar Mavinkurve and Advantest’s Fabio Pizza. Mavinkurve said: “We should focus on what we are already good at doing. It will be challenging to compete with advanced packaging providers elsewhere for AI and HPC business.”Ram Trichur of Henkel, however, urged the industry in Europe, “Do not take your foot off the gas on advanced packaging. You cannot do the full stack here, but in a technology such as CPO, there is a lot of innovation in Europe, and there is scope to add the manufacturing of these devices on top of the research capabilities.”Chris Scanlan, Senior Vice President of Technology at Besi, raised the idea of shifting production toward Eastern Europe. But Trichur cautioned that talent and infrastructure remain limiting factors in that strategy. From left to right: Chris Scanlan, Senior Vice President Technology, Besi;Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP Semiconductors; Fabio Pizza, Business Segment Manager, Advantest Europe; Rolf Aschenbrenner, Director Deputy, Fraunhofer IZM; Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationCollaboration is the Path ForwardSpeakers throughout the conference echoed a common message: advanced packaging is reshaping the semiconductor landscape, and global collaboration will be essential to success. “It is impossible for one country or one region to do the entire stack,” Trichur concluded. “Innovation must be matched with strategic partnerships to bring advanced packaging from research to real-world impact.”On behalf of SEMI, the SEMI Europe team would like to thank the industry leaders whose expertise and enthusiasm made this conference a resounding success. SEMI ContactCassandra Melvin, Senior Director of Business Development and OperationsEmail: [email protected]

The semiconductor industry is the bedrock of modern technology, enabling everything from AI and cloud computing to electric vehicles. Yet, this critical sector is also one of the most resource-intensive globally, with a substantial dependency on water. A single fabrication plant can demand up to 10 million gallons of water daily, comparable to the consumption of a city with 300,000 residents. Much of this water is, of course, reused and recycled through sophisticated systems. This immense water usage, particularly the requirement for ultrapure water for processes like cleaning and etching, makes consistent access to high-quality water a non-negotiable for operational reliability and business continuity. The new insights report "Ripple Effects: Water Risk and Resilience Across the Semiconductor Value Chain" provides the first global baseline of water risk hotspots for the semiconductor sector, assessing water risks across 140 facilities across 89 water basins to inform future risk mitigation strategies.The analysis discusses how water risk can manifest itself as a financially material impact on business continuity by triggering idle time, recovery costs, and cascading delivery delays across global supply chains. S P Global projects that by 2050, water-related risks could cost the world's largest IT companies up to $24 billion annually. Crucially, the study identified flooding and reputational risks—such as strained relationships with local communities over water allocation—as the most significant immediate threats to the semiconductor value chain. These concerns are most acute in major hubs like Taiwan, South Korea, and parts of the U.S.While the industry is frequently criticized for its water usage, only 16% of the analyzed sites are currently affected by water scarcity. However, this metric offers a false sense of security. As climate change intensifies, the frequency and severity of water-related disruptions are set to exceed the scope of existing contingency plans. The long-term projections show that over 40% of semiconductor facilities announced since 2021 are located in watersheds projected to face high or extremely high water stress between 2030 and 2040. This underscores the urgent need to integrate forward-looking risk modeling into new site planning to ensure long-term operational resilience.Effective risk management is significantly hindered by the limited transparency surrounding supplier-level water data. While many companies perform water assessments for their direct operations, a comprehensive, industry-wide approach to supplier data and risk management is lacking. CDP data shows that 1 in 5 companies reported $77 billion under threat from supply chain water risks, yet only half of those companies engage with their suppliers on these issues. For semiconductor end users, these risks are often deep within multi-tiered networks, requiring engagement that goes well beyond Tier 1 suppliers.To manage these complex risks, the report stresses the necessity of moving toward a contextual approach that includes localized assessments. Contextual water risks are inherently location-specific, dependent on local availability, quality, and infrastructure, as well as broader catchment-level dynamics, regulatory pressures, and community expectations. Several structured methodologies support this necessary shift from basic operational management to corporate water stewardship, including the Alliance for Water Stewardship (AWS) Standard, the TNFD's LEAP framework, and the Science Based Targets for Nature (SBTN). This approach encourages companies to look beyond their own operations to safeguard regional water security.Because water is a shared resource, collective action is essential to deliver the scale and urgency needed to tackle common challenges within catchments. The semiconductor value chain is deeply interconnected, with companies often sharing suppliers within the same water basins, creating a strategic opportunity for collaborative stewardship. The report encourages companies to scale their impact by moving beyond isolated efforts to form sector-wide and cross-sector partnerships—especially at the catchment level—through public-private engagement. This collaboration, which includes proactive engagement with policymakers and local utilities, is key to aligning on water management and stewardship practices to address shared water challenges and build collective trust.Innovation and technology must play a central role in advancing water stewardship across the value chain. A major hurdle is the general undervaluation and mispricing of water, which perpetuates systemic underinvestment in water-focused technology. Despite this, leading semiconductor companies are deploying advanced solutions such as onsite recycling systems, real-time water monitoring, and utilizing alternative sources like municipal wastewater. Embracing AI-driven systems for scenario modeling and catchment-level risk forecasting further enhances adaptive capacity and resilience.The "Ripple Effects" report makes it clear that water challenges affect every segment, demanding tailored response tactics and strategies. Foundries, with their large operational footprints, must prioritize sourcing reclaimed water and expanding onsite reuse, while chemical and materials suppliers must proactively manage rising regulatory risks around water quality contaminants. The insights report also provides a practical roadmap for advancing corporate water stewardship, outlining progression from water risk assessment (Stage 1) to site-level action and collective engagement (Stage 2), and culminating in transparent validation and reporting (Stage 3). By following a structured water stewardship pathway, the semiconductor industry can build operational resilience and ensure a responsible future for the entire value chain.To learn more, download the report or watch the webinar recording. Alua Suleimenova is Senior Program and Staff Manager | Global Sustainability at Marvell Technology and leader of SEMI's ERMR Working Group.The Environmental Risk Mitigation and Reporting (ERMR) Working Group was established under SEMI's Sustainability Initiatives in January 2023, and it aims to develop a baseline and roadmap of best practices for identifying, managing, governing and reporting climate, water, and biodiversity risks across the semiconductor value chain. This insights report is a publication in SEMI’s ERMR Working Group thought‑leadership series on global environmental risks and resilience.

The semiconductor industry is expanding at an unprecedented pace. Global semiconductor revenues are now forecast to exceed $1 trillion annually by 2030, yet recruitment is struggling to keep pace with the demand for new workers. This is why talent development is a critical focus for SEMI and the SEMI Foundation.Young professionals and students are crucial stakeholders of future talent. Held during SEMICON Europa, Building the Talent Pipeline event provided a showcase for some of Europe’s most enthusiastic promoters of careers in the industry: the Student Ambassadors of the European Chip Skills Academy (ECSA). The session opened with Andra Bornea, a Master’s student of electrical engineering at the Technical University of Cluj-Napoca in Romania, who shared the inspiring story of her journey towards a career in electronics. “For me, it started when I attended the ECS Summer School in 2023 along with 39 other students. It was a life-changing experience,” Bornea shared.The Summer School is a week-long programme jointly organised by AENEAS, ECSA, EPoSS and Inside, bringing together lectures, demonstrations and interactive sessions that give students a first-hand glimpse into what a career in semiconductors can look like. For Bornea, the impact was immediate and decisive. “Attending the Summer School convinced me to shift the focus of my studies from telecommunications and pursue a Master’s in electrical engineering,” she added. Today, Bornea is one of 70 students across Europe who form the ECSA Student Ambassador Programme, a community she describes as “a vibrant network of motivated students working towards the goal of keeping Europe at the forefront of the global semiconductor industry.”Andra Bornea, Technical University of Cluj-Napoca The event also featured other ECSA student ambassadors who are actively promoting the semiconductor industry within their own academic communities. One of them was András Bálint Mészáros, an electrical engineering student at the Budapest University of Technology and Economics, who spoke about his determination to build a student electronics club despite facing administrative hurdles along the way. Reflecting on the process, Mészáros said, “ECSA provided good opportunities to start a community of students interested in observing how the microelectronics industry works.”András Mészáros, Budapest University of Technology and Economics A similar spirit of initiative was shared by Nassim Beladel, a Master’s student at ETH Zurich, who described founding Young Neuromorphs which is a student association focused on computational hardware design inspired by the structure of the human brain. Beladel outlined ambitious plans for the group, including an FPGA hackathon in 2026 supported by the Edge AI Foundation, as well as a proposal to present the association’s work at an IEEE event in Shanghai. Nassim Beladel, ETH Zürich These new initiatives supplement a vibrant network of clubs and events around Europe. Octavian-Constantin Axinte, a Master’s student at the Technical University of Cluj-Napoca, told the forum of a Romanian competition for electronics students which has its roots way back in 1992. The Technologies of Interconnections in Electronics (TIE) contest attracted 1,500 students to its final stage in 2025. Axinte said that the benefits of participation included “hands-on experience of professional work, interaction with teachers, and, if all goes well, a job offer!” Octavian Axinte, Technical University of Cluj-Napoca Pioneering Research Efforts of the Next Generation of Students The Building the Talent Pipeline event also gave ECSA student ambassadors an opportunity to describe the findings of research projects that they have undertaken. Laura Sondakh, a Master’s student at Ghent University, presented her research into the environmental and social impacts of tantalum and cobalt which are critical minerals used in electronic components such as capacitors. “These minerals mostly come from the Democratic Republic of Congo, a country which ranks very low on development indices,” she explained, noting that many mines are located in conflict-affected regions in the east of the country. Laura Sondakh, Ghent University Vuk Vulević, a Bachelor’s student of telecommunications and IT at the University of Belgrade, shared his work on the applications of quantum computing, highlighting its potential beyond classic engineering uses such as machine learning. He explained how quantum technologies could also be applied “in pharmacology, for simulating complex molecules and testing compounds virtually, and in finance, for performing risk analyses and Monte Carlo simulations at high speed.” Vuk Vulević, University of Belgrade Z Zainab, a Research Assistant at Hochschule Anhalt, shared insights from her research into how mechanical strain can be introduced during the wafer saw-dicing process which is a critical step in turning wafers into individual chips. Using Raman spectroscopy, her work helps identify how key process parameters influence wafer integrity, enabling manufacturers to better optimise dicing conditions and reduce hidden damage that can affect chip reliability and manufacturing efficiency.Z Zainab, Research Assistant, Hochschule Anhalt Future Plans for Building the Talent Pipeline The event concluded by looking ahead at how SEMI and its partners are scaling up programmes to support talent development worldwide. Victoria Cummings, Senior Manager for Workforce Development and EU Projects at SEMI Europe, introduced Reinforcing Skills in Chips Design for Europe (RESCHIP4EU), a Master’s program for training the next generation of semiconductor designers supported by SEMI Europe and STMicroelectronics. Outlining the project’s ambition, Cummings said, “The program has a broad curriculum, covering everything from silicon chips and SoCs to safety-critical software, how to run a team, and how to start a semiconductor business.” Victoria Cummings, Senior Manager, Workforce Development and EU Projects, SEMI Europe The focus then shifted towards engaging younger learners. Marco van Schagen and Tijl Bouman, co-founders of JuniorIOT, unveiled their newest workshop, Chips in Schools, which builds on their work to spark interest in electronics among younger students. During a hands-on demonstration, audience members of all ages were invited to examine LEDs under a microscope, learning how different chips can be identified and classified by function.The Chips in Schools workshop will soon be available on the ECSA e-learning platform as part of the ongoing collaboration between ECSA and JuniorIOT. Reflecting on the importance of early engagement, van Schagen noted: “When we talk about the talent pipeline, we need to ask where this pipeline really begins. For us, it’s so important that we reach out to children early to foster their sense of curiosity and discovery.”Marco van Schagen, Co-founder of JuniorIOT, demonstrating the Chips in Schools workshop with Victoria Cummings.Rounding off the session, Mike Glavin, Program Director for Workforce Development at the SEMI Foundation, spoke about efforts to significantly scale the foundation’s impact. He described how, despite hundreds of individual microelectronics education initiatives across schools and colleges in the United States, their collective impact has often been limited by fragmentation and a lack of coordinated promotion. To address this, Glavin introduced the National Network for Microelectronics Education (NNME), an initiative designed to unify and amplify existing programmes by connecting educators, students and regional partners. The goal, he explained, is to build scalable, sustainable talent pipelines: “We want to answer the questions, how do we train teachers to educate students about semiconductors? How do we connect to networks through which we can train educators at scale? And how do we develop resources so that a university can host its own semiconductor day, rather than requiring the SEMI Foundation to put it on?” Mike Glavin, Program Director for Workforce Development, SEMI Foundation From university labs to industry-aligned Master’s programs, the message at SEMICON Europa 2025 was clear: talent development is critical to sustaining Europe’s semiconductor ambitions. SEMI would like to thank its partners across academia and industry, as well as the vibrant community of ECSA Student Ambassadors, whose collaboration, commitment and creativity are helping to build a diverse, resilient talent pipeline and shaping the future of the global microelectronics ecosystem.SEMI Contact Jatin Mendiratta, Communications Coordinator, European Projects Email: [email protected]