SEMI members span the entire semiconductor manufacturing supply chain, representing diverse industry segments, product offerings, geographic regions, company sizes, and ownership types. The SEMI Member Directory serves as a key resource that showcases companies across the microelectronics value chain while helping to amplify their brands. We’re excited to announce recent enhancements to our member directory that include a refreshed design, improved search functionality, and more up-to-date company information.WHAT’S NEWClean Look FeelDefault “tile view” display of member companiesCompany profile pages with English and optional local-language contentAbility to display up to 48 companies per page viewSmart Search Functionality Searches scan all company profile descriptions, keywords, and location detailsSearches support all languagesIndustry-focused results limited to the semiconductor manufacturing supply chainMember Company Access Primary member contact can instantly update their company’s directory information, including:Business overviewCompany logo uploadAdditional search keywordsWHY IT MATTERSThe Member Directory averages 15,000-20,000 active viewers each month, providing a powerful platform to boost your company’s visibility within the industry. Combined with SEMI’s reputation and reach, it’s an effective way to be seen by the right audience.LOOKING AHEADWe’re not done yet. SEMI will continue to improve and enhance the directory with additional upgrades in the coming months. Check out the new directory and see the latest improvements. If your organization isn’t yet among our 3,000+ member companies, now is the perfect time to join our global community. Learn more by submitting a membership inquiry form or contact a regional office.Eric Thoe is Senior Director, Member Services at SEMI.

The semiconductor industry is grappling with a critical talent shortage, both globally and within the United States. At the same time, the workplace landscape for high school and college graduates is changing. These dual pressures present an opportunity: to cultivate early career awareness by introducing K–12 students to dynamic, real-world learning experiences that open their eyes to emerging industries—like semiconductors—and the meaningful roles they could play in them.Investing in this early exposure strengthens the long-term talent pipeline for the semiconductor industry and prepares students to meet the demands of a rapidly evolving workforce. However, realizing this vision requires intentional, cross-sector collaboration among educators, industry leaders, workforce boards, and policymakers.One example of this type of collaboration is the ChipWorks Series in Idaho. Boise State University partnered with Micron, the Idaho Workforce Development Council, and the Idaho Digital Learning Alliance to design, develop, and launch the learning experience for middle and high school students in 2024. The ChipWorks Series consists of three courses: Chip, Chip, Hooray!; Introduction to Electrical and Computer Engineering; and Materials Science and Engineering. With the first course launching in Fall 2024, the program has already reached over 220 learners across Idaho – and it’s just getting started. Camille Platts-McPharlin is the Project Manager at the Microelectronics Education and Research Center helping Boise State prepare to expand their programming to a national audience in 2025.The origin of the ChipWorks Series began through a grant with the Idaho Workforce Development Council. “The Council and Boise State University saw an opportunity to address the growing workforce gap by building a pipeline that begins in middle school and goes through adulthood,” said Platts-McPharlin. Development began in 2023 and was shaped by more than 300 voices from industry, academia, and K–12 education. This cross-sector group of stakeholders worked collaboratively to ensure that the lessons were responsive to real-world industry needs and compatible with classroom delivery best practices. Furthermore, the courses are aligned with State and National learning standards as well as ABET standards. Overcoming logistics challenges around open-source resources and existing structures in formal education led to two of the programs being dual credit, setting high school students up for early success in post-secondary. There has been an enthusiastic response from learners across Idaho, and more learners are expected to engage this year, as the third and final course is launched in the fall. Students enroll at their home school, have the support of local teachers, and receive online instruction synchronously from a dedicated teacher through the Idaho Digital Learning Alliance. This model enables a broader group of learners to access the training, regardless of educator understanding of the content. Students learning ChipWorks Series lessons at Micron Chip Camp.The ChipWorks Series is now expanding its reach beyond Idaho. In collaboration with Micron, Platts-McPharlin and the MERC team are working to bring the courses to students in New York. Educators from Syracuse and surrounding districts participated in a week-long professional development event to learn the curriculum and begin the work of bringing it into their local school districts. Teacher training for educators from Idaho and New York. Platts-McPharlin offered words of wisdom for other educators, training providers, or partners who are trying to create industry awareness opportunities earlier in the learning journey. “The key to success is listening closely to stakeholders and balancing the various perspectives. This will result in a quality product,” she said. Her other suggestion: trust the process. While it was challenging to build entirely new programs, the impact it is having on students, their teachers and their families to make them aware of their potential is immense. Programs like ChipWorks offer a powerful solution to the semiconductor industry’s workforce crisis, but they cannot stand alone. For sustained progress, industry leaders, workforce development councils, and educational institutions must work together to co-design scalable, inclusive solutions. This means sharing expertise, investing in infrastructure, and championing long-term talent development—starting in the earliest years of education. For more information on the ChipWorks Series, or to learn how to bring it to your students, please contact Camille Platts-McPharlin: [email protected]. To learn about what the SEMI Foundation is doing to bring together cross-sectoral groups for similar projects, contact Anissa Hamdon-Morison: [email protected] Hamdon-Morison is Training and Curriculum Manager at SEMI Foundation.

The semiconductor industry faces an unprecedented paradox: AI demand is booming, fab investments are rising, yet wafer shipments remain stubbornly flat. What's driving this disconnect, and when will it break?As of mid-2025, the global silicon wafer market appears calm on the surface, but underlying structural tensions are quietly mounting. The demand for AI semiconductors remains resilient, and certain high-value supply chains continue to operate near capacity. Yet wafer shipments have shown little sign of meaningful recovery—a divergence that raises questions about the conventional supply-demand playbook.SEMI's latest Silicon Wafer Market Monitor Report begins with a structural hypothesis: that the current market dynamics cannot be explained solely by weak demand or delayed orders. Instead, we propose that the demand pattern of fab operations itself has fundamentally changed.The Hidden Constraint: Time ExtensionOne critical metric has emerged as a structural bottleneck—fab cycle time, or the average duration for a wafer to complete its full process flow. Our quantitative analysis reveals that since 2020, fab cycle times have grown at a compound annual growth rate of 14.8%. This represents a fundamental deceleration in fab throughput, meaning that even with the same number of tools and consistent utilization rates, the volume of wafers that can be processed is now structurally constrained.Why is this happening? Rising process complexity, increased equipment density, and tighter quality control requirements are absorbing more capital per wafer while paradoxically slowing production. Equipment spending per wafer area has surged over 150% since 2020, yet this investment translates into longer processing times rather than higher throughput.The High Bandwidth Memory (HBM) Economic ThresholdSimultaneously, the market is approaching a new inflection point driven by the rapid rise of HBM. HBM wafers consume over three times more wafer area per bit compared to standard DRAM, creating potentially significant wafer demand. However, HBM currently accounts for just 16% of total memory revenue—still below a critical economic threshold.Our analysis identifies that when HBM reaches 25% of total memory revenue, the trade ratio rises to 1.5. This is the structural breakeven point where CapEx per wafer for HBM-dedicated lines aligns with standard DRAM economics. At this threshold, memory makers gain clear incentives to expand wafer input, and customers become more willing to pay premium prices.The Quantitative FrameworkInstead of relying on conventional forecasts, we model the interaction of four critical variables—HBM penetration, DRAM bit growth, fab utilization, and cycle time—using a quantitative simulation framework. Under current conditions (16% HBM revenue share, 15% annual bit growth, 95% fab utilization, and 14.8% cycle time increase), wafer input would need to increase by 23.9% annually to meet projected demand.Yet no fab is scaling wafer input to that extent today. This suggests the market isn't demand-constrained but operating within a conditionally responsive system—one that won't activate until key thresholds align.Beyond Economics: Technical and Operational ReadinessThe slow pace of HBM expansion isn't solely about investment timing. Technical constraints including low yields, delayed customer qualification, and process stabilization challenges also play critical roles. These preconditions—investment readiness, yield optimization, and qualification completion—haven't yet aligned, keeping the market in strategic latency despite robust underlying demand.Additional factors compound this delay. Backend bottlenecks in Chip-on-Wafer-on-Substrate (CoWoS) packaging are causing semi-finished wafers to accumulate as inventory, constraining upstream wafer input. At the fab level, companies prioritize efficiency gains through process conversions over new construction. Meanwhile, macroeconomic uncertainty, geopolitical tensions, and foreign exchange volatility continue suppressing capital execution.The Three-Tier Response ModelThis structural shift creates a three-tier demand response across the supply chain:Wafer demand: Conditionally responsive, awaiting economic threshold alignmentEquipment investment: Process-transition driven, already responding to complexity increasesMaterials demand: Directly tied to cycle time extensions, with potential for early bottlenecksFor certain process-critical materials like EUV photoresists and TSV chemicals, supply constraints may emerge even before wafer input fully ramps, preceding equipment expansion.Strategic ImplicationsFor industry stakeholders, this analysis suggests three key actions: wafer suppliers should prepare scenario-based capacity plans around the 25% HBM threshold; equipment makers should anticipate process-transition driven demand regardless of current wafer volumes; and materials suppliers should prepare for potential bottlenecks as extended cycle times increase consumption per wafer.Crucially, the current stagnation shouldn't be interpreted as structural decline. Rather, the market exists in a state of strategic readiness, with key conditions not yet aligned. Once they are, wafer demand will likely respond nonlinearly—and momentum is already building in that direction.The structural inflection point (≈25% HBM penetration) and cycle time increase (+14.8%) serve as forward-looking indicators not just for wafer producers, but for the entire upstream supply chain. The question isn't whether this inflection will occur, but when. Companies that understand these structural dynamics and prepare accordingly will be best positioned to capitalize on the nonlinear demand response when it arrives.These key insights are from the market update section of the Q2 2025 Silicon Wafer Market Monitor Report. This quarter's analysis models structural inflection points using scenario-based projections across nine core charts and tables, offering data-driven perspective on the industry's readiness for the next demand shift. Download your free sample report today.For more information on the report or to subscribe, please contact the SEMI Market Intelligence Team at [email protected]. Details on the complete SEMI market data portfolio are available at our Market Intelligence website. Sungho Yoon is a Principal Analyst in the Silicon Wafer Market Research at SEMI Market Intelligence.

Electronic Design Automation (EDA) financial analyst Jay Vleeschhouwer, Managing Director of Software Research at Griffin Securities, carefully tracks the design portion of the semiconductor industry and offers insightful analysis used by this community. He also presents the State of EDA, a yearly report on EDA, during the Design Automation Conference (DAC). After this year’s presentation, he and I talked about trends, the difference between EDA and Architecture, Engineering, and Construction (AEC), security and chiplets. A condensed version of our talk follows. Smith: Now that the Synopsys-Ansys merger closed, what changes? Vleeschhouwer: Synopsys is now the largest company by revenue and backlog in all of Engineering Software, a well over $30-billion industry, including all the parts of that market—AEC, EDA and Technical Software. The pro-forma backlog, about $9.84 billion as of the most recently reported quarter, is the largest in the industry. An important question is how will Synopsys integrate, employ and leverage the four-fifths of Ansys that is not strictly EDA? That is, other than Ansoft and Apache, the two entities that mostly comprise Ansys' EDA, and that ties into the convergence theme. Also, the question in any acquisition is the balance between leaving the operations and the portfolios as they were, or not. In other words, let them continue doing what they were doing if they were doing it well or quickly absorbing, integrating and leveraging those portfolios into the buyer's portfolio. That roadmap is something that we would be interested in hearing more about in terms of its purely EDA aspects and as well the convergence aspects.Smith: Have you observed any new trends in 2025 that surprised you? Vleeschhouwer: The short answer is that it's more of the same in terms of the main technical and business trends. Of course, the most recent important exogenous effect is the advent of tariffs and new export restrictions, or the variability around export restrictions. That's perhaps the main thing that's occurred in the last few weeks and months. We're seeing a continuation of trends that have been in place for a number of years in terms of many of the technical and business results that we've highlighted in our reports. From industry data, there continues to be multiple EDA categories that are continuing to grow. It’s observable and important that we see this breadth of product adoption and growth across multiple categories. This has been beneficial to each of the four largest EDA companies. There have been compelling technical reasons for this, and I would expect it to remain the case. In terms of those significant multi-year trends, the answer would be no. Otherwise, in terms of 2025 specifically, the thing that was interesting about this year’s DAC was the presence of more startups, something that we've not seen in EDA for a long time. It's interesting that we are seeing startup activity not only in EDA, but even in one of the other areas of Engineering Software that we cover: AEC has little to do with semiconductors and electronic systems and it too has more startup activity than we've seen for about a quarter of a century. Although the rationales for the startups in these two different areas of Engineering Software are quite different. The rationale for the EDA startups is one set of rationales, whereas in the case of AEC, it's different, which to me is analytically interesting. Smith: What is the difference between the rationales for startup activity in EDA and AEC? Vleeschhouwer: AEC has to do with the design and construction of commercial buildings, residential buildings, infrastructure, meaning roads, bridges, airports, tunnels, civil engineering, public works. Among the companies that we follow in those markets are Autodesk and Bentley Systems. Autodesk has a small connection to EDA because one of their mechanical CAD products has some integration with some PCB design tools. In any case, the rationale for startups in AEC that we've seen has mostly to do with what has been some vocal dissatisfaction with the incumbent or large incumbent products. That's different from EDA, where we can’t make a case that there is dissatisfaction or sufficient dissatisfaction with the incumbent tools that would necessitate, or be a catalyst, for startups. What we're seeing here is the ongoing, complex, rapid evolution of semiconductor design and electronic systems design because of the unusual breadth of EDA tools and functions, far more so than in AEC. There's much more opportunity for niche products to perhaps complement existing tools. As you know, it can be difficult to dislodge an existing tool in EDA. The industry has become consolidated among the big four—Ansys, Cadence, Siemens EDA and Synopsys—and now three with Synopsys/Ansys merger. Backlogs have continued to grow and book-to-bill has been positive for 15 years. It’s hard to infer any dissatisfaction with incumbent tools or insufficient satisfaction showing up in the numbers. Whereas in AEC, it's different in terms of the profile of the customers or the way the tools are used. There are far more customers than in EDA—thousands upon thousands of architectural firms and construction firms and so forth. The installed base of the AEC software is an order of magnitude more than in EDA. It just so happens that there was one tool from Autodesk that has been getting considerable attention from customers in terms of how modern it is and so forth. This created an opening for some startups. Notwithstanding the nominal dissatisfaction with this tool, however, that particular brand continues to grow. It has the largest base in the industry. At the end of the day, the largest product of its kind in the market continues to grow at a decent rate. The vendor in this case, Autodesk, has acknowledged some of the things needed to do to improve the tool, and it's investing toward that. In any case, there are differences in why these startups exist, how they're approaching the market.Smith: The big topics now are 2D and 3D and chiplets. Where is the market relative to chiplet-based design? Vleeschhouwer: It’s still early, based on commentary from the EDA vendors, about developing and delivering the tools. I don't have a precise measure as to how much of the business is attributable to it. It’s still something that has a considerable runway, which is a good thing. As more tools that can enable it come together, then we'll continue to see this cycle of enablement and delivery. That phenomenon will continue to grow. We would love to hear the vendors’ provide more precise attribution in terms of how much of the business is coming from this. For investors, it will be incumbent upon the vendors to be more explicit about the contribution from the new technical phenomena because it is a new growth catalyst. Smith: The ESD Alliance is starting to see more interest in securing the design flow. This is a huge issue. The design flow is more complex and it's going to require cooperation, collaboration and new standards. Vleeschhouwer: Yes. Siemens EDA is the largest in classical product lifecycle management (PLM) or managing the whole process, an important issue for the industrial and manufacturing markets with its Teamcenter product. Interestingly, Siemens EDA still has work to do to integrate Teamcenter with Calibre, which would seem to have been a natural thing to have done, and I think still is. Teamcenter and Calibre are the two billion-dollar brands that Siemens Industry Software has as an entity. Calibre is by far the predominant product of its kind for semiconductor manufacturing. It's got at least two-thirds market share. Teamcenter is the market leader in classical PLM. The connection between those two brands, owned by the same company, would be an interesting executable to observe.About Jay Vleeschhouwer  Jay Vleeschhouwer, Managing Director of Software Research at Griffin Securities, has more than 40 years of research analyst experience in the technology sector, including software, semiconductors and computer hardware. Vleeschhouwer does a yearly presentation on the State of EDA during the Design Automation Conference (DAC). The slides can be found at: DAC presentation (June 2025) 2.pdf Note: The ESD Alliance will host a three-hour design track “The Convergence of Semiconductor Manufacturing and Design” Tuesday, October 7, from 1 p.m. until 4 p.m. during SEMICON West in Phoenix, Ariz. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

“In today's ever-evolving professional landscape, empowering women and fostering their success is not just necessary—it's essential," said Caryn Veach, a long-time Women in Semiconductors (WiS) committee member. Veach is a strategic account manager at Kokusai Electric Corporation, which sponsored the WiS program in Albany, New York in May. Additional sponsors included Axcelis, Energetiq (a Hamamatsu Company), IBM, Nikon Precision and Onto Innovation.This year’s WiS theme, "Empowerment in Action: Real Strategies for Women’s Success," was designed to provide all attendees with actionable strategies to support women's career growth and representation, as well as lead to greater talent retention and workforce stability. The program, which was open to everyone at the co-located SEMI Advanced Semiconductor Manufacturing Conference, was co-chaired by Joy Racowski, PhD., Strategic Account Sales Engineering Manager - Delivery Systems Services at EMD Electronics and Rosanna Robert, ES Process Engineer ll at TEL Technology Center America.Keynote speaker Jennifer Lynn, Cybersecurity Leader and Research Security Program Manager at IBM Semiconductors emphasized the significance of community in driving change. She stressed the role of Employee Resource Groups (ERGs) as a collective voice to advocate for safer and welcoming workspaces where all individuals feel respected and valued. Some key takeaways from Lynn’s address: champion supportive career initiatives, become a mentor or find a mentor, and be an ally in support of peer success. Shari Liss, Vice President of Global Workforce Development and Initiatives at SEMI, moderated a panel which also highlighted real strategies for women’s success. Panelists from EMD Electronics, Entegris, TEL Technology Center of America and University at Albany focused on actionable strategies which everyone, not only women, can implement to navigate corporate environments. They encouraged WiS participants to challenge norms which penalize specific employees. Panelists invited attendees to discover and embrace what makes them unique and use that as a strength for themselves as well as others. (l-r) WiS panel: Shari Liss, SEMI; Jennifer Braggin, Director, Technology, Office of the CTO, Entegris; Daniel Drellich, Managing Director Sr. Vice President of Business Partnering, EMD Electronics; Kathleen Dunn, PhD, Professor of Nanoscale Science and Engineering, University at Albany; Alex Oscilowski, President, TEL Technology Center AmericaImposter Syndrome is a common challenge to women and those who are new in their career or leadership role. Panelists advised everyone to push through it and support others who might feel this way. Assertiveness is an area which should be seen as a strength rather than a disadvantage, especially for women; it’s important that different voices and opinions are heard. Finally, panelists urged everyone to give credit where it is due and actively support team members and peers.The program concluded with an interactive workshop facilitated by Debbie Gustafson, CEO of Energetiq Technology. Attendees were invited to craft an elevator pitch which could be used when networking or applying for a new job or position. Common elements of a pitch include a concise description of oneself, a unique value proposition and a call to action for one’s audience or employer. WiS was an empowering experience with excellent opportunities to network with female business leaders from around the country as well as recent college graduates and industry professionals from major semiconductor manufacturers. There is something uniquely impactful about coming together with other women and peers who understand the challenges and opportunities of our industry. These events create space for honest conversations, meaningful networking, and a sense of community. It is a reminder that that together we can drive change and support one another in powerful ways. Through grants from the W.K. Kellogg Foundation and the David Lucille Packard Foundation, the SEMI Foundation is expanding Women in Semiconductors programming to several regions around the country. In addition to an event in San Jose, California there will be programs in Arizona, Michigan and Ohio in the second half of 2025. For information on WiS in Michigan, visit https://semiscan.org/event/women-in-semiconductors/.Empowering women in the workplace requires persistent effort and community support. By embracing these strategies and advocating for necessary changes, organizations can pave the way for a more equitable future. And just like the Kokusai Electric embrace of Tai-wa, a Japanese word meaning "synergistic discourse", WiS encourages face-to-face conversations and a willingness to understand others with a sense of empathy and respect for everyone.Margaret Kindling is Senior Program Manager at the SEMI Foundation. She has promoted inclusive workplaces via initiatives like WiS, Semiconductor PRIDE and workforce development programming at SEMICON West, SEMICON India and SEMIEXPO Heartland. After a combined 37 years at SEMI and the SEMI Foundation, she will be retiring in August 2025.

In Q2, the SEMI International Standards Program made progress on several emerging initiatives. Together, we reached a critical milestone for one of our data standards initiatives with Document 6938C recently passing Technical Committee review in mid-June 2025. Ballot 6938C, which provides guidance on how to identify manufacturing equipment data provided by the equipment supplier that can be used in equipment engineering or analysis applications, is slated to join SEMI E190 and E190.1 in providing industry-enabling data standardization.In addition, we began major revisions to SEMI Standards S2, S8, and S10. These standards govern environmental, health, and safety (EHS) considerations, equipment user fatigue and injury reduction, and equipment risk assessment and evaluation, respectively. In our recently concluded North America Standards Summer 2025 Meetings, the NA EHS Technical Committee Chapter approved a revision ballot to SEMI S10. The ballot (7169) proposed several major revisions to the SEMI S10 Safety Guideline on risk assessment which included changes to references to equipment to objects under consideration. Other changes also included the relocation of the assessment of the risk of harm to property other than the OUC to a Related Information section. Additional details are provided below.We’re eagerly preparing for this year’s SEMICON West event, taking place for the first time ever in Phoenix, Arizona. We are also pleased to announce the return of the SEMI Global Standards Summit taking place Tuesday afternoon, October 7 at SEMICON West. Our inaugural Summit was held last year at SEMICON Japan 2024 last December. The Summit aims to identify standards-critical areas and work towards an industry standardization strategy for the next 3- and 7-year time horizons. This year's Global Standards Summit will feature sessions on Supply Chain Traceability as well as Environmental Sustainability. Similarly, as cybersecurity considerations become more complex, SEMICON West will host a dedicated Cybersecurity Forum from October 7-9 to address today’s most pertinent challenges. More detailed program information will be available soon. Finally, we’re looking forward to our SEMI Standards + Award Ceremony Networking Event at SEMICON West. Following the International Standards Meeting and Standards Summit on Tuesday, October 7, join us for appetizers, drinks, and great conversation from 6-7:30 p.m. In the meantime, learn more about becoming a member of the SEMI International Standards Program.Balloting for Document 6938Document 6938C introduces a new potential standard – Guide for Equipment Edge Data Governance. Under development by the Equipment Edge Data Governance (EEDG) Task Force since 2021, Document 6938C was balloted in Cycle 3-2025 and approved during the Information Control Taiwan Technical Committee (TC) Chapter meeting held on June 12, 2025. It has since received approval by the International Standards Committee Audits and Reviews Subcommittee and is now undergoing final processing for publication by SEMI. As manufacturing equipment offers more accessible data than ever, poor communication, inconsistent expectations, and data security concerns continue to halt or slow factory integration efforts. If passed, this new standard will help organize the information that supports smart manufacturing efforts at the edge. In addition, the EEDG Guide will provide a comprehensive set of best practices to both users and suppliers to increase the value of existing equipment data. Update on Revisions to SEMI S2, S8, and S10 Safety GuidelinesOur 2025 Q1 Standards Watch newsletter announced a significant overhaul for SEMI Standards S2, S8, and S10.S2, SEMI’s standard for performance-based environmental, health, and safety (EHS) considerations for semiconductor manufacturing equipment, is undergoing discussions on redefining safety interlock systems. The S2 task force will issue an informal ballot to the general audience for feedback. The results then will be used to develop a formal letter ballot.First developed in 1995, SEMI Standard S8 works to reduce fatigue and injury by matching equipment to the user’s size, strength, and range of motion. Although this safety standard has been periodically updated since its inception, its last substantial revision was in 2018. The ballot to revise S8 ultimately failed the EH S TC Chapter review at this year’s Winter Meeting. With 214 comments and negatives to consider, the task force is revising the ballot and plans to reissue in Cycle 7 of August 2025.Finally, SEMI Standard S10 is moving through ballot 7169. This standard defines a consistent means of risk estimation that other SEMI Safety Guidelines can invoke. Ballot 7169 will separate facility and building risk assessment to a non-normative portion of the document, ensure EHS risks are separately calculated from commercial object risks, and clarify risk assessment of observed events from risk assessment of foreseen events. Ballot 7169 results were reviewed on June 5 during the North America Standards Summer meetings. The document was approved and is being processed for publication by SEMI.Cybersecurity Forum at SEMICON West 2025This year’s SEMICON West will feature a dedicated Cybersecurity Forum to address the semiconductor industry’s rapidly-changing cybersecurity landscape. The SEMI Cybersecurity Forum will gather industry experts to share knowledge and experience on the following topics. The goal is to develop actionable strategies and a deeper understanding of current and future cybersecurity risks. Cybersecurity in Legacy Semiconductor ToolsEmerging and Existing Cybersecurity Legislation and ComplianceCybersecurity in Maintenance and ManufacturingImpact of Cybersecurity Events on Semiconductor Manufacturing OperationsSupply Chain SecurityThreat Landscape in Semiconductor ManufacturingThe 2025 call for abstracts is now closed. Speakers will be announced in Q3.SEMI E187 Compliance Guidance White PaperThe SEMI Semiconductor Manufacturing Cybersecurity Consortium (SMCC), in collaboration with industry experts, is pleased to announce the release of the SEMI E187 Compliance Guidance Whitepaper. This comprehensive resource is designed to support semiconductor equipment suppliers and device manufacturers as they work to meet the requirements of the SEMI E187 0122 Standard - The Specification of Cybersecurity of Fab Equipment.Professionals involved in tool development, manufacturing, operations, and security will find the guidance particularly relevant and actionable. It provides guidance to address all twelve SEMI E187 requirements and focuses on new to fab equipment.Download the Whitepaper for freeSEMI Standards North America Summer MeetingsThis year’s SEMI Standards North America Summer Meetings were held from June 2-5 at SEMI’s headquarters in Milpitas, California. The meetings convened 11 committees and 40 task forces to discuss topics ranging from EHS to facilities, 3D packaging, MEMS, and more. In addition to the results of ballot 7169, technical changes to ballot 6601B, New Standard: Guide for Meeting IRDS Yield Table Recommendations for High Purity Polymer Materials and Components Used in Ultrapure Water, was also approved by the Liquid Chemicals North America TC Chapter, since the activity began in 2019. A Ratification Ballot will be issued in Cycle 7-2025 to verify the changes. In total, over 15 activities, ranging from Auxiliary Information, Reapprovals, and Line-Item ballots, also recently passed Procedural Review by the International Standards Committee (ISC) Audits Reviews Subcommittee and will be forwarded to Publications for final processing. The next SEMI International Standards Meeting will be held at SEMICON West from October 7-9 at the Phoenix Convention Center. Some technical committees and task forces may meet virtually outside of this meeting set, so be sure to check the SEMI Standards calendar of events for updates. Standards Introduced in Q2 2025New and revised standards released in Q2. April 2025 standards: https://store-us.semi.org/collections/standards/stdpbc-0425May 2025 standards: https://store-us.semi.org/collections/standards/stdpbc-0525June 2025 standards: https://store-us.semi.org/collections/standards/stdpbc-0625Get InvolvedSEMI Standards development activities take place throughout the year in all major manufacturing regions. To participate, join the SEMI International Standards Program.SEMI Standards are available through individual download purchases or online via SEMIViews. Sign up for a 30-day SEMIViews trial.For more information, please visit the Standards website and events page. For any questions regarding SEMI Standards activities, please contact your local SEMI Standards staff. Paul Trio is Director of Standards at SEMI.

The SEMI Foundation is undertaking a bold, novel approach to ensuring that the semiconductor industry has the skilled talent it needs to thrive. With a $40 million initial award from the U.S. National Science Foundation together with the U.S. Department of Commerce, and up to $160 million additional funds over the next five years, we have launched the National Network for Microelectronics Education (NNME), which is designed to reshape the landscape of microelectronics education and industry career awareness. The NNME is a federal effort to develop, connect and multiply workforce development activities throughout the nation to meet the needs of the semiconductor industry. The SEMI Foundation now serves as the Operating Hub of the NNME and will support large, multi-state regional coalitions of workforce development performers, called Regional Nodes. Collectively, the Hub and the Nodes will work to transform semiconductor industry training and awareness to provide pathways toward economic opportunity for American workers, and to provide industry the workforce it needs to grow to $1 trillion by the early 2030s.Join the NNMEOn July 16, 2025, we will begin accepting Letters of Interest (LOI) from institutions interested in leading or joining a Regional Node. Read on and visit www.nnme.org for more details.The ChallengeThe semiconductor industry has layered workforce development challenges, including: Greying workforce, with 30% of our workers over 50Aging infrastructure and a significant instructor shortageMicroelectronics curriculum that is often outdated and not aligned with industry needs, leading to critical gaps in learner knowledgeNo standardization of microelectronics learning across the fieldDuplicative and disconnected educational efforts nation-wideAn industry largely invisible to many students and jobseekersThe new industry investments spurred by the CHIPS and Science Act mean tremendous economic opportunity for more workers, bolstered American manufacturing, and a stronger U.S. microelectronics sector. None of this can be fully realized without a much larger and highly skilled workforce trained in today’s and tomorrow’s technologies.There have been numerous local, state, and federal workforce development initiatives to address some of these issues, and highly successful programs in various regions; but these have never been connected in a systemic way. This means people and institutions across the country are working separately to solve a collective problem. The NNME will connect and support these efforts, facilitate cross-regional learning, and braid together resources to illuminate the industry to students and jobseekers nationwide.The Solution“Talent is infrastructure,” said Shari Liss, Vice President of Global Workforce Development and Initiatives of SEMI. “We need skilled and job-ready talent at all educational levels to power the semiconductor industry. We have been working for years with educational and workforce leaders to design this national collective effort and we are thrilled to finally launch this transformative work.”The NNME is designed not as a series of isolated interventions, but as a cohesive, forward-looking national strategy. Grounded in the realities of a high-growth industry and an underprepared workforce system, NNME’s goals respond directly to the needs expressed by semiconductor employers, policymakers, educators, and learners. The NNME will:Design, develop, modernize, and disseminate industry-aligned curricula and share best practices across the networkDevelop regional partnerships and local workforce pipelines including colleges, universities, workforce development programs, labor, community-based organizations, and industry to create a national technical workforce that meets the evolving needs of industryFacilitate apprenticeships, internships, and other applied learning experiencesBuild, host, and update an open-source digital portal that houses the updated industry-aligned curricula for adoption in training programs nationwideConduct a major industry awareness, microelectronics education, and career opportunity campaign including PreK-12 schools and STEM organizationsThe NNME will be comprised of the Coordinating Hub (operated by the SEMI Foundation) and Regional Nodes which will be funded by the Hub. Regional Nodes will be comprised of workforce development performers – industry members, academic institutions, training providers, community-based organizations, and more. Collectively, the Hub and Nodes will execute the above activities with a commitment to information sharing and collaboration, transparency, responsiveness and agility, excellence, and accountability. Finally, the NNME is committed to expanding access to microelectronics careers for Americans from every region and walk of life. NNME initiatives are designed to open doors to technical training and career exploration for high school students, veterans, people returning to work, college students, and others seeking high-quality jobs in this critical industry, as well as provide opportunities for current professionals looking to grow their careers. Call for ParticipationThe SEMI Foundation is soliciting LOIs for performers interested in leading or joining a Regional Node. Information on node requirements and performer eligibility can be found on the NNME website at www.nnme.org. The solicitation goes live on Wednesday, July 16. An informational webinar will be held on Wednesday, July 23, and LOIs will be due on Friday, August 8 at 5 p.m. EDT. The NNME envisions a future in which every American, regardless of where they live or how they start their journey, can pursue a rewarding, well-paying career in microelectronics. The NNME will be instrumental in helping to build a robust and vibrant semiconductor industry by fueling it with a wide range of skilled workers and creating a broad pipeline of future talent. Our intention is to serve as the nation's premier resource for microelectronics education and training, connecting learners to employers, programs to successful outcomes, and empowerment to opportunity. We invite industry members and other workforce partners to join us in this work. Together, we will strengthen the talent pipeline that powers American leadership in semiconductors and advanced manufacturing. For more information, contact us at [email protected] or visit www.nnme.org. Michelle Williams is Executive Director at the SEMI Foundation.

The future of technology depends on cultivating a strong and skilled talent pipeline. According to McKinsey Company, the global semiconductor industry could grow to $1 trillion by 2030, driven by surging demand across sectors like automotive, consumer electronics, AI, and clean energy technologies. That’s why the SEMIquest Pop-Up Exhibition at SEMICON West, October 8-9, 2025 in Phoenix, AZ, will bring the semiconductor story to life through immersive, hands-on learning experiences for students, educators, families, and the general public.What Is SEMIquest? SEMIquest is an engaging, interactive experience designed to introduce students in grades 7-12 to the world of semiconductors. The program features hands-on activities, direct interaction with industry professionals, and workshops for educators aimed at highlighting the essential role semiconductors play in everyday life and future career opportunities. Key Program Components:Students trying on NXP bunny suits at Semiconductor Adventure DayIndustry Engagement – Offering students the opportunity to interact with industry through the interactive exhibition space.Hands-On Activities – Highlighting careers in semiconductors and promoting STEM education for students.Educator Engagement – Offering teachers training and resources to carry lessons back into their classrooms.Field Trip to SEMICON West 2025 – Providing students an opportunity to attend SEMICON West 2025 at the Phoenix Convention Center in Arizona, with complimentary admission and curated tours that offer a behind-the-scenes look at the global semiconductor industry.Students from ASU Preparatory Poly Tech Campus Participating in Semiconductor Adventure Day and event led by the Semi Foundation and ASU PreparatoryThe program culminates in an on-site learning experience at the Arizona Science Center, located adjacent to SEMICON West 2025—where students can explore exhibits, engage with companies, and witness the semiconductor ecosystem firsthand.Projected Reach: In its inaugural year, SEMquest aims to engage 500-1000 students in grades 7-12, with a national expansion plan already in motion.Impact Goal: Reach 60,000 families and students during a 4-month Pop-Up exhibition in Arizona through targeted programming and outreach.Why This Work Matters: The Semiconductor Industry Needs TalentSemiconductors are the foundation of modern life—from smartphones to satellites, healthcare tech to AI applications, and more. Yet, many students are unaware of what semiconductors are or how to pursue a career in the field.The Semiconductor Industry Association (SIA) estimates the U.S. could see a shortfall of 67,000 skilled workers by 2030 in key roles that require postsecondary education.A 2023 Deloitte report warns of a global shortfall of 1 million skilled workers in the semiconductor industry by 2030 if proactive steps aren’t taken.Semiconductor Research Corporation 2023 findings indicate that while 577,000 students pursue four-year STEM degrees annually, only about 19,000 enter the semiconductor industry each year. This disparity underscores a significant gap between STEM education and semiconductor industry employment.SEMI's American Semiconductor Academy (ASA) Vision Paper highlights the importance of raising student awareness through educational and industry collaboration, offering hands-on experiences and real-world applications.Image Source: Photo courtesy of SRC (Semiconductor Research Corporation).The SEMIquest Pop-Up Exhibition tackle this urgent gap through meaningful engagement, accessibility, and experiential learning—helping students envision themselves as future leaders in the field.What Sets SEMIquest ApartReal Industry Involvement – Students interact directly with professionals, tools, and environments used in the field.National Scalability – While beginning in Arizona, the program is structured for national rollout.Cross-Sector Collaboration – A unique fusion of education and industry.Integrated Learning Model – Teachers and students learn together, amplifying classroom impact.Join the Movement: Shape the Future of InnovationWe’re calling on partners across the country to join this work. Whether you’re an industry leader, educator, or community-based organization, your involvement is essential to inspiring and preparing the next generation of innovators.Industry Partners – Showcase your work, engage directly with students, and contribute resources to the traveling Semiconductor Pop-Up Exhibition.Schools Educators – Bring your students, co-host hands-on workshops, and integrate real-world tech experiences into your curriculum.Foundations Funders – Support the expansion of this scalable model and help bring it to communities nationwide.Join us at SEMIQuest! To get involved or learn more, contact Perla DeBaggis at [email protected]. Perla DeBaggis is Sr. Specialist, Career Industry Awareness at the SEMI Foundation.

On July 7, President Trump issued an executive order (EO) extending the ten percent baseline tariff rate through August 1, 2025. In addition, the EO suspends the variable "reciprocal" tariffs imposed under the International Emergency Economic Powers Act (IEEPA) until August 1. The order applies to nearly all countries except Mexico, Canada, and China. These changes do not impact separate reciprocal tariff actions on China or alter existing Section 232 measures on steel, aluminum, autos, and their derivative products. At the time of this posting, letters had been sent to 20 trading partners outlining expected tariff rates if no agreement is reached by August 1; bilateral negotiations are ongoing. Eleven of the 21 countries received rate cuts compared to the "Liberation Day" announcements on April 2, ranging from one to 13 percent. President Trump indicated rates could rise around 25 percent if trading partners retaliate. Next Steps: The extension offers short-term stability for SEMI member companies to assess supply chain exposure. SEMI continues to monitor bilateral trade and tariff policy negotiations, including for discussion related to the semiconductor supply chain. We aim to keep member companies informed of relevant tariff escalations. If your company is directly impacted by a country-specific rate shift, please reach out to your region’s SEMI Global Advocacy contact with any feedback on how these tariffs are affecting your operations.Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Scarlett Bickerton, Manager, Federal State Affairs at SEMI.

Under the Greenhouse Gas Protocol (GHGP), all companies are required to calculate and report their emissions, including those of all members of their downstream and upstream supply chains. These are called Scope 3 emissions, and are divided into 15 Categories, including Category 11 - Use of Sold Products, a heavy lift for many small (and often large) companies. Measurement and improvements in vendor Scope 3 emissions are already influencing vendor selection and sourcing decisions, and experts agree that this will continue to increase. Upstream suppliers have typically relied on broad GHGP guidance to follow in making their calculations. For the semiconductor sector, and its well-documented, incredibly complex supply chain, there was no guidance accounting for the nuances within the industry to standardize calculations. Work began a year-and-a-half ago to change that.The Semiconductor Climate Consortium (SCC)’s Scope 3 Working Group compiled, verified and published a guidance document for calculating Scope 3, Category 11 emissions. The guidance document helps standardize emissions reporting and calculation methods and accounts for the unique requirements and circumstances of the semiconductor value chain.The SCC 3.11 guidance explicitly highlights where it maintains consistency with the existing guidance (e.g., GHG, SBTi, US EPA) and where it expands on that guidance to close a gap relevant to one or more of the semiconductor industry segments. The document was developed with the help of the Sustainability Consulting Group ERM, as well as excellent participation from the Scope 3 Working Group members, including representation from every segment of the semiconductor value chain from IDMs to foundries, fabless companies, chemical gas and materials companies, OSATS, and equipment manufacturers.Some of the significant areas considered while compiling the guidance included:Boundaries, especially around products and direct use-phase emissionsProduct lifespan, especially across the different sectors of the value chainMarket based emissions guidanceIncorporating grid decarbonization into the inventory and calculationsThe document includes several useful calculation examples, including direct use phase emissions and direct and indirect energy consumption. The examples help to make the guidance more tangible and practical in real world application.We were pleased to collaborate with our industry colleagues on developing this guidance as we work to align with others in the industry and minimize our reporting via efforts by the SCC. Download the Guidance Document.For further insights into the Guidance, the authors, including experts from ERM recently hosted a webinar. Register to watch the recording. Sara Turner is Climate Program Manager at Lam Research, and Mike Halblander is Product Marketing Manager at Teradyne. Both Turner and Halblander lead the SCC’s Scope 3 Working Group.