Manufacturing is a cornerstone of U.S. national security and economic prosperity, supporting jobs, growth, and global competitiveness. Within this ecosystem, the U.S. semiconductor industry holds a uniquely critical role, powering the advanced technologies that form the backbone of the modern world. Realizing the full potential of American manufacturing, however, depends on a policy environment that encourages investment and innovation. The pro-growth, competitive, and predictable tax policies in President Trump’s Working Families Tax Cuts (WFTC) are therefore essential to sustaining global leadership of the U.S. semiconductor industry. SEMI welcomes the Administration’s signing of the “One Big Beautiful Bill” and delivering a pro-investment tax framework that accelerates domestic investment and strengthens the American semiconductor industry’s global competitiveness. Demand for semiconductors is rapidly increasing, driven by critical applications such as artificial intelligence and quantum technologies that are integral to American innovation and national security. Meeting this demand requires billions in capital investment across the comprehensive supply chain, making tax policy a key factor in investment decisions. Policies such as the WFTC’s permanent extension and doubling of immediate expensing for qualifying equipment and software provide a significant advantage for companies building, maintaining, and supporting American chip-making. Likewise, by making 100% bonus depreciation permanent, the WFTC allows businesses to expense qualified equipment and property in the first year, significantly improving return on investment for capital-intensive semiconductor projects.Importantly, the American semiconductor supply chain includes not only large manufacturers but also droves of small and medium-sized businesses. President Trump’s WFTC permanently extends the Section 199A deduction, leveling the playing field for these businesses that would otherwise face higher hurdles to growth. That long-term tax certainty allows for businesses to confidently invest in and expand their facilities, hire new employees, and grow production—directly supporting American families. Together these pro-growth tax cuts help drive American semiconductor innovation, growth, and competitiveness. SEMI applauds the Administration’s competitive WFTC policies that support the full semiconductor supply chain. The WFTC allow companies to commit the capital necessary for multi-year semiconductor manufacturing investments with confidence and drive continued U.S. semiconductor and technological leadership. SEMI supports the Administration’s efforts to make the United States the premier destination to do business and looks forward to continued collaboration on U.S. economic and national security policy priorities. Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Royal Kastens is Vice President, Global Public Policy Advocacy at SEMI.

The global semiconductor industry is entering a new phase of growth to keep pace with the increasing demand for artificial intelligence (AI), high-performance computing (HPC), and system-level integration. At the same time, rapid technological advancement is intensifying the need for highly skilled talent. Industry projections indicate that by 2030, the global semiconductor sector will face a shortage of more than one million professionals, making talent a critical variable shaping competitiveness and supply chain resilience.In this context, governments and industry organizations worldwide are accelerating efforts to develop talent pipelines and strengthen cross-border collaboration. For a highly globalized industry like semiconductors, the movement of talent and exchange of knowledge are no longer confined to individual markets, but are essential to the development of a resilient and interconnected global ecosystem. Increasingly, competition is extending beyond technological breakthroughs to the ability to build and sustain a global talent pipeline.Supported by a cross-border collaboration framework, SEMI and the UK Electronics Skills Foundation (UKESF) have jointly organized a program to cultivate the next generation of semiconductor talent. Through structured exchange mechanisms and close collaboration with industry, academia and public sector partners, the program connects global talent with real-world industry environments and contributes to building a more sustainable foundation for long-term workforce development.From Lab to Fab: Understanding the Path from Research to ManufacturingA core objective of the project is to bridge the gap between academic research and industrial application. Through a 14-day immersive experience combining industry engagement and hybrid learning formats, participants engage directly with experts and gain a system-level understanding of how the semiconductor industry operates—from research and development to high-volume manufacturing.The program covers key segments of the semiconductor value chain, including advanced research, wafer fabrication, IC design, packaging and testing, and system applications. This integrated learning experience enables participants to move beyond isolated technical knowledge and develop a broader understanding of how innovation is translated into scalable industrial capabilities.As one participant shared: “Experiencing the award-winning R D solutions at ITRI and the massive scale of wafer manufacturing at UMC firsthand was unforgettable. It was incredibly inspiring to see how advanced research is translated into global manufacturing capabilities—from lab to fab.”Participant feedback highlights a clear shift in understanding. Through hands-on learning and industry engagement, participants moved beyond isolated technical knowledge to develop a more comprehensive, system-level perspective of the semiconductor industry—supporting more effective collaboration across the global ecosystem.A Practice-Oriented Approach: Redefining Semiconductor Talent DevelopmentAs technology evolves and industry demands shift, traditional discipline-based education models are no longer sufficient to fully meet the needs of semiconductor manufacturing and R D environments. Increasingly, the industry is seeking talent with cross-disciplinary capabilities and hands-on experience.The project adopts a “learning by doing” approach, combining laboratory sessions, expert-led workshops, and company visits to provide participants with practical exposure to semiconductor devices, materials, process technologies, and system design. Participants also gain exposure to real-world applications such as chip security, design verification, and advanced process technologies.From an industry perspective, this approach aligns more closely with evolving workforce needs. Compared with conventional academic training, individuals with cross-disciplinary experience and international exposure are better equipped to understand the interplay between R D and manufacturing, and to integrate more effectively into real-world operational environments.UK participants, dressed in cleanroom suits, gained firsthand exposure to Taiwan’s semiconductor manufacturing environment—observing wafer fabrication equipment up close and engaging in hands-on learning to experience the journey from lab to fab.From Talent Development to Ecosystem ConnectivityAt a time when the semiconductor industry is entering its next phase of growth, talent plays a central role not only in driving innovation, but also in enabling global collaboration. As supply chains become increasingly interconnected, building mechanisms for cross-border talent mobility and cooperation is critical to strengthening both resilience and innovation capacity.At the program’s closing event, “UK–Taiwan Semiconductor Industry and Talent Exchange,” Terry Tsao, Global Chief Marketing Officer and President of Taiwan, SEMI, noted:“By 2030, the semiconductor industry is expected to require more than one million additional skilled professionals. Through international collaboration and industry–academia engagement, SEMI aims to enable more global talent to engage with Taiwan, gain a deeper understanding of its semiconductor ecosystem, and build long-term connections with the industry.”The project reflects a broader objective: not only to develop talent, but to build a sustainable, globally connected workforce network. By fostering a shared understanding and collaboration across borders, such initiatives help align capabilities and drive innovation across the global semiconductor ecosystem.Terry Tsao, Global Chief Marketing Officer and President of Taiwan, SEMI, emphasized the importance of nurturing globally connected semiconductor talent to help drive the industry’s future growth.Advancing Global Collaboration to Meet Long-Term Industry NeedsAs the industry continues to evolve, no single organization or region can address workforce challenges alone. Cross-border collaboration and structured talent development frameworks will be essential infrastructure for the future of the semiconductor industry.Looking ahead, SEMI will continue to expand international partnerships, connecting global industry, academia, and government stakeholders to deepen and scale talent development efforts—supporting the next generation of semiconductor professionals with both global perspective and practical expertise.For more information or partnership opportunities, please contact:Ily TsaiTel: +886-3-560-1777 [email protected] Ily Tsai is Project Manager, Workforce Development at SEMI Taiwan.

Lu Dai, Vice President of Technical Standards at Qualcomm, presented “Converging Chip Design and Manufacturing in the Era of High Integration” at SEMICON West in October 2025, offering an insightful look at how design and manufacturing are collaborating effectively.I had an opportunity to talk at length with Dai and asked him to define collaboration. His thoughtful answers, perspective on industry trends and what it will take for a seamless automated flow between design and manufacturing made for a great discussion.In addition to his role at Qualcomm, Dai, who lives in San Diego, is Chairman of Accellera Systems Initiative, Chairman of RISC-V International and Director of Silicon Integration Initiative (Si2).Smith: Qualcomm is a fabless company. How do you define what collaboration is between design and manufacturing? Dai: When we talk about design and manufacturing collaboration, we need to consider how a design is optimized for a certain manufacturing process. For example, will an advanced manufacturing capability help designers simplify designs or allow them to bypass traditional actions?I compare it to the way software was optimized to hardware because of hardware limitations. We had to make sure the C code was compact and that the variable types we specified wouldn’t waste memory. We also had to write the code in a certain sequence to speed up the execution of the code. As hardware capability grows, we can write dirty code and it isn’t as critical. We understand the manufacturing process capability. That allows us to be more flexible about where to focus the chip design effort based on needs for power, performance, area, and schedule. We want to make sure we know the chip size and how big the silicon space is for certain features. For example, low power is often a key feature of today's designs. As manufacturing process nodes improve, power goes down and area shrinks. We can therefore focus more on optimizing performance.This is the kind of collaboration we use with foundries. Libraries need to be optimized for the design and tweaked for yield. This collaboration is critical for foundries pushing leading-edge nodes in the design house—they have to work closely with the design team.Smith: And how about collaboration with packaging suppliers? Dai: I'm not a packaging expert. Traditionally, packaging is one of the important steps and even more so because of the push toward the use of chiplets. Packaging becomes really important when dealing with multi-chiplet types of design. Traditionally, IP vendors sell a license to use the register transfer level (RTL) code, which is subject to IP theft. With a chiplet approach, they sell a netlist, which often becomes a hard coded chip as a bundled service instead of a single IP. The subsystem sales approach makes more money, creating another opportunity or a new landscape. SoC companies may get into the IP business and conversely, IP companies are getting into the SoC business by selling the bundled subsystem. Smith: The margins are getting blurred. It sounds like there is collaboration and it’s between designers, but also the foundries, process and the packaging.Dai: And partially between EDA tools because both the design side and the manufacturing side are speaking two different languages. EDA is somewhere in between, helping the translation.Smith: What are the trends and challenges that make it hard or even prevent a fully integrated flow?Dai: The extremely high costs of doing the implementation for an advanced node, especially for the first tape out. If we are the first to use the newest node, we know there is a tremendous benefit in the long run. But we are also the pioneers that have to work out the tough challenges. Few companies have the technical capability and deep financial resources to be the pioneers for a new process node. We’re starting to see high-flying semiconductor companies use leading-edge nodes. On the design side, they are challenged and trying to run faster by adopting a newer node. Cost is probably the biggest challenge for this collaboration. If their margins get challenged or they need to be a little bit more careful, they adapt by becoming fast followers.Another challenge comes from more specialized designs. There has been a long period where general-purpose chips are used for many different applications. But, we are now seeing designers increasingly focus on more specialized chips with custom designs.Custom IP and ASICs are becoming trendy. Designers are trying to figure out how to make a general baseline and then differentiate on certain IP and the best possible manufacturing process for the application. Doing a custom chip on an advanced node is quite expensive. We may be challenged if we don’t have sufficient data to clean up a process because every chip and process combination is unique. Lessons learned from this chip may or may not apply to everyone, while a general-purpose design tends to be a good baseline for lessons learned.Smith: How do you envision an integrated automated flow between design and manufacturing? Dai: In today's environment, we would like an RTL design to be fully portable to any kind of manufacturing process or foundry. Based on our architectural and business, we could then pick and choose the fab and the process. How do we port a design into a new process? That's difficult because we need to consider special constraints required by the new process that didn’t apply to the previous process. There's also the reverse case for porting a new design into an old process.Let’s say we have a chip designed for a 3-nanometer process and we want to port it back to a 28-nanometer process. Why would we want to do this? Imagine a COVID type of situation—a supply chain constraint and/or a geopolitical flare up with no access to the advanced fab, but an older local fab is still available. In this case, we need the chip for the feature it provides. Perhaps a car needs that chip and it was designed to be produced in a three-nanometer process but is suddenly unavailable. A 28-nanometer chip that runs at half of the speed might do the job for a few years. Unfortunately, this is somewhat wishful thinking because of the challenge of the flow. We didn’t think about it but we have to do it now and need to consider whether we have sufficient time to work out the challenges.Smith: How do you make that decision for making chiplets? Dai: Porting to another process is not a small job. It's labor intensive going from a same design in one process to another process.The project lead presents a process porting non-recurring engineering (NRE) cost budget to management. The questions span resources and time needed that boil down to how much money will need to be invested to achieve the porting. It should be simple. It’s not. It’s a lot of work.For many companies, the strategy is to offload the porting to a low-cost geographical team with a cheaper NRE that matches management expectations for the costs of process porting. History often shows that the company is not reducing that much time and manpower by offloading the porting. Smith: What about the EDA tool side? Is there typically a team from the EDA vendor? Dai: For advanced nodes, we involve the EDA and in-house EDA experts when certain parts of our design don't work out as expected.Back-end tools need experts involved in the debugging. And if we don't have an in-house expert, we need our EDA vendors to send engineers to work on the project.Smith: I have a generic question about AI. We talked about reporting. Where would it fit in collaboration?Dai: Sooner or later, we're going to be asked for a proper supply chain tracking or hardware bill of materials (BOM). Conceptually easy, but difficult in practice because it goes from logic design to physical design all the way to manufacturing. How do we carry that type of information through each step with EDA tool providers and manufacturing equipment providers? Their credentials need to be registered and they can’t alter any of the existing flow credentials.Supply chain tracking can ensure that if there's any kind of natural disaster or geopolitical issues, the hardware BOM is properly categorized, and the chip can be made. Security is another reason for supply chain tracking. Collaboration between design and manufacturing is important because once a netlist is sent to the foundry, our job is to make sure it is done correctly. We wait for our silicon to come back. Then we do testing. But during manufacturing, the chip comes back and it doesn't work. How do we know if somebody tampered with it? Supply chain tracking could help.Smith: How can you know that someone didn’t tamper with a chip design after it was handed off to manufacturing? This could cause big issues for end markets such as medical, automotive, defense and aerospace applications.Dai: The solution is EDA heavy because EDA tooling can help on the traceability at every step. It’s all automated through some kind of tool. If we need to have a proper format, we need to have proper encryption. And we know when we use this tool to run it, we check to show we are using the real tool not a hacked version that doesn't have the security credentials.Smith: Will this drive supply chain tracking or drive new standards?Dai: I hope so. Once upon a time, there was an initiative by the Department of Defense to track the supply chain. It was a mandate and no one liked it. It’s much better for the industry to proactively come up with a standard for a global economy.A mandate tends to come from one government. It may be a good mandate if we do business only within one country or within a small region. What if we have to do business with another government that may not like our mandate? Say a certain part of our design stage is done in a different country and we need this level of detail. Who's doing the work and what's the tool version? Per local government rule they may not be willing to give the information to us. This might be sufficient. We don't know the details of the risk, but we know there is a risk. We could simply add to our tracking that a portion of design is done in a foreign country with foreign EDA. It's important to have an industry standard and an international standard so that we can procure our tools and the services around the world instead of being limited.Smith: How can we encourage companies and people to want to cooperate and sign on to a project like this?Dai: With lessons learned, we can go deeper. Maybe the first level is a meeting in the U.S. About Lu DaiLu Dai is Vice President of Technical Standards at Qualcomm Technologies, Inc., spearheading semiconductor standards efforts and relationships with industry organizations. Lu was previously Senior Director of Engineering and led Qualcomm’s SoC design verification team and front-end methodologies and initiatives. He was also the Design Verification Lead responsible for multiple generations of premium tier platforms at Qualcomm, including the Snapdragon 8 series and products that power the Mars Perseverance rover and Ingenuity helicopter. Prior to Qualcomm, Lu was the Design Verification Lead for Cisco’s Gigabit Switching Business Unit where he worked on multiple generations of Cat4k ASICs. Lu is the current Chair of Accellera, Chairman of the RISC-V International Board of Directors and serves on the Board of Directors at Si2. Lu holds a Master of Science degree in Electrical Engineering from Cornell, and a Bachelor of Science in Electrical Engineering and Computer Science from UC Berkeley.Robert (Bob) Smith is an independent consultant who has been involved directly in multiple roles in the EDA industry over the past 38 years. His career experience spans analog engineering, marketing, sales, business and strategy development and others including numerous c-suite roles. He holds a Master of Science degree in Electrical Engineering from Stanford University.

The artificial intelligence revolution has a dirty little secret: for all its "brain" power, AI and autonomy are hopeless without the hardware that connects them to the physical world. Today’s semiconductor-related blockbuster tech topics like autonomous humanoid robots, Edge AI, self-driving cars, and lights-out fabs all depend on a variety of sensing modalities and enabling technologies (from MEMS to photonic and others). The 2026 MEMS Sensors Executive Congress (MSEC) gathered industry leaders to discuss how sensors continue to evolve from simple sensing components to the essential “eyes and ears” of a global, AI-driven transformation.The Sensor Industry is ShiftingMarcellino Gemelli of Bosch Sensortec took a retrospective approach during the Leadership Roundtable starting with the statement “to understand where we are going, we have to look at where we’ve been.” While logic and memory chips scaled rapidly, sensors faced a different reality:Commoditization: Rapid price erosion in high-volume markets like mobile.The "One Process, One Product" Curse: Unlike standard CMOS, every new MEMS device historically required a unique manufacturing flow which results in high development costs.Hard to fill MEMS Fabs: Geometries are shrinking resulting in more devices per waferPackaging: A challenge because it directly impacts device performanceSensor Fusion: Integrating sensor components with ASICs and MCUs to create smart sensorsAccording to Maximize Market Research, the global sensor market is predicted to have an 8.7% CAGR from 2024 through 2030. There is a fundamental realization about sensors: the next stage of autonomous manufacturing and intelligent systems cannot exist without high-fidelity, real-time sensor data from the edge. This was a common theme throughout MSEC. Data presented at MSEC by Pierre-Marie Visse of Yole Group shows the global MEMS market is projected to grow more slowly with a 3.7% CAGR over the same time frame, with higher growth predicted for automotive, industrial, and medical applications.The Leadership Roundtable, featuring executives from Bosch, Infineon, STMicroelectronics, and Rogue Valley Microdevices, highlighted the strategic roadmaps that will define the next decade, echoed by others during other technical presentations:The Edge of Perception: AI is pushing sensing technologies to process data within the sensor itself and not in the cloud, reducing latency and power consumption while improving privacy.Autonomous Manufacturing: Leaders like John Behnke (INFICON) and Edvard Kälvesten (Silex) mapped out the path toward “Autonomous Fabs,” where sensors allow tools to communicate and self-optimize with minimal human intervention.Emerging Modalities: Beyond traditional motion and pressure sensing, MSEC spotlighted the rise of Quantum sensors for resilient navigation and Photonics combined with MEMS for ultra-precise inertial sensing.From “Parts” to “Interfaces”A recurring theme throughout the congress was the death of the "sensor as a part" mentality. In his keynote, Kurt Busch (Syntiant) argued that sensors plus AI models are becoming the default interface layer for products.“The next-generation interface is not a screen. It is the physical world, captured by sensors, interpreted by models, and delivered through natural interactions,” said Busch.This shift is visible in the rapid adoption of Edge AI integration, the development of humanoid robots, autonomous drones and vehicles, and AI enabled smart glasses—rewriting what the human machine interface looks like.Conclusion: Sensorizing the FutureWe are no longer just building devices; we are building an “industrial AI operating system” that connects the digital and physical world. This all starts with sensors. By 2030, the most valuable AI won't just be the one with the biggest brain, it will be the one with the best senses.If you are a leader in the field of MEMS Sensors, let your voice move the industry needle by becoming a SEMI and MEMS Sensors Industry Group (MSIG) member company and getting involved with MSIG. MSIG will be hosting the MEMS Sensors Technical Congress (MSTC) on September 16-17 at SEMI HQ in Milpitas, CA. Engineers and technical executives will dive deep into new technology and processes that advance the sensor industry. To learn more or to be a part of the fascinating world of MEMS Sensors visit the SEMI MSIG website.Paul Carey is Director, MSIG at SEMI. Rafael Tudela is Senior Technical Marketing Manager at SEMI.

The number of regulatory proposals, including restrictions on substances such as per- and polyfluoroalkyl substances (PFAS), that could hinder the semiconductor industry’s ability to continue manufacturing is increasing. The SEMI Environmental, Health Safety (EHS) Working Groups, composed of industry technologists from across the global supply chain, meet on a regular basis to share intelligence and develop strategies to earn exemptions and/or extensions from regulators to enable the industry to continue manufacturing the chips critical to our modern way of life.In addition to an EHS session each year at SEMICON West, SEMI also hosts a full-day EHS Summit annually. This year’s event will be held on Thursday, May 26 at SEMI Headquarters in Silicon Valley. Experts from AGC, Beveridge Diamond, Intel, Tokyo Electron, SEMI Public Policy Advocacy staff from Brussels and Washington DC, as well as other key industry leaders will address the EHS regulatory challenges facing semiconductor manufacturing in 2026 and beyond. Presentations will allow for questions, discussions, and planning for taking collective action to strengthen semiconductor manufacturing.  Tentative topics include:US regulatory landscape under second Trump Administration and global impactUS State-level legislationEurope: PFAS restriction, REACH restriction, packaging and packaging waste regulation, GENESIS Consortium, and more.PFAS recyclingStockholm ConventionEmerging regulations in AsiaSupply chain transparencyUS EPA Technology Transition Rule (HFC Phasedown)US EPA TSCA New Substances Risk EvaluationPlasticizers and flame retardantsMark your calendar to attend, network, and strategically prepare your company. Register today. EHS Summit LocationSEMI 673 South Milpitas Ave. Milpitas, CA 95035James Amano is Senior Director, EHS at SEMI

Ever wondered if the industry could reduce the environmental impact of its manufacturing? And maybe even provide a positive return-on-investment (ROI) without modifications to environmental permits? Or realize the alchemist’s dream of turning waste into revenue in the semiconductor supply chain?SEMI has launched a new report “The Evolving Paths for Waste in Semiconductor Manufacturing” focused on the concept of re-use and resale versus onsite treatment or offsite disposal of manufacturing wastes within the semiconductor manufacturing value chain. This compendium of best-known methods (BKMs) should be used as a roadmap for companies to reduce costs and make a positive impact on global sustainability efforts.Historically, semiconductor manufacturing has followed a linear “take–make–dispose” model. More recently, semiconductor manufacturing and advanced packaging facilities (fabs) are trying harder to improve their waste management strategies to minimize costly (and undesirable) waste treatment services such as landfill or hazardous waste incinerators. Many barriers prevent fabs from further transitioning from a linear to a circular mindset.The semiconductor industry generates on average ~1.88 tons of waste per million dollars of revenue or 6.8 million metric tons of total waste per year, based on data gathered from over 140 companies in the semiconductor value chain and aggregated in the SEMI Dashboard. Identifying Addressing the BarriersTo identify and address the barriers, SEMI has developed the first of its kind guide to support the adoption of circular design principles and resource recovery practices across the semiconductor manufacturing value chain. The primary recommendation is to accelerate adoption of proven circular solutions by improving visibility of peer practices, aligning regulatory strategies, and strengthening ROI assessments to support informed decision-making.The report consolidates publicly available BKMs for recovering and recycling spent chemicals, wastewater treatment by-products, tool packaging, and other manufacturing wastes generated by integrated device manufacturers (IDMs), foundries, outsourced semiconductor assembly and test (OSAT) facilities, equipment manufacturers, and material suppliers. The report’s recommendations are completely accessible with advice on how to respond when management raises objections on common topics – helping to change the mindset from ‘waste’ and seeing it as a product.ConcernsResponsesThere are regulatory barriers.There are options to addressing those barriers.No one else is doing it.There are companies taking action and making a difference.It is a waste of time and money.There is an opportunity to turn the funds spent on disposal into revenue sources.There is no room in the facilities areas for a new tank.Switching from tanks to totes is a viable strategy. The review draws on corporate sustainability reports, waste treatment technology publications, and industry data compiled by SEMI, complemented by professional experience in chemical waste management in the EU and USA. The report identifies existing technological, regulatory, and economic enablers for material recovery, as well as barriers in legacy facility design. The report provides circular design and resource recovery practices across the semiconductor value chain. It is a single, accessible information source on current best-known recovery and recycling practices. This report enables you to become the alchemist, streamline discovery, accelerate adoption, and turn waste into revenue streams. How to PurchaseThe report is an ‘alchemists dream’ and provides guidance on turning waste into revenue in the semiconductor supply chain.Get your copy today! Purchase “Evolving Paths for Waste in Semiconductor Manufacturing: A Guide to Turning Waste into Revenue” at the SEMI Store.Taimur Burki is Sustainability Consultant at SEMI.

The rapid growth of AI has created a surge in the global energy consumption at a rate never seen before. Today, data centers account for approximately 415 terawatt-hours (TWh) of electricity globally. To put this into perspective, the annual energy consumption of the United Kingdom in 2023 measured at 309 TWh. The International Energy Agency (IEA) projects data centers’ energy consumption will more than double to nearly 945 TWh by 2030 [1]. A single generative AI query can consume up to ten times the power of a traditional search [1]. Meanwhile, data center energy usage in the U.S. is projected to leap from 4.4% to as much as 12% of the national grid by 2028 [2]. This creates a stark reality for the semiconductor industry. Traditional monolithic scaling has hit its physical and economic limits, leaving advanced packaging and heterogeneous integration to define the industry’s trajectory [3].To meet these escalating compute demands, the industry is rapidly shifting toward multi-die architectures, chiplets, and 3D stacking to decrease the amount of energy needed for advanced computing. This transition is fueling explosive growth in the advanced packaging market, which the Yole Group projects will reach $79.4 billion by 2030 [4]. However, stacking chiplets to bypass Moore’s Law exposes massive systemic bottlenecks. Engineers are now fighting interconnect parasitics, navigating complex power delivery architectures, and battling extreme thermal density.In a 3D-stacked architecture, pulling heat away from vertically integrated dies is one of the most pressing engineering challenges of our time. As compute density rises, issues like die warpage and localized thermal hotspots threaten both reliability and yield. The shift toward sustainable AI systems for energy-efficient computing requires breakthroughs in everything from hybrid bonding process flows to advanced thermal interface material (TIM) strategies and liquid cooling integration [6].These are not challenges that any single company can solve in isolation. Whether you are a foundry, OSAT, material supplier, or equipment provider, overcoming these bottlenecks requires pre-competitive, industry-wide collaboration. Foundational capabilities must be built collectively before competitive differentiation occurs.This is the core mission of the SEMI Advanced Packaging and Heterogeneous Integration (APHI) Technology Coalition. By collaborating on common standards, shared research frameworks, cross-vendor interoperability models, and collective technology roadmap congruency, APHI is actively dismantling the barriers to next-generation computing.The APHI community is already tackling these issues head-on. Monthly chapter meetings identify and address these and other issues facing heterogeneous integration. The most recent chapter meetings showcased in depth review of these challenges. Jonathan Abdilla from BESI detailed the technical challenges and collaborative research required for global hybrid bonding process flows. Similarly, Dr. Jie Geng from Indium Corporation led a deep dive into crucial TIM strategies for AI and HPC, exploring hybrid stacking evaluation methods and liquid cooling options to combat GPU die warpage.The future of advanced manufacturing will be defined by how effectively we manage power and heat in heterogeneous systems. We invite you to join this critical conversation at the upcoming SEMIEXPO Heartland (April 29-30 in Detroit, MI) Day 2 will feature dedicated sessions on Thermal Management Power Delivery in Advanced Packaging: From TIMs to Warpage Control, as well as strategies for securing the advanced packaging supply chain.To help shape the standards and shared roadmaps that will power the AI revolution, explore our initiatives and get involved with SEMI Advanced Packaging and Heterogeneous Integration (APHI) Technology Coalition.Rafael Tudela is Senior Technical Marketing Manager at SEMI References[1] International Energy Agency (IEA). (2024). Energy and AI Report. [2] U.S. Department of Energy (DOE) Lawrence Berkeley National Laboratory (LBNL). (2024). Report on U.S. Data Center Electricity Demand and Grid Impact.[3] Semiconductor Packaging News. Advanced Packaging and Heterogeneous Integration. Retrieved from: https://www.semiconductorpackagingnews.com/articles/92402.html [4] Yole Group. (2025). Status of the Advanced Packaging Industry 2025.

The House Semiconductor Caucus event held on March 17, 2026 at the Rayburn House Office Building in Washington, D.C. brought together industry leaders for an in-depth panel discussion around the upstream vulnerabilities in the U.S. semiconductor supply chain and policy actions Congress should consider. If policymakers do not hear from all segments of the supply chain, critical issues go unaddressed and the policies that result are less effective than they could be. Events like this reflect SEMI’s mission to bring the full breadth of the supply chain into policy conversations. Key topics addressed during this panel were supply chain and critical material challenges, tax and domestic incentives, and export controls and trade policy. The briefing featured executives from leading materials companies—Entegris, Materion, Avient, and CoorsTek—and was moderated by SEMI. They shared firsthand insights into bottlenecks and risks within the global supply chain, emphasizing how disruptions in sourcing and processing critical materials can threaten the entire semiconductor manufacturing process. The event also addressed the need for targeted policy actions to strengthen U.S. competitiveness, such as extending and expanding the Sec. 48D tax credit, targeting R D in specific areas, and workforce development. The event underscored the strategic significance of a robust and resilient semiconductor supply chain as a cornerstone of national and economic security, particularly in light of ongoing global supply chain uncertainties. The panel encouraged policymakers to increase consultation with industry stakeholders and consider specific, actionable steps to close existing gaps and support the entire ecosystem. The Q A session allowed congressional staff to engage directly with experts, further deepening their understanding of the complex challenges facing the semiconductor industry today. SEMI is the preferred trusted partner to the government and the event concluded with a networking lunch to reinforce the collaborative spirit between industry and government that is necessary to build a stronger, more secure future.Thank you to Representative Zoe Lofgren for providing a keynote address, Representative Michael McCaul for collaborating with SEMI to host this panel event, and to our speakers for raising these important issues and sharing timely insights. Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Scarlett Bickerton, Manager, Federal State Affairs at SEMI.

The semiconductor industry continues to grow at an unprecedented pace and so does the demand for highly skilled employees at all levels in the industry. With the focus on reshoring manufacturing in the United States, we are increasingly faced with two questions: 1) how to identify talent that is ready to work today with the skills and experience that they already have and 2) how to best prepare a workforce for tomorrow, to meet the estimated shortage of 59,000-146,000 technicians and engineers by 2029. The SEMI Foundation – the workforce development arm of SEMI – provides solutions to address the talent gap and more through programs such as SEMI Credentialing. This innovative effort that helps employers identify talent, jobseekers communicate their work readiness, and training and education providers align their programs to industry needs.SEMI Equipment Maintenance Technician CertificationIndustry subject matter experts who provided initial inputs for the Knowledge, Skills, and Abilities (KSA) of an Equipment Maintenance Technician.The SEMI Foundation is building out the first nationally accredited, industry-recognized Equipment Maintenance Technician Certification. In collaboration with industry leaders like Micron, GlobalFoundries, Intel, Western Digital, TEL, Onto Innovation, and others, we have identified the key competencies for equipment maintenance technicians. Individuals from 45 companies across 16 states have provided technical subject matter expertise, resulting in one of the most regionally diverse and comprehensive certification offerings to date. Our partner, NOCTI, an ISO-certified credentialing provider, is in the final stages of developing the certification exam. Our two-part certification exam includes 100 multiple choice questions that assess a candidate’s knowledge of safety, quality, electrical and mechanical principles, maintenance principles, and semiconductor industry awareness, as well as a hands-on electrical and pneumatic skills-based performance task. Educators from 12 community colleges and universities across the United States developed the questions, ensuring the highest academic standards and rigor. This certification will allow job seekers to demonstrate their readiness and create clear pathways into technician roles for qualified individuals regardless of their previous training. Furthermore, the Equipment Maintenance Technician certification will establish a national source of truth for curriculum alignment made available to training providers and educators and ensure relevance and continuity through routine industry review. The SEMI Equipment Maintenance Technician Certification will launch regionally in Spring 2026. National roll-out is scheduled for Fall 2026, and we encourage training and industry partners to connect with us directly to ensure early access to the certification.SEMI Endorsement of Programs and CoursesPartners from 12 community colleges and universities provided their expertise in developing test questions for the SEMI Certification.The SEMI Foundation is endorsing programs that prepare entry-level workers for success in the semiconductor industry. Since 2024, we have endorsed programs at Austin Community College, Foothill College, NY Creates, and WGNStar. These programs, and others like it, are emblematic of what strong partnerships between academia and industry can look like. Learners seeking programs can look to these as options for their education. Receiving SEMI Endorsement for Programs and Courses conveys that: Learners who are new to the semiconductor industry and successfully complete the program will be well-prepared for entry-level roles; Program completers have had exposure to fundamental semiconductor industry information and context, as well as introductory hands-on experience; Completers of these programs have the specific knowledge and skills required for entry level positions; andProgrammatic design and content have been informed through input and feedback from local industry partners.As we continue to expand the portfolio of programs and courses that the SEMI Foundation endorses, we are looking increasingly at programs with strong industry alignment and clear pathways for learners once they complete their training, be that apprenticeships, additional training, or direct access into the workforce.Microcredentials and MoreThe SEMI Foundation is a leader in convening stakeholders across academia and industry in support of workforce development initiatives. This unique ability to bring together diverse perspectives positions us to play a central role in shaping the future of skill validation. Microcredentials address several key changes and trends in training, including the rising costs of education coupled with an increased appetite for hands-on learning opportunities. Microcredentials are stackable, adaptable, and aligned directly with workforce demands. Learners can build competencies step-by-step. Employers can identify specific skill sets with greater precision. Education providers can modernize programs to reflect emerging technologies and evolving roles. We are forming panels and committees to explore the idea of microcredentials, as our partners are looking to us for innovative ways to recognize short-form training programs, amplify opportunities for individuals in up-and-coming regions, and continue to connect our partners in service of workforce solutions. In addition, the SEMI Foundation is exploring the provision of badges to teachers, career counselors, and other educators to demonstrate their knowledge and awareness of semiconductor careers.As we continue to drive solutions and add value to the world of credentials, we look forward to ongoing conversation and collaboration with partners. Every conversation we engage in about credentialing strengthens our offering and ability to provide solutions to the semiconductor industry’s growing workforce demands. Anissa Hamdon-Morison is Manager, Curriculum Developer Training at the SEMI Foundation

As the semiconductor industry continues to advance, effective quality management is increasingly essential. The SEMI Quality Benchmarking Consortium (QBC) brings together leading companies to exchange best practices, benchmark performance, and promote collective improvement across the global semiconductor landscape. The last QBC meeting was hosted by Bill Lechten of Micron at their headquarters in Boise, Idaho. Representatives from GlobalFoundries, Infineon Technologies, STMicroelectronics, NXP Semiconductors, and Texas Instruments came together for two days of in-depth discussions and knowledge sharing.The session began with an overview of Micron’s global business and manufacturing footprint. The company reported record revenue of $37 billion in 2025 and currently hold more than 60,000 patents. Micron is investing approximately $150 billion in U.S.-based DRAM manufacturing, which is expected to generate around 90,000 direct and indirect jobs. The QBC operates on a “give-to-get” philosophy where members must actively contribute survey responses and participate in open discussions to access shared benchmarking data. This meeting focused on three topics: risk management, customer return, and product change notification. Participants presented their approaches, shared lessons learned, and engaged in roundtable discussions to identify best-known methods and address common challenges. Customer Returns and Failure AnalysisThe group reviewed processes for handling customer returns and failure analysis. Discussions covered escalation protocols, data-driven versus physical failure analysis, sampling strategies, and customer acceptance challenges. Members shared approaches to closure criteria, complaint prioritization, and using FA and complaint data for trend analysis and continuous improvement. Local support models and the balance between cost, proximity, and specialized lab capabilities were also key topics.Product Change Notifications The consortium explored industry-wide PCN practices, focusing on notification volume, approval processes, and customer expectations. Companies highlighted distinctions between PCN (requiring approval) and CIN (informational) and the challenges of handling multiple changes per notification. Participants shared strategies for managing customer approvals, sample delivery, and internal tracking, including phased notifications and customized communication. Standardization efforts were discussed, such as adopting the JDEC XML schema, while balancing operational efficiency with contractual obligations and customer requirements.Risk ManagementMembers discussed structured approaches to quality and qualification risk, including product grade classification and risk assessment methodologies like FMEA and QRA. Emphasis was placed on assessing end-user system complexity, mission profiles, and application-specific requirements, especially for automotive and AI workloads. Organizations shared practices for transparent customer communication, balancing speed and risk, managing residual risk, and integrating qualification with change management. AI and data analytics were highlighted as emerging tools to support predictive risk assessment and continuous improvement.AI and Digitalization in Quality ManagementArtificial intelligence is becoming a growing focus for semiconductor quality teams. Companies shared early-stage AI initiatives. Based on survey results and discussion, consortium members agreed to establish a working group to explore AI uses cases in risk assessment for change management and new product introduction. Looking AheadWith growing complexity in semiconductor technologies, industry collaboration is vital. Through open discussions and benchmarking, the SEMI Quality Benchmark Consortium enables companies to share knowledge, identify best practices, and address common challenges. The consortium will continue its work at the upcoming meeting to be hosted by Texas Instruments in Dallas, Texas. (From Right to Left) – Karim Somani (SEMI), Sarah Shen (SEMI), Mark da Silva (SEMI), Ivo Clerici (GlobalFoundries), Wesley Hirsch (TI), Roberto Lissoni (STMicroelecetronics), Lou Cerra (NXP), Jens Luepke (Infineon), Bill Lechten (Micron), Fern Yoon (Texas Instruments)Sarah Shen is Senior Coordinator, MEMS Sensors Industry Group at SEMI.