Edge AI is a fundamental technology for applications that require real-time decision-making. Contrary to cloud-based AI solutions that specialize in large and complex tasks, edge AI is embedded directly into local devices, allowing for lower-latency decision-making for less bandwidth consumption. These properties are essential for advancing technologies like 6G, autonomous vehicles, industrial IoT solutions, and more. However, edge AI can’t be achieved with traditional silicon because it requires more efficient thermal management, higher performance, and lower power than silicon can deliver. To address these limitations, the Silicon-on-Insulator (SOI) technology platform offers a path forward. SOI is a layered silicon substrate technology with a silicon device layer on top, an insulating silicon dioxide layer in the middle, and a thick silicon base at the bottom. This structure disconnects devices from the bulk substrate, enabling major performance improvements for faster and more power-efficient ICs and photonics devices. In addition, FD, or fully depleted SOI (FD-SOI), is a subcategory of SOI that offers even higher performance and lower power usage.According to Michaël Tchagaspanian, Executive Vice President of Technology Strategic Partnerships at CEA-Leti, SOI is not just an alternative material. Instead, it’s a foundational technology that’s crucial for advancing the next wave of edge AI innovation. Therefore, to accelerate its advancement, CEA-Leti is combining its four decades of pioneering research with the cooperative efforts of the SEMI SOI Industry Consortium.CEA-Leti’s HistoryFor nearly 50 years, CEA-Leti has been at the forefront of SOI leadership. The company began in 1980 with its research into radiation-hardened electronics, which led to breakthroughs that enabled the Smart Cut™ process. Smart Cut ultimately served as the foundation for enabling SOI wafers to become a commercially viable global standard.This legacy also paved the way for much of the cutting-edge R D of today, including the FD-SOI Next Generation 10-7 nm program. This effort leverages flexible back-biasing to allow dynamic control over power consumption, leading to substantial efficiency gains.Tackling Tomorrow’s Challenges: A Sustainable FutureCEA-Leti’s deep SOI expertise allows it to address many of edge AI’s environmental challenges. To promote energy efficiency, CEA-Leti is working to advance silicon photonics while at the same time, incorporating the comprehensive PPAC-E framework across its new technology developments. The organization also works toward reducing energy through its fully integrated neural-network-on-chips technology that uses hybrid memory. This effort supports ultra-low-power, on-chip learning and inference for applications like autonomous vehicles, medical sensors, and others. Finally, CEA-Leti works to reduce greenhouse gases through its involvement in the GENESIS project, plus its ongoing efforts in eco-design and lifecycle analysis. The SOI Industry Consortium: Accelerating Industrial AdoptionAs part of its partnership, the SOI Industry Consortium works to ensure that CEA-Leti’s lab innovations can be seamlessly integrated into global production. This "lab-to-fab" model can be seen in the volume production of FD-SOI transistors from leading companies like STMicroelectronics and GlobalFoundries. The Consortium helps achieve volume production through its three-part approach: Secure the supply chain, reduce SOI adoption barriers, and close the specialized skills gap. To promote a healthy supply chain, the Consortium offers a platform that brings lab-to-fab solutions for SOI wafers. This is achieved through leading-edge development capabilities at CEA-LETI, Soitec and its Foundry manufacturing partners, with additional support from leading wafer suppliers like Shin-Etsu, GlobalWafers and Okmetic.It lowers SOI adoption barriers by collaborating with EDA leaders to standardize design tools and methodologies, ensuring robust proven design flows fully leveraging SOI technology.Finally, the Consortium supports training initiatives that address the SOI industry’s specialized skills gap. Partners like Synopsys also provide extensive training options, equipping engineers with the expertise to master SOI designs. SOI is helping the innovations of tomorrow become a practical reality. CEA-Leti’s leadership, combined with the global reach of the SOI Industry Consortium, allows the SOI ecosystem to optimize for low-power and sustainability while driving the next generation of high-performance systems. Gity Samadi is Senior Director of R D at SEMI.

Hosted by the SEMI North America Advisory Board (NAAB), executives from member companies across the semiconductor supply chain with operations in the U.S. recently convened in Washington, D.C. to advocate for the policies most critical to semiconductor competitiveness and national security. From March 3-5, 2026, SEMI executives and more than 80 representatives from member companies embarked on Capitol Hill, engaging directly with members of Congress and federal officials to advance the industry’s top policy priorities heading into 2026. These industry leaders from across the semiconductor ecosystem—from materials and equipment suppliers to chipmakers and end users—underscored the urgent need for industry-informed policymaking. Focus topics included:• Trade and Tariff Policy – Promote a balanced trade policy that preserves market access and avoids overlapping tariffs on the same product, as well as narrowly tailored, coordinated export controls to protect national security without harming U.S. competitiveness.• Tax Policy and Investment Incentives – Establish a competitive tax framework would reward innovation and lock the next generation of semiconductor production onto U.S. soil.• Research and Development (R D) Investment – Invest in long-term tax and R D incentives to sustain semiconductor investments.• CHIPS and Science Act Implementation and Beyond – Continued implementation of the CHIPS Act and related programs and develop a forward-looking initiative or roadmap to continue the industry’s momentum.• Workforce Development – Establish a national workforce pipeline aligned with federal, state, and industry programs to meet critical talent needs.• Environmental Regulations – Support pragmatic policies that balance environmental goals with innovation. The semiconductor industry is vital to every facet of our lives today from artificial intelligence and advanced manufacturing to healthcare. The U.S. leads in semiconductor design and advanced technologies that enable the AI era—and clear, predictable policy frameworks are critical to the Administration’s goals around maintaining U.S. technological leadership and advancing national and economic security.A highlight from the Fly-In was recognizing Indiana Senator Todd Young with the SEMI Americas Government Leadership Award on March 4. The NAAB selects Government Leadership Award honorees based on their impact on policies and incentives to bolster semiconductor design and manufacturing and advance the growth of the global industry. SEMI member companies are making record level investments in the U.S. semiconductor ecosystem, bringing high-paying, skilled jobs to communities across the country. This year’s Fly-In participants met with over 100 key congressional offices and committees and engaged directly with administration officials to discuss policies that support economic growth, innovation, and national security. Through collaboration, credibility, and consistent engagement, SEMI looks forward to continuing to work with Congress and the administration to ensure the next phase of U.S. semiconductor expansion delivers lasting benefits for the U.S. economy. Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Learn more about the SEMI Public Policy and Advocacy program and the 2026 policy strategy: https://www.semi.org/en/global-advocacy.Christina Banoub is Senior Manager, Federal Affairs at SEMI.

As the global semiconductor industry enters a decisive new phase shaped by artificial intelligence, SEMICON Korea 2026 convened the ecosystem from February 11–13 in Seoul, bringing together the companies, technologies, and talent required to sustain momentum on both sides of the AI equation: using AI to transform semiconductor operations, and advancing semiconductor innovation to enable the next generation of AI systems.At the SEMICON Korea press conference, Hyun Cha, President, SEMI Korea stated that with nearly 550 exhibiting companies and over 2,400 booths, the event underscored how progress now depends on a virtuous cycle of collaboration across the entire value chain—from materials and equipment to design, manufacturing, packaging, and systems integration.Opening Perspectives: Collaboration as the Catalyst In the opening ceremony, Ajit Manocha, President and CEO of SEMI, framed the opportunity and challenge ahead: AI is accelerating the industry’s trajectory toward a trillion-dollar market, but sustaining that growth will require deeper collaboration across an increasingly complex ecosystem.That message was reinforced by YH Lee, Chairman of Wonik, who emphasized the need for alignment across the value chain, “looking side to side, not only forward,” as scaling semiconductor technologies grows more difficult. From a policy perspective, Shinhak Moon, Vice Minister of Korea’s Ministry of Trade, Industry Resources (MOTIR), highlighted the importance of the full ecosystem, including parts, materials, and equipment, while cautioning that resilience will be critical amid economic cycles. Together, these perspectives set the stage for a keynote program focused on how AI and semiconductors are now co-evolving.Opening Keynote: Samsung Electronics on Architecting the Future of AI SystemsThe keynote program opened with Jaihyuk Song, Corporate President and CTO of Samsung Electronics, who examined what comes next for AI systems as compute and memory demands rise exponentially. He described a widening gap between compute performance and memory bandwidth, positioning advanced packaging and architectural innovation as central to closing that gap.Song outlined Samsung’s focus on next-generation memory technologies, including high-bandwidth memory and compute-in-memory approaches, as well as the transition beyond traditional Moore’s Law scaling toward planar, vertical, and stacked architectures. His message was clear: sustaining AI performance gains will depend on tight integration across design, process technology, packaging, and system architecture, reinforcing the need for ecosystem-wide coordination. ASE: From Chip Integration to System OptimizationTien Wu, CEO of ASE, expanded the discussion from devices to systems, arguing that advanced packaging has become a primary driver of system-level performance and efficiency. As AI workloads push power, thermal, and bandwidth limits, Wu described a shift from single-chip packages toward heterogeneous integration, 2.5D and 3D architectures, and co-packaged optics.Wu emphasized that productivity, yield, and throughput will increasingly determine competitiveness as packages grow larger and more complex. His perspective reinforced a central theme of SEMICON Korea 2026: AI-driven demand is forcing tighter coupling between design, manufacturing, and packaging, making collaboration not optional, but essential.Cadence: AI-Enabled Design Across the Value ChainBoyd Phelps, Senior Vice President and General Manager of Silicon Solutions at Cadence Design Systems, highlighted how AI is already reshaping semiconductor design and development. As process scaling slows and cost per transistor rises, Phelps described disaggregation and chiplets as a new abstraction layer that enables continued innovation through customization and configurability.He also pointed to the growing role of AI-driven design automation, noting that a significant portion of recent designs leveraged AI-enabled tools. Cadence’s end-to-end portfolio—from IP and tools to packaging and test—illustrated how AI is becoming both a design accelerant and a necessary response to rising system complexity, reinforcing the industry’s virtuous cycle.Lam Research: Velocity Through AI and AutomationThe theme of operational transformation took center stage with Tim Archer, President and CEO of Lam Research, who introduced “velocity” as the defining imperative of the AI era. As AI-driven demand accelerates product cycles and increases complexity, Archer argued that speed must be matched with direction—enabled by AI, automation, and digital twins.Archer detailed Lam’s progress toward autonomous fabs, equipment intelligence, and collaborative virtual development environments that reduce variability and accelerate process development. These capabilities, he explained, allow the industry to respond faster while preserving quality and resilience—another example of AI improving semiconductor operations even as semiconductor innovation enables AI growth.SK hynix: AI as a Tool for Memory InnovationLooking further into the future, Sunghoon Lee, Senior Vice President and Head of R D Process at SK hynix, addressed the mounting difficulty of sustaining memory technology cadence. As stacking, bonding, and material challenges intensify, Lee described a shift toward AI-based R D models that dramatically accelerate material discovery and optimization.By integrating AI into material exploration and process development, SK hynix is shortening development cycles and enabling new memory architectures. Lee emphasized that realizing the full potential of AI-driven R D will require greater data sharing and collaboration across partners—reinforcing the ecosystem-wide virtuous cycle.NVIDIA: From Chips to AI InfrastructureThe final keynote, delivered by Soyoung Jeong, Head of Korea Business at NVIDIA, framed the transformation of NVIDIA from a GPU company into an AI infrastructure provider. He described how accelerated computing and AI factories are reshaping chip design, manufacturing, packaging, and system integration.From AI-assisted design and simulation to system-level optimization and physical AI, NVIDIA’s approach illustrated how semiconductors and AI are now inseparable, each advancing through the other. Partnerships across memory, equipment, and software ecosystems were highlighted as critical to sustaining this momentum.A Program Aligned Around the Same ThemeBeyond the keynotes, SEMICON Korea 2026 reinforced these messages through technology symposia, AI and smart manufacturing forums, cybersecurity discussions, and workforce development initiatives—all focused on enabling AI-powered innovation across the semiconductor lifecycle.Additional Program Highlights: Extending the Virtuous Cycle Across the EcosystemBeyond the keynote stage, SEMICON Korea 2026 reinforced the same virtuous cycle of AI and semiconductor innovation through a wide range of technical, business, and workforce programs designed to engage every layer of the value chain.AI Summit: Translating Strategy into Industrial ImpactThe AI Summit, co‑hosted by SEMI and KAIST, served as a focal point for aligning academic research, device manufacturers, and equipment leaders around AI-powered industrial innovation. Featuring faculty from KAIST alongside representatives from Samsung Electronics, SK hynix, and global equipment companies, the summit explored technology strategies and future roadmaps aimed at accelerating AI adoption across semiconductor manufacturing and design.The discussions reinforced a central theme of SEMICON Korea 2026: AI is no longer an isolated software layer, but a system-level capability that must be embedded across processes, tools, and infrastructure to unlock its full value.Smart Manufacturing Forum: Advancing the Autonomous FabThe Smart Manufacturing Forum highlighted how AI, digital twins, and real-time data are transforming semiconductor fabs toward more autonomous, resilient operations. Speakers shared trends and success cases demonstrating how advanced analytics and AI-driven decision-making are improving yield, productivity, and operational agility.This forum echoed themes raised by equipment and manufacturing leaders in the keynote program, underscoring how AI-driven manufacturing excellence is becoming a prerequisite for meeting the speed, scale, and quality demands of next-generation AI chips.Startup Summit: Fueling Innovation from the Ground UpThe Startup Summit showcased emerging semiconductor and display startups focused on applying AI to improve chip performance, energy efficiency, and manufacturing processes. By connecting startups with industry leaders and venture capital firms—including Applied Ventures, Intel Capital, Samsung Ventures, and SK hynix—the summit emphasized the importance of nurturing innovation across the ecosystem.These early-stage technologies represent the next wave of ideas feeding into the virtuous cycle, where AI-enabled innovation at the startup level can scale rapidly through collaboration with established players.Cybersecurity Forum: Securing the AI-Driven Semiconductor FutureAs AI becomes deeply embedded in semiconductor operations and data flows, the Cybersecurity Forum addressed the growing need for digital trust across the ecosystem. Global experts examined cybersecurity challenges related to compliance, fab security, and AI data governance, highlighting the importance of collaboration to protect sensitive data and intellectual property.The forum reinforced that secure, trusted infrastructure is a foundational requirement for the AI-driven transformation discussed throughout SEMICON Korea 2026.Conclusion: Advancing TogetherSEMICON Korea 2026 made clear that the next phase of industry growth will not be driven by isolated breakthroughs, but by a virtuous cycle of alignment across the full semiconductor value chain. By integrating AI into design, manufacturing, and operations—and by advancing semiconductor technologies that power AI—the industry is building a foundation for sustained innovation. As the event demonstrated, progress will be fastest when the ecosystem moves forward together.Samer Bahou is Director, Corporate Communications at SEMI. Jaegwan Shim is Senior Specialist, Marketing at SEMI Korea.

In the summer of 2025, I had the privilege of leading more than a dozen SEMI Foundation STEM summer camps in schools across multiple communities.Each camp brought students face-to-face with hands-on engineering challenges, semiconductor learning modules, and conversations about the careers connected to what they were building.What stood out most wasn’t just the energy in the classrooms; it was the moment students began to see themselves in futures they hadn’t previously imagined. For many, it was their first exposure to the semiconductor industry. Their first time hearing about advanced manufacturing careers. Their first time understanding that a certificate, credential, or engineering degree could lead to a stable, high-quality job shaping the technologies that power modern life.And it reinforced something we believe deeply at the SEMI Foundation, that workforce development does not begin at graduation; it begins in grade school with early awareness and intentional exposure.Starting Earlier: Where the Semiconductor Workforce Truly BeginsBuilding a strong, future-ready semiconductor workforce does not begin in college, or even high school. It begins in the earliest years of science, technology, engineering, and mathematics (STEM) exposure.Since 2003, I have created STEM programming that introduces college majors and career pathways to K–12 students. At the SEMI Foundation, that work now connects directly to one of the most urgent workforce challenges of our time, ensuring the semiconductor industry has the skilled talent needed to support domestic manufacturing expansion and global competitiveness.When elementary and middle school students engage in hands-on STEM experiences, they build confidence. They develop technical vocabulary, critical thinking skills, and resilience. They begin to understand how the devices they use every day are designed and manufactured. That early spark matters, especially in industries like semiconductors, where awareness has historically been limited among younger students.Moving From Exposure to Industry ExplorationAs students progress, programming must move from exposure to exploration.Through SEMI Foundation initiatives, including hands-on camps, classroom modules, and industry-connected programming, students begin to see how semiconductors power everything from smartphones and AI to healthcare systems and clean energy technologies.Middle school and early high school programs should intentionally connect STEM learning to real-world applications:Engineering design challenges tied to semiconductor conceptsProject-based learning informed by industry practicesCareer speakers from manufacturing and technical rolesMentorship that reflects diverse entry points into the industryThis stage is critical for workforce development. Quality hands-on learning must be paired with representation and mentorship. Students need to hear authentic stories about different pathways into technical fields, whether through two-year degrees, apprenticeships, industry certifications, or four-year engineering programs.High School: Where Awareness Becomes PreparationHigh school is where exploration must transition into preparation.Structured career pathways, dual enrollment opportunities, industry certifications, internships, and apprenticeship models create tangible bridges between classroom learning and workforce entry.When students graduate with credentials aligned to high-demand sectors, including advanced manufacturing and semiconductor production, they leave with more than knowledge. They leave with validated skills and industry relevance.This alignment does not happen by accident. It requires coordinated partnerships between K–12 systems, higher education institutions, workforce agencies, and employers. At the SEMI Foundation, we work to support this alignment so curriculum reflects industry needs and students experience clear, navigable pathways into careers.When education and industry move in sync, skills gaps narrow, and regional economies strengthen.Sustaining Momentum: Postsecondary and Employer PartnershipPostsecondary institutions and employers play a pivotal role in sustaining momentum.Stackable credentials, registered apprenticeships, and paid work-based learning models allow students to build competencies while earning income. Clear articulation agreements between high schools, community colleges, and universities reduce talent loss and create seamless transitions. In the semiconductor industry, where technical precision and specialized skills are essential, these structured pathways are not optional. They are foundational.A Long-Term Vision for Semiconductor Workforce GrowthThe semiconductor industry powers nearly every aspect of modern life. But sustaining that innovation requires long-term workforce vision. The students I met in our 2025 summer camps reminded me of what is possible when exposure meets opportunity.When we start early, align intentionally, and collaborate across systems, we do more than prepare a workforce. We cultivate the next generation of innovators who will design, build, and lead the technologies shaping our future.Bia Hamed is Program Manager, Global Education Initiatives at the SEMI Foundation.

The semiconductor industry is hitting a structural inflection point: explosive AI‑driven demand, rapidly rising manufacturing complexity, and stringent sustainability expectations are converging at once. In this context, edge AI deployed directly on tools, sensors, and local controllers, is shifting from experimental to essential, particularly in fabs where milliseconds matter. SEMI’s timely workshop, Smarter Sensors, Smarter Fabs: AI at the Edge in Semiconductor Manufacturing, taking place March 18–19, 2026 in Milpitas, CA, will address this important topic.From sparse sensing to dense instrumentationTwo decades ago, most process tools relied on dozens of sensors per chamber. Today, leading etch, deposition, CMP, and lithography systems routinely integrate hundreds of sensing channels spanning pressure, flow, RF power, optical endpoint, vibration, and chemistry. At 3 nm and 2 nm, process windows are so tight that yield hinges on multivariate understanding of chamber conditions and tool state rather than a few independent alarms. Sensor proliferation has turned fabs into rich data environments—but also exposed the limits of traditional, centrally managed control.Why edge AI is displacing cloud‑only controlConventional architectures push heavy analytics to centralized servers or the cloud, with supervisory systems periodically updating recipes, setpoints, or dispatch rules. Across manufacturing, measured cloud round‑trip times commonly range from 800 to 2,400 ms, whereas edge systems co-located with equipment can respond in 15–45 ms, roughly 50–160× faster. For safety‑ and yield‑critical loops in semiconductor manufacturing, that latency gap is often unacceptable.At the same time, new generations of low‑power neural processing units (NPUs) and edge accelerators deliver tens of trillions of operations per second (TOPS) at single‑digit watt budgets, making always‑on inference viable inside tools, cameras, and controllers. The result is a decisive move toward edge‑native architectures: models execute where data is produced, while cloud resources are reserved for retraining and fleet‑wide learning.Edge AI on the line: control, inspection, and maintenanceIn process control, edge AI is enabling a shift from univariate threshold checks to multivariate models that understand the joint dynamics of sensor streams. Platforms today embed deep‑learning and statistical models directly at or near the tool, performing real‑time endpoint prediction and anomaly detection from high‑dimensional time series. Similar approaches are emerging in lithography and CMP, where local inference helps keep focus, overlay, and removal rate within spec before wafers drift out of control.Inspection and logistics are undergoing a similar transformation. Vision systems with embedded NPUs classify defects at line speed, often above 100 parts per minute, eliminating the need to ship large image volumes to a central cluster. Robots and autonomous mobile robots (AMRs) use local intelligence for short‑horizon planning and collision avoidance, while higher‑level systems focus on global scheduling and optimization.Predictive maintenance is one of the most mature applications: vibration, acoustic, temperature, and pressure data are analyzed locally to detect anomaly signatures hours or days before conventional thresholds trip. Reported benefits include reductions in unplanned downtime, longer component life, and lower maintenance costs when these models are integrated into manufacturing execution systems (MES) and maintenance workflows.Digital twins and agentic AI on top of edge dataDigital twins build on this sensing and edge‑analytics foundation. By maintaining virtual, live‑updated models of tools, lines, and entire fabs, they enable scenario testing, debottlenecking, and root‑cause analysis without putting WIP at risk. Vendors and early adopters report that such twins can shorten process‑node ramps and facility bring‑up by enabling thousands of “what‑if” experiments before physical changes are made.​Agentic AI is now emerging as the orchestration layer above these twins. In semiconductor case studies, agents connected to MES, advanced process control (APC), and planning systems have delivered double‑digit improvements in throughput, cycle time, and tool utilization by autonomously adjusting routing, batch sizes, and scheduling in response to live fab conditions. Other agents mine unstructured engineering notes and fault reports to accelerate root‑cause analysis, turning hard‑won lessons into repeatable, codified behavior.Sustainability as a first‑class requirementSustainability pressures are reinforcing this stack. Semiconductor manufacturing is energy‑ and resource‑intensive, and regulators and customers alike are demanding more transparency and improvement. Edge‑connected monitoring of energy, utilities, and emissions has already helped some fabs cut energy‑related costs by around 20 percent through tighter control of HVAC, process gases, and idle modes. Research initiatives such as imec’s Sustainable Semiconductor Technologies and Systems (SSTS) program are using virtual fab methods and detailed life‑cycle assessment to guide process and equipment choices for lower environmental impact.Strategic takeaways and where to learn moreThe trajectory is clear: fabs that combine dense sensing, edge AI, digital twins, and agentic AI are building toward continuously learning, self‑optimizing operations. Architectures will need to be edge‑first rather than cloud‑only. Simply adding sensors without local intelligence will not deliver competitive advantage, and environmental KPIs are likely to be optimized with the same rigor as yield and cycle time.For practitioners who want to translate these trends into roadmaps, the Smarter Sensors, Smarter Fabs: AI at the Edge in Semiconductor Manufacturing” workshop (March 18–19, 2026, Milpitas, CA) spearheaded by the SEMI Manufacturing Coalitions* will bring together experts in sensing, edge architectures, digital twins, and agentic AI to share concrete deployments and architectures tailored to semiconductor fabs.*The SEMI Manufacturing Coalitions include Smart Manufacturing, Fab Owners Alliance (FOA) MEMS and Sensors Industry Group (MSIG), Advanced Packaging Heterogenous Integration (APHI) and Semiconductor Components, Instruments, and Subsystems (SCIS). Anshu Bahadur is Senior Program Manager, Technology Communities at SEMI. Mark da Silva is Senior Director, Manufacturing Coalitions at SEMI.

On February 20, the U.S. Supreme Court ruled that the International Emergency Economic Powers Act (IEEPA) does not authorize the use of tariffs, invalidating certain tariffs imposed by the Trump Administration under the statute.SEMI shared the following statement on the ruling: SEMI acknowledges today’s U.S. Supreme Court ruling regarding the use of tariffs under the International Emergency Economic Powers Act. As the implications of the decision become clearer, we welcome further guidance and remain committed to working with the U.S. government to strengthen semiconductor supply chains, support innovation, and expand domestic chip manufacturing.Continued investment in U.S. manufacturing depends on stable, reliable access to the highly specialized equipment, materials, and components essential to semiconductor production. Driven by global demand, breakthrough innovation, and record levels of investment, the semiconductor industry is projected to reach a $1 trillion market this year. Clear, consistent, and predictable trade policy remains critical to providing manufacturers – particularly small- and medium-sized enterprises – the certainty necessary to sustain long term investment, scale production, and reinforce technological leadership in the United States.Visit SEMI Global Advocacy to learn more about public policy efforts and developments as well as how your company or organization can get involved.Royal Kastens is Vice President, Global Public Policy Advocacy at SEMI.

When most people hear “semiconductors,” they think of something abstract: tiny chips, complex equations, cleanrooms hidden behind glass. Relevant, sure, but distant. Compare that to professions like architects or doctors. We can picture their training. We understand their impact. We see a clear path from curiosity to contribution. The semiconductor industry deserves the same clarity and more. Because semiconductors don’t just power devices. They power progress. The semiconductor industry plays a crucial role in sustaining modern life and will remain instrumental in the future. We know this all too well because most of us work within this industry. It isn’t abstract or difficult for us to see how we fit into the grand scheme of this critical industry. It is important to reflect on our initial motivation for entering this field. The technological advancements we are currently developing were likely beyond consideration when we began our careers. Historically, we’ve done a great job of explaining how someone becomes a doctor or an architect: education, residency or apprenticeship, specialization, growth. The semiconductor industry can and must do the same.Imagine clearly mapped pathways that show:High school students how math, science, and technical programs connect to real semiconductor jobsCommunity college and university students how internships, co-ops, and labs translate into manufacturing, design, or research rolesCareer-changers and Veterans how reskilling programs, certifications, and on-the-job training can open doors without starting overWhen people can see the steps, the industry becomes less intimidating and far more inviting.Introducing ChipPathThis is where the SEMI Foundation’s newest platform, ChipPath, comes in! ChipPath, powered by the National Network for Microelectronics Education (NNME) , makes it easier for individuals to understand where they fit today and where they can grow tomorrow. “ChipPath marks a major step forward in our mission to connect people to opportunities in the semiconductor industry,” said Shari Liss, Vice President of Global Workforce Development and Initiatives at SEMI. “By combining career exploration, education pathways, and live job data into one platform, we’re not just helping individuals find jobs, we’re helping them build lifelong careers that drive innovation and impact.”ChipPath helps users explore roles across the semiconductor ecosystem, not just by job title, but by skills, interests, and pathways. A student interested in problem-solving, automation, or precision work can see how those interests translate into manufacturing, technician, or engineering support roles. A career-changer with experience in logistics, quality, or data analysis can quickly identify how their existing skills map to in-demand semiconductor jobs.This shift from “Do I belong here?” to “I can see myself doing this” is foundational. When people can visualize a role that fits them, they are far more likely to pursue it with confidence.Perhaps most importantly, ChipPath doesn’t end with exploration and preparation, it connects talent to actual job openings across SEMI member companies. By serving as a shared access point between job seekers, educators, training providers, and employers, ChipPath strengthens the entire talent ecosystem. Candidates gain visibility into opportunities they may never have discovered on their own. Employers gain access to a broader, more diverse, and better-prepared pool of talent aligned to semiconductor workforce needs.This connection transforms workforce development from a fragmented effort into a coordinated system; one where awareness, training, preparation, and hiring reinforce one another.Access for job seekers doesn’t end once they apply. ChipPath includes resources that help them prepare for the next critical step: the interview. Through guidance on interviewing expectations, communication, and workplace readiness, ChipPath helps candidates show up informed, confident, and prepared to engage. This preparation reduces anxiety for candidates and increases the likelihood of successful matches for employers.When candidates understand how to talk about their skills, experiences, and potential in industry-relevant terms, interviews become more productive, and hiring decisions become clearer.For employers, ChipPath is more than a platform, it has the potential to be a workforce multiplier. It reduces friction for job seekers, improves candidate readiness, and helps align skills with real demand across the industry. By leveraging ChipPath alongside outreach and engagement strategies, employers can help create a talent journey that is easier to navigate, access, and succeed in.When people can see where they fit, understand how to prepare, and connect directly to opportunity, the semiconductor industry becomes within reach.Job seekers today want and need more than just a salary; they want meaningful work and pride in what they do. Our industry offers these opportunities, but we must guide them to find it.Visit http://nnme.org/chippath to explore the platform, build your profile, and take your first step toward a future in semiconductors.Melinda Gomez is Program Manager, Veteran Initiatives at the SEMI Foundation.

Aki Fujimura has been at the forefront of chip design innovations from the beginning of his career and his technology leadership continues today. He serves as Chairman and CEO of D2S, co-founder of the eBeam Initiative, President of BACUS, and a Governing Council member of the ESD Alliance, a SEMI Technology Community. At Tangent (now Cadence), Fujimura and Steve Teig (a chip designer for the last 20 years and now Vice President and Distinguished Engineer at Amazon) built the first commercial over-the-cell routing system dedicated to fully synchronous designs with timing assurance and automated test-scan insertion. Fujimura and Tom Kronmiller developed LEF/DEF for efficient representation of Manhattan routing, both used as standards in the automated place and route (P R) flow to this day. He again teamed with Teig and Kronmiller to develop the X Architecture, an interconnect architecture based on the pervasive use of 45o diagonal routing. I was thinking about his background as I called him to chat about his evolution from chip design before focusing on chip manufacturing via eBeam technology at D2S.Smith: Let’s talk about your journey from focusing on how to do physical design of chips to chip manufacturing. How did this happen?Fujimura: GPUs weren’t a thing until late 1990s. With CPUs, Manhattan design was the obvious choice for computational efficiency. Largely gridded metal n that went up and down, and metal n+1 that went left and right with vias to connect the line segments were how all automated layout worked. PCB routing and packaging (even back then) used diagonal routing and even curved routing. But chip P R was all Manhattan. That was still true when we worked on the X Architecture at Simplex Solutions (now Cadence). ATi (now inside AMD), NVIDIA and several other GPU companies started in the late 1980s to 1990s, but they were targeting video and gaming more than scientific computing at the time. It’s when Teig came up with the idea for the X Architecture that he wanted to know if 60-degree routing was possible “because a hexagon tessellates a plane.” A good question. I set out to try to find out what the actual limits were in manufacturing that create the limitation to Manhattan shapes. I got introduced to the late Bill Arnold of ASML, who then introduced me to a lot of people in manufacturing who helped me get the answer. Naoya Hayashi of DNP was instrumental in helping me understand that mask making is where the limit exists. Hayashi-san kindly explained to me about the two mask writers. I had to dig around a lot more to make sure that that was the only barrier, but that’s how I came to understand that before masks, everything is data, and after masks, everything is physical. Mask making is the key that enables 45 degrees, but not 60 degrees. The lessons I learned then are still very important to me today. That’s when I saw and appreciated the opportunity there is for software for semiconductor manufacturing.Smith: But you still couldn’t use GPUs for the X Architecture work?Fujimura: Right. Way too early. The idea that GPU-accelerated gaming machines can be connected together to do video editing, or that large scientific simulations can be done on a connected set of gaming machines, was being explored in the 1990s already. It was only 20 years ago (2006) when Jensen Huang announced his bet with the CUDA software stack for general purpose GPUs (GP GPUs) for nodes in racks of CPUs, GPUs, memory and communication to create the modern scientific computer. Six years later in 2012, AlexNet won the ImageNet Large Scale Visual Recognition Challenge (ILSVRC) with CUDA, and the rest is history. But no, we didn’t use GPUs at Simplex. But we did help design GPUs, including with the X Architecture.Editor’s Note: ILSVRC evaluates algorithms for object detection and image classification at large scale. Smith: Now, everything you do at D2S is with GPU acceleration. When and how did that change come about?Fujimura: It was back in 2009, two years after D2S was founded. An extraordinary engineer, Harold Zable, noticed that simulation-based manipulation (rather than rules-based manipulation) of mask shapes, both for wafer manufacturing and for mask manufacturing, would be the ideal application for GPU acceleration. Fast-Fourier Transforms (needed for lithography simulation and optical proximity correction (OPC)/inverse lithography technology (ILT)) and Gaussian manipulations (needed for eBeam mask simulation and mask process correction (MPC) are nearly “free” in terms of compute time on GPUs. You still have to get the data in and out efficiently, but you can do pretty sophisticated computing without much overhead. At the same time, multi-beam based eBeam writing was getting momentum, first in wafer direct write applications. In 2007, at the BACUS conference in Monterey, Calif., IMS—then a well-respected research organization in Vienna—published a paper saying that multi-beam for mask writing is what they’d like to do. The wafer market is much bigger, but this technology is more suited for mask writing, where write times are measured in hours per mask. “Wafers Per Hour” is the measure in wafer manufacturing, so mask writing gets to flip the division. We were looking at a mask design and mask manufacturing world that should be doing simulation-based manipulation rather than rule-based. That’s better with GPUs. On top of that, maybe the world is going to go to multi-beam writing, going away from four decades of variable-shaped beam (VSB) writing. And I knew from the X Architecture experience that VSB was the only thing in the eco-structure that restricted mask shapes to be Manhattan or 45 degrees. In fact, with multi-beam, any curvilinear shape within the limits of resolution of a given pixel size can be freely written on the mask. The only barrier then to having curvilinear masks would be the software stack and trying to compute it with CPUs only. We knew GPU acceleration was the answer. Smith: Was it just totally an accident that multi-beam and GP GPUs happened at the same time?Fujimura: Yeah, it was. However, just as when multiple people simultaneously invent the same thing without knowing about each other, the environment and times in which we live have a lot to do with this. So, I guess, it’s not really just “luck.” But GP GPUs in 2006 and IMS Multibeam in 2007, I think that’s luck.Anyway, D2S became the GPU-acceleration partner for the semiconductor manufacturing industry and decided to work only on things that can be accelerated by GPUs in 2012.Smith: What trends do you see going forward in the next three to five years?Fujimura: A move toward curvilinear mask features, as well as an increased interest in curvilinear wafer targets as designers become aware that the manufacturing side has established a solid path for curvilinear mask shapes. We’re leaving a lot of margin on the table to accommodate gridded Manhattan assumptions, and that’s really no longer necessary from a manufacturing standpoint. I think electronic design automation (EDA) should be working on enabling curvilinear designs, because the door is open for the design world to explore curvilinear chip design and to reap compelling benefits in terms of power/performance and reliability.Editor’s Note: While Manhattan geometries are rectilinear shapes aligned to vertical and horizontal axes, curvilinear design introduces smooth, continuous curves into layouts and masks, leveraging advanced computational lithography and mask-writing technologies. This improves pattern fidelity, electrical performance and manufacturability at advanced technology nodes.About Aki FujimuraAki Fujimura is chairman and CEO of D2S, Inc., and managing company sponsor of the eBeam Initiative. Previously, Fujimura was CTO at Cadence Design Systems, President/COO and inside board member of Simplex Solutions, and VP and inside board member at Pure Software. He co-founded Tangent Systems (acquired by Cadence).Fujimura, made a SPIE fellow in 2023, serves as President of the SPIE BACUS Technical Group. He serves on the governing council of the ESD Alliance, a SEMI Technology Community. Fujimura was on the board of HLDS, RTime, Bristol, S7, and Coverity, Inc.Fujimura received his BSEE and MSEE degrees from MIT.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

Presentations from SEMICON West’s “The Convergence of Semiconductor Manufacturing and Design” offer great insights into the collaboration between the two, as I was recently reminded by presenter Sutirtha Kabir, R D Engineering, Executive Director at Synopsys.Reviewing his talk “Revolutionizing Silicon to Systems Design: Unlocking the Future with 2.5D and 3D Multi-Die Innovations” was a good kick-off for our discussion that covered the continuous need for collaboration and where AI fits. Kabir, as I quickly learned, is a technical innovator and articulate communicator passionate about ongoing collaborations between design and manufacturing. Today’s blog post is the second in a four-part series featuring presentations from the SEMICON West design program, organized by the ESD Alliance, a SEMI Technology Community. The first blog, with Dave Kelf, CEO of Breker Verification Systems, appeared on January 6 (“Circular Collaboration Leverages EDA Advances”).Smith: How do you define collaboration between design and manufacturing?Kabir: Multi-die design and advanced packaging are a big focus of high-performance computing (HPC) and AI chips. Engineers are trailblazing and foundries are coming up with new stacking combinations. For this reason, design and manufacturing teams need to be closer than ever. Solutions must be made available to give ample visibility to manufacturing from the very start of the design process. Single die design has been done for 15 to 20 years with a continuity of power, area, and performance (PPA). Design flows, methodologies and the ecosystem between design houses, EDA vendors and foundries are mature and stable. The conundrum is that it's a different situation with multi-die designs. Not only is multi-die emerging rapidly, but the types of design innovations are different.We have been working closely with our foundry partners to move multi-die innovation forward by enabling more advanced process and packaging technologies. I don't see this slowing down as they are coming up with different ways of doing designs. Design teams are collaborating closely with the foundries to take advantage of the benefits of these new multi-die designs.Smith: You mentioned new stacking combinations and collaboration with the foundries. What about collaboration with the OSATs? Kabir: Generally, it’s both silicon foundries and OSATs. With advanced packaging, both play a significant role depending on the types of applications being targeted. Design house targets may shift from the traditional silicon foundry to several OSATs. For example, if an organic interposer is required, the collaboration could be with an OSAT in conjunction with the silicon foundry. There are many possible collaborations that may be required. The point I’m trying to make is that there is a strong need for collaboration between EDA and the foundries during design that continues through manufacturing and test.Smith: What trends in general are driving the need for this collaboration?Kabir: The trends are performance and scalability and the need for high-performance compute. Look at some of the mega-chip systems coming out today compared to the bigger systems from five years ago. HPC was not driving that much in 2.5D. The big interposers used to be on silicon, maybe 1.2 to somewhere around less than three reticle sizes. Today, the reticle limit is more than 5X. Leapfrog to today, and the configuration has changed where the state of the art is to use an organic interposer with multiple embedded bridges (up to 20 or more) buried inside the interposer to support high-speed interconnect. The organic interposer with multiple layers on the front side and back side communicates with bridges and the SoC and HBM that sit on top of that interposer.3D architectures stack dies with GPUs and a large amount of HBM such as an HBM4 memory stack. The memory stacks may be 8 or 16 high. All of this memory needs to be as close as possible to compute for scalability. In terms of the high-power demand, the designer needs to make sure that the voltage that is pushed from the bottom of the stack can feed the power hungry SoC blocks on top of the 3D stack. At the end of the day, EDA is all about giving design and manufacturing houses the capability to predict how a design is going to perform in all different kinds of scenarios. EDA must keep up with this trend and that requires collaboration.Smith: What about the verification side, specifically system verification? Kabir: Let’s say I am using a spreadsheet and doing back-of-the-napkin calculations, a technique that used to work well for single die or design blocks. Multi-die doesn't scale since multiple heterogeneous dies in a single package must be considered. Design planning must include directional changes to measure the effects with key performance indicators. The challenge is to correlate signoff and verification. Signoff engineers can no longer just verify at the end of the design cycle. Instead, it has become a continuous process that transcends the flow from design planning through implementation and signoff and release to manufacturing.The industry is repeating a pattern from about 20 years ago, when single-die design evolved from relatively naive approaches to much more sophisticated EDA-flow-driven methodologies.Smith: As you drive the tools forward, who are your counterparts on the manufacturing side? Kabir: It depends on the different stages of design—design planning, implementation or signoff. It starts at the architecture stage from the left when architects and physical design engineers are doing floorplanning. The term design technological co-optimization (DTCO) has evolved into S (system)TCO now because we are trying to co-optimize system design and technology. I'll give you a simple example. A working chip manufactured in a certain technology node is going to be used in a multi-die design. Is the existing chip technology good enough to support the design or will it require a new chip at a different node? In either case, how does an engineer work with the manufacturing house to make sure it has the right metal layers or a different number of metal layers or a different metal width or some other property on the technology side? Designers need to make data-driven decisions based on the configuration and technology numbers to meet power budgets.In the past, what was once managed through designer-ASIC house-manufacturing interactions are now increasingly being handled by EDA flows as part of design implementation.Smith: Ultimately, it's driven by business. The hard work and decisions are made by two teams of knowledgeable technical people who must come together.Kabir: And then of course it has to be rolled into program management, business development and all this needs to be supported by data. We all recognize that the design window is not increasing. It’s always about trying to get more out in less time with less people. That doesn't help the equation.Bob Smith: How does AI fit into this and how is it best leveraged? Kabir: I’m hearing, learning, and reading about the tremendous advantages AI could bring. AI has a huge role to play, but it won’t eliminate the need for savvy design and verification engineers.Multi-die design brings together different users from different tool backgrounds. Even the language between a packaging person and a silicon person is different. The terminologies they use are different, as are the ways they have done design over the last 15-20 years. The same applies to thermal, power or signal integrity engineering. Bringing them together requires that EDA will provide platforms where the whole system design, including chip design, is managed. That’s a tall ask for people from all different backgrounds to come in, learn different technologies and tools within a short time. This is where ChatGPT or Microsoft’s Co-Pilot can be applied in the EDA world today to quickly find solutions by reading through manuals, application notes, forums and the like to find solutions. This use of AI agents can save tremendous amounts of time for designers. Another aspect that can be positively impacted are roles. We have customers coming to us and brainstorming on the use of workflows and methodologies, instead of the design aspect. Scalability from the human perspective has become difficult because of the need to closely guide engineers to get them up to speed on new technologies and workflows. This is where Agentic AI can deliver a huge productivity boost. It's not replacing anyone. It's getting them to decisions and end results faster.Smith: Can Agentic AI play a big role? Kabir: Current AI is like the person who, when asked a question, has to give an answer even if it’s the wrong answer. The same thing is going to happen when we bring in all these EDA technologies with AI capabilities.The point I'm trying to make is how do we verify that AI is doing the right thing? In EDA, one of the biggest questions and concerns is if a result or outcome or design can be verified. If it can't be verified accurately, verification engineers will not trust what AI is telling them no matter how fantastic the algorithm is. The verifiability of AI solutions is important for EDA. The key question is: Why would I trust what your tool is telling me to do?EDA flows that are more mature rely on decades of expertise, thorough documentation, and various scenarios to train AI algorithms. Those are the AI-powered EDA flows that I trust the most. About Sutirtha KabirSutirtha Kabir, an Executive Director of R D for Synopsys’ 3DIC Compiler, has over 20 years of product engineering experience, driving, building, and inspiring teams across companies in the EDA industry. In his role at Synopsys, he supports construction and analysis of multi-die systems including stacked ICs plus Interposer configurations. Prior to joining Synopsys, Kabir was a Group Director of Engineering at Cadence. Kabir has a Master of Science degree in Electrical Engineering. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

2025 was a fast-paced, exciting, and impactful year for the SEMI Standards team. We developed 14 new standards on crucial topics like supply chain traceability, defect mitigation, compound semiconductor materials, and so many more. In addition, we introduced the SEMI Global Standards Summit (GSS) in North America, where we created new standardization roadmaps and continued pertinent sustainability conversations from the inaugural GSS at SEMICON Japan 2024. We’re also excited to announce that we closed out 2025 with an impactful Q4. From December 17-19, we held our SEMI International Standards Meetings during SEMICON Japan. More than 15 Task Force meetings and 5 Technical Committee meetings were held, followed by an award ceremony. The brand-new Digital Twins in Manufacturing Task Force was also established to define and standardize a digital twin framework that supports consistent and scalable implementations. We published the new SEMI T27 standard in Q4, and we celebrated several outstanding volunteers for their contributions to the SEMI Standards Program at both SEMICON West and SEMICON Europa. As we reflect on Q4, it’s apparent how important collaboration is to the success of SEMI Standards. By working together, we lay the foundation for groundbreaking innovations in microelectronics manufacturing. The SEMI Standards team would like to extend a warm and sincere thank you to everyone who donated their time and expertise to define the future of our industry. These efforts would not be possible without your commitment and support.Still, it’s never too late to join the SEMI Standards Program. Learn more about membership and how you can help influence the next phase of semiconductor manufacturing. Q4 2025 HighlightsTakeaways from the International Standards Meeting at SEMICON JapanIn Q4, the SEMI Standards team held its International Standards Meeting at SEMICON Japan, where several task forces convened to set standards for compound semiconductor materials, information and control, traceability, and more. From December 17-19 at Tokyo Big Sight, the SEMI Standards team supported these technical committees in advancing several key standards revisions, including SEMI E181, Specification for Panel FOUP for Panel Level Packaging, and SEMI E182, Specification for Panel FOUP Loadport for Panel Level Packaging. In addition, a new Maintenance Robot Communication (MRC) Task Force was established with the objective of defining communication protocols and data exchange specifications between maintenance robots and equipment.The next SEMI International Standards Meeting will take place from May 11-14 in Albany, New York, during the SEMI Advanced Semiconductor Manufacturing Conference (ASMC). Digital Twins in Manufacturing Task Force Although the terms “digital twins” and “digital twin frameworks” are becoming more prevalent in the semiconductor industry, there’s still much debate on what they cover. To develop concrete, standardized definitions for each, the SEMI Standards team established the Digital Twins in Manufacturing Task Force in Q4. After the task force defines these crucial terms, it will then create definitions for internal digital twin components outlining baseline capabilities, discovery mechanisms, prediction quality metrics, unified model interfaces, and lifecycle management. Eventually, the task force will outline a framework for Digital Twins compatible with existing guidelines like SEMI Standard E133 or ISO 23247. The SEMI Digital Twins in Manufacturing Task Force is open to industry stakeholders. To participate, join the SEMI International Standards Program or learn more. Standards Awards at SEMICON West and SEMICON Europa SEMICON West honoreesQ4 was also a time to celebrate some of the talented individuals who make a difference in the SEMI Standards Program. At SEMICON West and SEMICON Europa, we honored 25 accomplished industry leaders across the following five award categories for their commitment and participation. Merit Award winners led projects to successful completion at the task force level. SEMICON Europa honorees: Judith Wittmann, Cristina Sanna, Peter Wagner, Friedrich Passek, Frank Riedel SEMICON West honorees: Dave Dunne of Applied Materials, Kirsten Smith of UCT/ChemTrace, Tommaso Orzali of ASML, Dr. Tyler Harrison of Teledyne MEMS, and Dr. Mary Ann Maher of SoftMEMSSEMICON Europa honorees: Christian Kranert of Fraunhofer IISB, Enrica Cela of Soitec, Hans-Christian Alt of the Munich University of Applied Sciences, and Ulrich Kretzer of Freiberger Compound Materials GmbHLeadership Award winners bolstered the SEMI Standards program through member recruitment, mentoring, and training efforts. SEMICON West honorees: Michael Potts of Arcadis, David Kandiyeli of KINETICS Equipment Solutions Group, and Per Nelson of Daikin AmericaSEMICON Europa honorees: Frank Riedel and Judith Wittmann of Siltronic, Cristina Sanna of GlobalWafers, and Jochen Ruth of Pall CorporationHonor Award winners have demonstrated long-term dedication to advancing SEMI Standards.SEMICON West honorees: Steve Martell of Nordson Test Inspection Americas, Lucian Girlea of Nikon Precision, and Dave Huntley of PDF SolutionsSEMICON Europa honorees: Peter Wagner of SEMI Standards, Fritz Passek of Siltronic, Arnd Weber of SiCrystal GmbH, and Frank Petzold of trustsec IT solutions GmbHCorporate Device Member Award winners are participants from the user community who act as corporate representatives for the SEMI Standards Program from the device manufacturer side. Stefan Radloff of Intel was honored with this award at SEMICON West. Technical Editor Appreciation Award winners are adept at translating complex technical information into clear and precise language. Dr. Alissa M. Fitzgerald of A.M. Fitzgerald Associates became the award recipient in 2025. Workshops at SEMICON WestOn October 8, the SEMI Voltage Sag Immunity Task Force hosted its Enhancing Voltage Sag Immunity workshop to address fab downtime caused by voltage sags. The workshop convened more than 20 industry professionals to review the limitations of SEMI Standard F47. They found that while 20% of downtime instances can be attributed to three-phase events, SEMI Standard F47 does not require testing for such occurrences. As a result, the Voltage Sag Immunity Task Force is developing a draft revision of SEMI Standard F47, scheduled for balloting in March 2026. If you missed this workshop, you can access the recording and presentation here. October 8 also saw the exciting return of the Analytical Workshop, hosted by the SEMI Liquid Chemicals Committee after a multi-year hiatus. This year’s workshop addressed near-term challenges and advancements identified by the International Roadmap for Devices and Systems (IRDS). It covered chemical quality and consistency, trace metallic impurities and improvements in ICPMS instrumentation, automated instrumentation for online measurements, detection for particle precursors and sub-10nm particles in liquids and on-wafer, and organic particle precursors identification using FTIR-ATR, SERS and AFM-IR. If you missed this workshop, you can access the recording and presentation here. The 2026 call for abstracts will be announced soon. Lastly, the SEMI Standards and SEMI University teams worked together to host Semiconductor Device Manufacturing in a Cleanroom, a workshop meant to introduce best practices for overcoming contamination problems in the cleanroom. By reviewing different sources of contamination, reviewing analytical techniques for quality control, and performing cleanliness testing, the course aims to help cleanroom facilities improve production reliability and yield.New and Revised Standards Released in Q4October 2025November 2025December 2025Get InvolvedSEMI Standards development activities take place throughout the year in all major manufacturing regions. To participate, join the SEMI International Standards Program.SEMI Standards are available through individual download purchases or online via SEMIViews. Watch this video to learn more about how SEMIViews offers a cost-effective and streamlined way to access 1,110+ SEMI Standards. Sign up for a 30-day SEMIViews trial.For more information, please visit the Standards website and events page. For any questions regarding SEMI Standards activities, please contact your local SEMI Standards staff.Paul Trio is Director of Standards at SEMI.