Imaging’s role is expanding beyond lithography and inspection into assembly and test. As packages incorporate multiple dies, advanced interconnects, and heterogeneous materials, imaging provides critical visibility into structures that electrical test alone cannot fully characterize.

At SEMICON West, speakers described imaging’s transformation from a reactive inspection function into a proactive intelligence layer. As fabs embrace AI-driven manufacturing, imaging systems are becoming essential data sources for learning, prediction, and optimization across the factory.

Advanced Imaging sessions at SEMICON West underscored a subtle but critical shift: imaging performance is increasingly constrained by materials behavior, particularly advanced dielectrics.

At SEMICON West, the Advanced Imaging sessions reinforced a pivotal industry shift: imaging has moved from a supporting manufacturing function to a strategic enabler of AI-driven semiconductor innovation.

Large-field lithography is emerging as a focal point in the Advanced Imaging, reflecting the industry’s shift toward panel-level packaging and larger form factors. These trends challenge long-standing assumptions about lithographic tradeoffs between resolution, depth of focus, and throughput.

At SEMICON West, NY CREATES provided a deep examination of data security risks across semiconductor fabrication ecosystems. Their perspective reflects a reality that is becoming clear: in semiconductor manufacturing, data is both an invaluable asset and a critical vulnerability.

Artificial intelligence (AI) is scaling at a pace that is reshaping semiconductor roadmaps, data center design, and long-term infrastructure strategy. AI promises many economic and social benefits; but the growth comes with an escalating demand for power, and energy has emerged as a major challenge.SEMI, as the global semiconductor and electronics association connecting over 4,000 companies, continues to unite the entire ecosystem to “bend the curve” – to maximize AI performance while minimizing power consumption. In a series of successful, sold-out workshops that the SEMI Smart Data-AI Initiative held on this topic, a resonant theme has emerged: sustaining AI progress requires energy-efficient computing with holistic co-design and co-optimization across materials, devices, systems, data transmission, data centers, emerging architectures and software. While this dialog is an important starting point, the ultimate goal is to drive concrete action through collaborative innovation.The AI Energy ChallengeAI training compute for frontier models is growing at an estimated 4–5x per year, driving unprecedented demand for hardware capability and infrastructure capacity. That trajectory has resulted in a global “data center gold rush” and is testing energy availability limits. As model sizes scale exponentially, so too does the energy required to train and deploy them; and power consumption has become a significant limiter to performance gains. Further, this increases heat dissipation, and requires innovations like direct liquid cooling.Modern AI and high-performance computing systems now operate at levels comparable to small cities, with tens of megawatts per installation and a trajectory toward gigawatt-scale data center campuses. Grid capacity—both in the U.S. and globally—may be challenged to keep pace with projected demand. Thus, AI infrastructure is no longer just a technical challenge, but it is an energy, systems, and policy challenge.System-Technology Co-OptimizationContinuous advances in chip and inference efficiency have delivered orders-of-magnitude improvements over many decades. These gains must now be expanded by holistic co-optimization of the entire compute system from silicon technologies to data center to the grid.For example, processors can be made more efficient by customizing them for specific workloads. However, only part of total data center power is consumed by the processor itself. A significant portion is used by data movement, power conversion and cooling. The energy required to move data increases dramatically with distance. Moving bits across packages, boards, and networks can consume far more energy than the compute operations themselves. This makes locality a critical design principle. The opportunity—and necessity—therefore lies in cross-layer optimization: efficient compute, efficient communication, and intelligent power management across the entire system. Not surprisingly, advanced packaging and integration are becoming central to performance. These technologies can enable architectures that tightly couple compute, memory, and I/O—using 2.5D and 3D integration techniques—reducing energy per bit and increasing bandwidth. Photonic interconnects and low-power materials can further lower the cost of processing and moving data.The bottom line is that incremental chip-level gains alone will not be sufficient and energy optimization cannot be siloed—system-technology co-optimization is needed.Hardware-Software Co-optimizationKeeping data as localized as possible depends as much on software algorithms as it does on hardware architectures. The challenge is that the development cycles are mismatched: new software models can be developed in months, while designing and fabricating new hardware can take years. While this cycle mismatch is fundamental, closer coordination between hardware and software developers can significantly improve efficiency. For example, offloading selected functions in the algorithm, including distributed DPUs, and reducing the level of data precision can reduce energy use. Partitioning workloads logically across the hardware/software stack between cloud services and compute-on-edge can also reduce energy appreciably. Further, risk mitigation techniques—for example, building in strategic redundancy—can make future designs more resilient to shifts in software algorithms and models.Diverse Computing ModalitiesWhile AI dominates current infrastructure investment, the future of computing will likely include multiple, diverse computational modalities such as quantum, neuromorphic, photonic and analog computing.Different computational paradigms will be applied where they are most effective. For example, quantum computing is likely to complement—not replace—classical systems; especially for specific classes of problems where it offers exponential advantages. However, progress in quantum computing is tightly coupled to advances in semiconductor infrastructure. Error correction, orchestration, and hybrid algorithms all depend on high-performance classical systems operating with low latency alongside quantum processors. While there is no single silver bullet, system-level design can ensure that multiple computing modalities work together within unified workflows spanning edge, cloud, and exascale environments.Why It Matters What to WatchEnergy will now be a key constraint for AI performance and infrastructure expansion.The evolution of gigawatt-scale AI campuses and their interaction with public energy grids will accelerate – or slow down – AI growth.Data movement, memory bandwidth, interconnect efficiency, advanced packaging and heterogeneous integration will be strategic levers. Enhanced system-technology co-optimization and integration of advanced technologies like 3D ICs and photonics will be critical.Co-optimization across hardware, software, and systems will be required.Future architectures will blend classical and emerging compute modalities like quantum, photonic and neuromorphic.In conclusion, AI has become a defining global force with much promise, but its trajectory will be shaped by technology, energy and infrastructure economics working together. This is a formidable challenge because it requires many diverse players with divergent priorities to collaborate effectively.We invite you to join the SEMI Smart Data-AI initiative to collaboratively address this challenge and help realize AI’s full potential sustainably. Our next workshop in this series will be on September 9 in Silicon Valley – please join us for this exciting event.SourcesSEMI Smart Data-AI Initiative – Future of ComputingEnergy-Efficient Computing for AI and Beyond, SEMICON West, October 2025Sustainable AI Systems, SEMI HQ, March 2026About the AuthorsDr. Pushkar P. Apte is the Strategic Technology Advisor for SEMI Global Lead for the Smart Data-AI Initiative Dr. Melissa Grupen-Shemansky is Senior VP and CTO of SEMI

With edge AI emerging as a clear driver of smart manufacturing, SEMI hosted a two-day workshop detailing the future of this technology. The workshop, Smarter Sensors, Smarter Fabs: AI at the Edge in Semiconductor Manufacturing, was held in-person from March 18-19 in Milpitas, California. It convened industry professionals to explore how AI-driven sensors and edge intelligence are fostering scalable and resilient solutions for the next generation of semiconductor manufacturing. The workshop took place across four sessions, with each highlighting a unique edge-AI implementation area – including process control, yield enhancement, tool coordination, and predictive maintenance – and featured keynotes from leaders at Lam Research and KUKA. Didn’t get a chance to attend in person? View this workshop on demand. Session 1 - Smart Sensors and Edge Intelligence for Advanced Process Control​The semiconductor industry has always been defined by precision. However, as device architectures shrink to angstrom-scale dimensions, and as wafers become thinner and more fragile, traditional process control tools are reaching their limits. Sampled, low-frequency, univariate monitoring systems were built for an era where deviations were visible, failures were catchable later, and a handful of sensors per tool were enough to keep yield in check. Session 1 explored the latest sensor technologies, discussing how data collection at the point of production, with AI embedded directly into the tool, is becoming paramount for success. Advanced in-situ sensors were brought up as an example of this in practice. Although these sensors are generating richer signals than in the past, reaching lower latency requires AI models deployed at the edge.In addition, AI is extending into the physical world through robots that can handle various tasks autonomously. These robots are enabled by digital twins that provide simulation environments for training and validation before they ever see the fab floor. The common thread across Session 1 was the growing need for data and knowledge integration in fabs. Smart sensors must be built into AI systems, and those systems must be scalable across tools without sacrificing speed or reliability. Finally, the insights they generate must flow back into maintenance optimization and equipment health monitoring to promote a continuous cycle of learning. Session 2 - Yield Enhancement Through Edge-Driven Defect Detection and Classification​ Session 2 focused on how edge AI models, process sensors, and image data can identify yield-impacting defects earlier in the manufacturing process. As semiconductor devices lean into 3D architectures, the complexity and volume of data have outpaced the capabilities of traditional monitoring tools. Today's fabs are required to evaluate terabytes of inspection images per hour, as well as tool sensor traces that require analysis across dozens of parameters simultaneously. Each speaker approached this challenge from a different angle, yet the solutions fit together into a coherent architecture. One introduced Gaussian Process Regression, a model for assessing both predictions and uncertainties, as a statistically rigorous, data-efficient method for learning "golden trajectory" baselines for tool sensor signals. This generates actionable scores and maintenance guidance beyond standard anomaly alerts. Another speaker demonstrated the ability of deep learning models to triage multi-gigabit-per-second image streams in milliseconds. AI-based defect classification was shown to compress root cause analysis timelines from days to hours, with demonstrated gains of a 0.3% die yield recovery and 0.5–1% yield exposure prevention. Predictive metrology for RF filter frequency also assessed device performance using upstream process data, with less than 0.02% error.Lastly, a software-defined automation framework built on open standards and vendor-neutral architecture demonstrated effective workload consolidation onto a single edge platform. It was shown to be scalable across fabs without replacing legacy infrastructure.These presentations stressed the importance of measurement and action in real-time at the tool level. Gathering information as early as possible, using AI to triage and classify, and feeding insights back into process control and maintenance workflows, allows for a continuous cycle of improvement.Session 3 - Autonomous Work in Process Movement: Robots, Sensors, and Edge AI Coordination​The "lights out" factory is shifting from an aspiration to a concrete, engineering roadmap. To fully realize this, each presentation in Session 3 highlighted the importance of supplementing human-dependent workflows with AI systems that can act in real-time. This shift will require a mix of deep reinforcement learning and AI-based perception approaches. Currently, deep reinforcement learning is training agents to discover new routing strategies that optimize yield, equipment effectiveness, cycle time, and queue-time compliance – including joint front and back-end-of-line coordination for advanced packaging. AI-based perception is also on its way to replacing manual, pre-shipment inspection checklists, demonstrating inspection time reduction by as much as 78%. To enable these improvements, presenters suggested private 5G as the foundational connectivity infrastructure. Currently, private 5G is helping eliminate dead zones and bandwidth issues that are preventing real-time machine data and connected robotics from reaching their full potential.Based on these presentations, the prevailing formula is to integrate intelligence at every level. This includes precise in-situ sensing to eliminate manual setup and measurement, edge AI models that act on data immediately, platforms that coordinate across tools without humans, and lastly, a reliable connectivity infrastructure.Session 4 - Predictive Maintenance at the Edge: From Vibration to VisionSemiconductor fabs have long operated in a state of crisis management. Fab managers spend between 40% and 70% of their time firefighting unexpected equipment failures, rather than executing planned maintenance strategies. Unplanned downtime in semiconductor manufacturing can cost up to $1 million per hour, yet the maintenance industry has been slow to move beyond reactive repairs. Fab managers need faster ways to determine issues and act on that knowledge before wafers are lost. Session 4 outlined a framework for how this transformation will happen. At the foundation, smarter sensors (vibration, acoustic, thermal, spectral, and vision) are generating the high-fidelity, multi-modal data streams that make predictive models possible. In addition, "ultra edge" AI accelerators are enabling machine learning inference to happen directly inside MEMS sensors and on-device hardware without cloud dependency. Fabs require low-latency, data-sovereign, real-time decisions that the cloud is unable to support, and the path forward requires an integrated chain of sensing, edge inference, health scoring, and maintenance scheduling. This session also made the case that irrelevant correlations and confounding variables make purely statistical AI unreliable for root cause analysis, and that causal AI models are required to give fabs actionable information. It concluded that cybersecurity concerns, soaring cloud infrastructure costs (datacenter GPU prices reaching $25,000–$50,000 each in 2025–2026), and latency requirements have made distributed, machine-local intelligence the only viable path to achieving autonomous fabs. SummaryThis workshop highlighted how edge AI, smart sensors, and advanced connectivity are transforming semiconductor manufacturing by enabling real-time process control, faster defect detection, and more autonomous operations. Across sessions, experts emphasized that integrating AI directly at the source of data is essential for improving yield, reducing downtime, and building scalable, resilient “smart fabs.”Learn more by registering for this workshop on demand, or view the recap videos on LinkedIn. Day 1 recap Day 2 recap The SEMI Manufacturing Coalitions include Smart Manufacturing, Fab Owners Alliance (FOA), MEMS and Sensors Industry Group (MSIG), Advanced Packaging Heterogeneous Integration (APHI) and Semiconductor Components, Instruments, and Subsystems (SCIS).Anshu Bahadur leads the Smart Manufacturing Initiative, Karim Somani leads the Fab Owners Alliance (FOA), and Paul Carey leads the MEMS and Sensors Industry Group (MSIG), all of which are part of the Technology Coalitions at SEMI.

Today’s post is the last of four Q A-style feature posts based on presentations during SEMICON West 2025’s “The Convergence of Semiconductor Manufacturing and Design” organized by the ESD Alliance (ESDA).Bob Smith interviewed Joe Kwan, Director of Product Management from Siemens EDA, about his presentation, “3D Design Brings Multi-physics Requirements While Manufacturing Yield Improvements Require Digital Twin Modeling and Ingesting Design Data.” They covered a range of topics from partner collaboration and integrated design flows to digital twins, AI and more.Smith: How does Siemens EDA define collaboration between design and manufacturing? What does that look like?Kwan: Manufacturers and designers have been cooperating for a long time. The most familiar example is the design rule check (DRC) rule deck provided by the foundry to the design team. It enforces designers to adhere to the layout rules that must be followed for a design to be manufacturable. What’s different now are new problems arising from the latest advances in technologies. Close collaboration is needed between the design team and foundry to identify and share data necessary for a successful final product. Foundries are challenged to encapsulate information that provides design teams with critical information for success without divulging proprietary data.Smith: Can you elaborate with a few examples of what technologies you are referring to that are driving these new collaborations?Kwan: Sure. A great example is the industry’s move from monolithic single chip solutions to chiplet-based solutions that require 2.5D, 3DICs, heterogeneous integration and the like. These approaches require multi-physics simulations to verify physical phenomena in ways that were not necessary when previously focusing on just a single chip design. Thermal, electrical and stress are not independent variables anymore.Design teams need to understand how these effects come in to play with functionality, performance and other design specifications. Most important, they need to be aware of factors that could cause the chip or system to fail. To do this, close collaboration between all parties involved (design team, foundry and packaging) is required so designers know what to look for in their analyses and what to avoid. It adds a whole new layer of complexity necessary for getting to the finish line.Smith: I imagine some scenarios that fit into what you are talking about. For example, if the design includes stacked die, the team will need to be concerned about heat distribution and potential hot spots in the stack. Kwan: That is a good example. Heating problems cannot be overlooked. How does the heat escape from the stack? What is the thermal profile across the stack from the die on the top all the way through to the bottom of the stack. Is there a sufficient pathway for heat to get out? We can do rough estimates early on to see if putting this die on top of this other one, is it going to work? Or be reliable? Back of the envelope calculations might show that the dies need to be positioned differently or even designed differently. Smith: What can be done to improve design success?Kwan: This is where collaboration comes in. The product owner should establish a cross-domain team of experts from chip design, package engineering and process engineering. The product spec and design decision trade-offs must be evaluated against impact to all domains.EDA also plays a critical role. EDA is the link between designers, packaging and manufacturing. We hear and capture concerns from designers and package engineers. We prototype solutions, collaborating with packaging and IC manufacturers to encapsulate requirements for successful production.Smith: At SEMICON West, we also talked about how design data can help foundries during the manufacturing flow.Kwan: Yes, going back to our discussion at SEMICON West, I spoke about that important topic, which is embodying design data into the manufacturing platform in the context of a digital twin for virtual metrology.In an ideal world, we would measure everything. If we could do that, we would have all the data needed to make perfect manufacturing decisions. But it would be extremely expensive. What we can do instead is apply AI virtual metrology. We collect the usual sparse metrology and then combine design data to train a predictive engine. The result is the ability to accurately predict where metrology was not collected.With traditional process-of-record, foundries run a qualification wafer every 10 or so wafers. That’s very expensive. With virtual metrology, we can predict when drift becomes significant enough to blow up a wafer and you can intervene to restore individual nominal tool performance.Smith: Engineers are writing their own agents to automate parts of the design flow such as analyzing the outputs of simulations.Kwan: We see a lot of interest in AI and Agentic AI. There is a lot of potential to improve engineering productivity. But as we race to develop Agentic AI flows, we must also approach this in a rigorous manner that cross-checks to ensure accurate and robust results.About Joe Kwan Joe Kwan is the Product Director for Calibre AI/ML Fab Solutions at Siemens EDA. He has more than 30 years of experience in the EDA semiconductor industry. He previously worked at VLSI Technology Inc, COMPASS Design Automation, Silicon Access Networks and Virtual Silicon. Kwan received a Master of Science degree in Electrical Engineering from Stanford University and a Bachelor of Science degree in Computer Science from the University of California, Berkeley. Robert (Bob) Smith is an independent consultant who has been involved directly in multiple roles in the EDA industry over the past 38 years. His career experience spans analog engineering, marketing, sales, business and strategy development and others including numerous c-suite roles. He holds a Master of Science degree in Electrical Engineering from Stanford University.

As competition within the semiconductor industry continues to intensify, the need for Europe to strengthen its current position within the global supply chain and develop new partnerships are more important than ever. How can Europe forge a unified semiconductor strategy amidst geopolitical tensions, fast‑moving technological change, and ongoing supply‑chain challenges? These dynamics set the stage for the 2026 Industry Strategy Symposium (ISS) Europe taking place in March in Sopot, Poland for the second consecutive year, bringing together leaders from across the semiconductor ecosystem to assess a rapidly shifting global landscape and define Europe’s path toward greater competitiveness and resilience.The symposium opened with a welcome speech featuring Lech Wałęsa, Nobel Peace Prize Laureate and former leader of the Solidarnosc movement which led Poland’ s resistance to its authoritarian Communist regime in the 1980s. Wałęsa shared a strong message on the importance of collaboration: “Old geopolitical structures and the bipolar world order have reached their limits, and as we transition toward a new global order, it is essential to rebuilding a system better suited to today’s realities”. In this uncertain moment, the Nobel Peace Prize called for peaceful dialogue and collective action to shape a new, more suitable world order rather than relying on conflict.Lech Wałęsa, Nobel Peace Prize LaureateAmidst geopolitical tensions, accelerating technological change, and intensifying global competition, a clear message emerged: semiconductors are now foundational to European economic security and technological leadership. As Laith Altimime, President of SEMI Europe, emphasized, “Semiconductors are the infrastructure of the modern world, and only through close collaboration can we master the challenges ahead and strengthen Europe’s technological leadership.”Laith Altimime, President, SEMI EuropeEurope plays a vital role in this industry, with global revenues expected to reach $2 trillion by 2035. As Altimime noted, “Europe has strong foundations, leading in manufacturing equipment and innovation. We must maintain this leadership while reducing dependencies.”A central theme throughout the symposium was how Europe can build on its leadership positions while strengthening its role across the value chain. As Leonard Hobbs, Director of Government Affairs at Intel Ireland, said, “No region controls the entire supply chain. Europe has to figure out how to differentiate itself within the various parts of the supply chain.” Marc Hijink, author of the book Focus – The ASML Way highlighted Europe’s deep supplier ecosystem, and explained that “more than 80% of the value in the products that ASML makes comes from suppliers who are mostly based in Europe.” Marc Hijink, Author of Focus – The ASML WayAt the same time, significant investments are reshaping Europe’s manufacturing footprint. Joerg Recklies, Executive Vice President Frontend at Infineon, drew the audience’s attention to Infineon’s upcoming Smart Power fab opening in summer 2026 “six months ahead of schedule.” Recklies added, “The new ESMC facility in Dresden is expected to produce 40,000 300mm wafers per month, and will provide the first FinFET capability in Europe.” Joerg Recklies, Executive Vice President Frontend, Infineon TechnologiesLooking at opportunities in advanced semiconductors, Cesc Guim, CEO of Open Chip, said, “25 years ago, the only way to learn how to do advanced chip design was in one of the large US companies. That’s no longer the case. Europe now has the capabilities, supported by RISC-V and a full supply chain backed by the wealth of hardware and software engineering talent in regions such as Pomerania.” Left to Right: Mikołaj Trunin, Deputy Director, Invest in Pomerania and Cesc Guim, CEO, Open ChipTo reinforce the sense of opportunity in a changing world, futurist Christian Kromme gave a whirlwind tour through the revolutions to come in technology and society. He described how each wave of technological change, from the internet to AI to autonomous machines, is arriving faster than the one before. “The internet wave commoditized media and knowledge. In the AI wave, we will see the same value compression, but this time squeezing out human skills such as problem-solving and system design,” said Kromme.Kromme urged delegates to “shift from hard skills to heart skills: imagination, empathy, curiosity and integrity, this is where the value of humans lies, because machines cannot do these things.”Christian Kromme, FuturistTrade tensions and international conflictGeopolitics and supply chain dynamics were central to the discussions. Martin Zech, Senior Director at FTI Consulting, described how the US’s approach to the semiconductor industry had shifted from incentives to restrictions. Zech warned that “a new section 301 investigation into the European semiconductor industry could lead to new tariffs.” Johan Rauer, Partner at McKinsey, added that the threat extends beyond tariffs. “Regions will apply a range of measures, including export controls and IP protection.”Martin Zech, Senior Director, FTI ConsultingJohan Rauer, Partner, McKinsey CompanyChristopher Frieling, Director of Advocacy and Public Policy at SEMI Europe, outlined the EU’s response, including its evolving economic security framework and the concept of “trusted chips,” reflecting a preference for products with strong European involvement.Christopher Frieling, Director of Advocacy and Public Policy, SEMI EuropeThe question of technological leadership was addressed by Carlos Pardo, CEO of KD, who stated, “If Europe wants a relevant position in semiconductors, it needs to invest more.” He added that even in automotive semiconductors, European players hold relatively limited shares. Carlos Pardo, CEO, KDProviding another perspective, Dr. Rafał Bugyi, CEO of TRUMPF Huettinger said, “We don’t need to cover the entire supply chain, but we must be indispensable.” Dr. Rafał Bugyi, CEO, TRUMPF Hüttinger GmbH Co. KGSpeakers also addressed how Europe could adapt to the new reality of supply chain dependency. Benoit Chassagne, End-to-End Supply Chain Manager at Edwards, presented a model of a systems response which his company has implemented to mitigate its exposure to supply chain volatility, while David Forrest, Director of Sustainability and Criticality at Vital Materials, emphasized the role of waste materials recovery, saying that “circularity is an industrial mechanism for supply chain resilience, not an environmental add-on.”Benoit Chassagne, End-to-End Supply Chain Manager, EdwardsDavid Forrest, Director of Sustainability and Criticality, Vital MaterialsCarl van Vugt Luning, Chief Commercial Officer at Resilicon, highlighted the need for greater resilience in polysilicon supply, noting Europe lacks dual sourcing. “Polysilicon is often seen as a commodity, but it is critical. Sovereign chips require a resilient polysilicon supply chain,” said van Vugt Luning.Carl van Vugt Luning, Chief Commercial Officer, ResiliconTurning innovation into commercial revenueIn the session ‘From lab to fab’, speakers examined how Europe can improve its track record in converting innovation into commercial success, for example, by companies such as NVIDIA and Qualcomm.An important part of the EU’s strategy was the creation of technology pilot lines. Jari Kinaret, Executive Director of the Chips Joint Undertaking (Chips JU), told the symposium that the pilot lines are an example of successful collaboration between the state and the private sector. Kinaret said, “The total cost of the NanoIC pilot line (for advanced semiconductor fabrication) is €2.5 billion, but this includes €1 billion of funding from ASML.”Jari Kinaret, Executive Director, Chips Joint Undertaking (Chips JU)The role and value of the pilot lines was the subject of a panel discussion at the symposium. Panelist Anne Van den Bosch, Vice President of Public R D Policies and Programs at imec, said the pilot lines “give the European semiconductor ecosystem faster access to advanced process technology.” Patrick Bressler, Director of Fraunhofer Mikroelektronik, agreed. “Pilot lines are a lab-to-industry scheme to give access to prototype manufacturing for SMEs, start-ups and fabless companies which would not otherwise be able to afford advanced manufacturing,” he said.Moderating the discussion, Laith Altimime asked, “How do we ensure that the products which emerge from innovations developed thanks to the pilot lines get manufactured in Europe? Are boutique fabs the answer?” Kevin Williams, Deputy Director of the PIXEurope pilot line, responded: “There are certainly opportunities in building new types of chips and new types of fabs. We have the know-how in the pilot lines, and the equipment for them is made in Europe.” Bruno Paing, Vice President Europe at CEA-Léti, added, “We need to aim for indispensability, replicating what we have with ASML in the EUV field. For instance, the world needs better memories and better interconnects. There are many opportunities in AI. It is not just about the GPU.”Left to Right: Moderator, Laith Altimime, President, SEMI Europe; Panelists: Anne Van den Bosch, Vice President of Public R D Policies and Programs, imec; Bruno Paing, Vice President Europe, CEA-Léti; Patrick Bressler, Director, Fraunhofer Mikroelektronik; Kevin Williams, Deputy Director, PIXEurope.The symposium also highlighted examples of European innovation from two startups developing new technologies. Antonio Mesquida Küsters, Strategic Advisor to Euclyd, presented a processor system combining 16,384 cores with ultra-high bandwidth memory using advanced 2.5D and 3D packaging, offering an alternative to GPUs for AI inference. As he said, “We want to break the hyperscaler/cloud model of AI to build sovereign AI capability for Europe by 2030.”Antonio Mesquida Küsters, Strategic Advisor, EuclydJekaterina Viktorova, Founder and CEO of Syenta, introduced additive manufacturing technology enabling denser interconnects for advanced AI systems, noting, “Our roadmap is set to produce a 20x increase in bandwidth over the next 10 years.”Jekaterina Viktorova, Founder and CEO, SyentaNew strategies for competitiveness in semiconductor manufacturingIf these types of innovative products are to be manufactured in Europe, the region’s fab operations will need to combat the growing competition from China and elsewhere. Giovanni Notarnicola, Partner at Porsche Consulting, said, “Our position in Europe is under attack. The next threat is not from a new product, but from how chips are designed and produced.”Giovanni Notarnicola, Partner, Porsche ConsultingThomas Altenmüller, Vice President of Manufacturing Analytics at Infineon, highlighted the role of automation: “We get more automation in the transition from 8” to 12” wafers, which gives us an advantage in Europe because of our higher labor cost compared to China. But to compete, we still need more AI smart workflows to increase the automation.” Carina Lainer, Principal at Roland Berger, added, “Today we optimize operations with tools built for a human-centric process, which has reached its limit. We can instead use digitalization and AI to fundamentally change the way that semiconductor innovation takes place.”Thomas Altenmüller, Vice President of Manufacturing Analytics, InfineonLeft to Right: Carina Lainer, Principal, and Thomas Kirschstein, Partner, Roland BergerOded Tal, CEO of MAX Group, cautioned that the barrier to increased implementation of automation was not technical but social. “Humans can be very flexible, but leadership is crucial. “You have to give training and clear instructions. It’s about structure, making people’s roles and responsibilities crystal-clear,” he said.Oded Tal, CEO, MAX GroupThe symposium closed with a panel discussion about the implementation of AI and automation in the fab. Moderator Cassandra Melvin, Senior Director of Business Development and Operations at SEMI Europe, pointed out that “intelligence is moving beyond the tool to the control room, a development which is powered by AI.” The panelists were quick to acknowledge the radical impact that AI is having on fab operations. Dirk Drescher, Plant Manager at Bosch Semiconductor, said, “We built the Bosch fab in Dresden around a standardized data architecture, which is what enables us to implement AI. That is a contrast to a 20 year old fab, which can only see a patchwork of different data systems.”Thomas Richter, Senior Vice President and Managing Director at Infineon, added, “digitalization is about much more than just AI. We have had great success in getting rid of boring, routine tasks through digitalization. This makes a huge difference, and helps our fabs to stay competitive.”The panel also debated the potential impact of humanoid robots on the scale and impact of automation. Richter said, “In our fabs, I can see rooms in which it has never been possible to automate before, but humanoid robots give me hope that we can automate more in future.”Matthias Bonkass, Vice President of Advanced Manufacturing Engineering at GlobalFoundries, agreed. “By 2035, we will see collaboration between humans and humanoids. This wave is coming!” Going even further, Dirk Drescher looked forward to an era of total automation. He said, “We will see a lights-out fab by 2035. This is definitely a tailwind for the European semiconductor industry, making it faster, reducing cost, and giving us more opportunity to build semiconductors in Europe.”Thomas Morgenstern, Executive Vice President of Manufacturing at STMicroelectronics, concluded, “We must not let culture be a barrier to AI. Technical strategies to implement AI are all very well, but you need people to buy in. Morgenstern added, “The name of the game is productivity. The most advanced fabs have to be dark, with remote operating centers somewhere in the world, running clusters of fabs. I am extremely confident that by 2035, if not before, the first dark fab will be in operation.”Left to Right: Moderator, Cassandra Melvin, Senior Director of Business Development and Operations, SEMI Europe; Panelists, Dirk Drescher, Plant Manager, Bosch Semiconductor; Matthias Bonkass, Vice President of Advanced Manufacturing Engineering, GlobalFoundries; Thomas Morgenstern, Executive Vice President of Manufacturing, STMicroelectronics; Thomas Richter, Senior Vice President and Managing Director, Infineon.During the event, SEMI Europe announced recipients of the SEMI European Award and Special Service Award for 2025. Dr Peter O’Brien, Head of Research in Photonics Packaging and Systems Integration at Tyndall National Institute, was honored with the SEMI European Award and, Eric Beyne, Senior Fellow at imec, with the Special Service Award. Peter O’Brien, Head of Research in Photonics Packaging and Systems Integration, Tyndall National InstituteAnne Van den Bosch, Vice President Public R D Policies and Programs, imec receiving the award on behalf of Eric Beyne, Senior Fellow, imecOn behalf of SEMI, the SEMI Europe team and ISS Europe committee, we would like to thank all speakers, sponsors, and attendees for making the event a great success. ISS Europe 2027 will take place in Dresden, Germany from March 8-10.Serena Brischetto is Director, Marketing and Digital Engagement at SEMI Europe.