Automakers are currently evaluating prototypes of Viper from AdaSky, a Far Infrared (FIR) thermal camera that embeds custom silicon co-designed with and manufactured by ST in 28nm FD-SOI. The complete sensing solution aims to enable autonomous vehicles to see and understand the roads and their surroundings in any condition. “With the help of ST, we have created the first high-resolution thermal camera for autonomous vehicles with minimal size, weight, and power consumption--and no moving parts. ST’s access to, and expertise in, ultra-low-power design, IP that is fully qualified for automotive applications, and 28nm FD-SOI technology have been vital to meeting the severe power constraints that would challenge our sensors’ performance,” said Amotz Kats, Vice President Hardware, AdaSky. “We’re in a position to deliver a breakthrough solution to revolutionize and disrupt the autonomous vehicle market because of ST’s mastery of automotive qualification and its strong manufacturing supply chain, which grants reliability, long-term support, and business continuity to car makers throughout the whole life of their production.” Passive infrared vision, like that in AdaSky’s Viper, when used in a fusion solution, can help close the gaps to provide accurate sight and perception without fail in dynamic lighting conditions, in direct sunlight, in the face of oncoming headlights, and in harsh weather. The new camera uses an FIR micro-bolometer sensor to detect the temperature of an object. In an ADAS solution, Viper uses proprietary algorithms based on Convolutional Neural Networks to classify obstacles and show them in a cockpit display to give the driver an early warning. This warning comes several seconds earlier than it would when using a conventional sensor in the visible wavelength and is even faster than what is possible with the human eye. The two companies say that the Far-Infrared thermal camera extends ADAS sensor fusion capability with a new layer of information, helping pave the way to fully-autonomous driving in any condition. Prototypes are now under evaluation by carmakers with initial production targeted for 2020. (Read the full press release here.)

SEMI and 106 other associations today joined forces to express deep concern to congressional leaders about the Trump Administration’s decision to use tariffs to address China’s unfair trade practices. In a letter from the collective to House Ways and Means Committee Chairman Kevin Brady and Ranking Member Richard Neal ahead of today’s hearing on "Effects of Tariff Increases on the U.S. Economy and Jobs," we expressed our strong support to better protect valuable intellectual property, the crown jewel of our industry.However, we worry that these tariffs will hurt companies in the semiconductor supply chain, introduce significant uncertainty, impose greater costs, open companies to retaliatory tariffs, and ultimately do nothing to address our concerns regarding China’s trade practices. We strongly encourage Congress to work together and with the Trump administration to jointly develop and execute a plan that will address the longstanding problems with China. As part of the SEMI Washington Forum (April 17-18), SEMI staff and senior executives from across the industry will raise this and other issues with policymakers in Washington, DC. SEMI will continue to engage as trade tensions continue.

GlobalFoundries' new ecosystem partner program, called RFwave™, aims to simplify RF design and help customers reduce time-to-market for a new era of wireless devices and networks (read the full press release here). The program aims to give designers a low-risk, cost-effective path to highly optimized solutions that leverage GF's platforms including RF on FD-SOI and RF-SOI. The target is wireless applications such as IoT across various wireless connectivity and cellular standards, standalone or transceiver integrated 5G front end modules, mmWave backhaul, automotive radar, small cell and fixed wireless and satellite broadband. As such, the RFwave™ partner program provides GF customers with IP design elements, EDA tools, design consultation and services and OSAT product packaging and test solutions. These products and services are validated, and comprise a plug-and-play catalog of design solutions. With this level of integration, GF customers can create high-performance designs while minimizing development costs. Bami Bastani, senior vice president of GF’S RF Business Unit, says, “As a leader in RF, GF’s RFwave program takes industry collaboration to a new level, enabling our customers to build differentiated, highly integrated RF-tailored solutions that are designed to accelerate the next wave of technology.” Initial members of the RFwave Partner Program are: asicNorth, Cadence, CoreHW, CWS, Keysight Technologies, Spectral Design, and WEASIC.

Worried that you’re underhydrated after a heart-pounding run or bike ride? SEMI’s Nano-Bio Manufacturing Consortium (NBMC) has you covered – with a patch. A few years after the group undertook the sweaty task of creating a non-invasive health monitor, the patch that tracks electrolyte levels recently ended up stuck to the skin of U.S. Air Force volunteers.“During extra workout sessions at the Air Force Research Laboratory in Ohio, the volunteers wore on their backs adhesive patches that collected their perspiration," according to GE Reports. "Sensors in the patches were able to detect the specific levels of electrolytes in the sweat the volunteers released. That data was transmitted wirelessly to a laptop computer app where researchers could analyze it in real time.” Read more about the project in the GE Reports blog.The project came together when NBMC, a diverse group of companies, universities and organizations, brought their enthusiasm and interdisciplinary know-how across nanotechnology, biotechnology, advanced (additive) manufacturing, and flexible electronics to tackle the challenge of underhydration and dehydration. The idea was to develop a device that delivers reliable, wireless, actionable human performance data in a non-invasive way.Congratulations to GE Global Research, and the partners from the Air Force Research Laboratory, University of Connecticut, University of Massachusetts-Amherst, American Semiconductor Inc., University of Arizona, UES, Dublin City University and NBMC on these impressive strides in the field of health monitoring!Watch this video to see the patch in action! (https://www.facebook.com/GE/videos/1667584156643205/)Visit www.nbmc.org for more information.

Sales revenues for fluid management subsystems grew 28 percent in 2017 to $1.28 billion, breaking the $1 billion mark for the first time. Fluid management subsystems have now seen five years of consecutive growth, and 2018 is expected to extend the growth streak to six years for the segment.Fluid management subsystems control the delivery of process gases and chemicals onto the wafer during processing and may be located either on-tool or near the tool. This segment can be further divided into two main categories – gas delivery and liquid delivery subsystems. Gas delivery subsystems, such as mass flow controllers (MFCs), deliver gases or speciality chemicals to a vacuum process chamber, and liquid delivery subsystems typically deliver liquid chemicals to a wet processing module. Demand for gas and liquid delivery subsystems is roughly 54 percent and 46 percent respectively – a ratio that has not changed significantly over the past few years.Although fluid management subsystems account for approximately 10 percent of expenditures on all critical subsystems used on semiconductor manufacturing equipment, growth of other critical subsystems such as vacuum processing subsystems has been sluggish.Mass flow controllers (MFCs), however, are showing strong growth potential and are set to buck their historical slow growth trend as the industry transitions into sub 10 nm processing. At the leading edge, processes are becoming more vacuum intensive and the importance (and difficulty) of accurately controlling chemical delivery for deposition onto the wafer is increasing. Process operating windows are getting tighter and the specification ranges demanded by chipmakers are shrinking, posing challenges for existing MFC technology. The upshot is that new MFC solutions and technologies are needed to enable transitions to smaller nodes, providing an opportunity for growth in this segment.The fluid management subsystems market is currently dominated by Japanese- and U.S.-based vendors. Horiba is the largest player, accounting for 30 percent of total fluid management sales, and the rest of the market is extremely fragmented, with a raft of companies competing in this space.Given the large size and fragmentation of this segment, interest in these products in the coming year is sure to intensify as the race to find lucrative solutions to enable sub 10 nm processing heats up.For more information about VLSI Research and Critical Subsystems, visit www.vlsiresearch.com.

Although many months past due, Congress on March 23 finalized the federal spending for the remainder of fiscal year (FY) 2018, only hours before a what would have been the third government shutdown of the year. Congressional spending has been allocated in fits and starts since the end of FY 2017 last September, with patchwork deals keeping things running amid pervasive uncertainty. While this clearly isn’t an ideal way to fund the federal government, the end result will make many in the business of research and development pleased with the addition of more resources for science and innovation.There was grave concern over the future of federal spending with the release of the president’s FY 2018 budget, which would have cut the National Science Foundation (NSF) budget by 11 percent and National Institutes of Standards Technology (NIST) spending by 30 percent. Relief came with early drafts from Congress that whittled those cuts down to between 2-9 percent. But the real boost was a February bipartisan Congressional agreement that lifted self-imposed spending caps and introduced a generous dose of non-defense discretionary spending, increasing NSF spending 3.9 percent over the previous year and the NIST budget an astounding 25.9 percent over FY 2017 levels.SEMI applauds this much-needed support for basic research and development (R D) at these agencies after their budgets were cut or flat-funded for multiple cycles. It is well understood that federal R D funding is critical to U.S. competitiveness and future economic prosperity. With the stakes that high, full funding of R D programs at the NSF and NIST should be a bipartisan national priority backed by a strong and united community of stakeholders and advocates in the business, professional, research, and education communities.With the work for FY 2018 completed, Congress will now turn to FY 2019 spending – already behind schedule due to the belated completion of the previous year’s budget. With 2018 an election year, Congress will likely begin work on the FY 2019 budget in short order, but probably won’t complete its work prior to the November elections. SEMI will continue to work with lawmakers to support the R D budgets at the agencies and their important basic science research. If you’d like to know how you can be more involved with SEMI’s public policy work, please contact Jamie Girard, Sr. Director, Public Policy at [email protected].

Following the immense success of last year's FD-SOI training day in Silicon Valley, the SOI Consortium has another one planned for the end of April this year. If you want to start learning how to leverage FD-SOI in your chip designs, this is a great place to start. Click here for information on how to sign up. ST Fellow Dr. Andreia Cathelin has put together another great line-up. World renowned professors and experts from industry will deliver a series of four training sections of 1.5 hours each, focused on energy efficient and low-power, low-voltage design techniques for analog, RF, high-speed, mmW and mixed-signal design. You'll learn about design techniques that take full advantage of the unique features of FD-SOI, including body biasing capabilities that further enhance the excellent analog/RF performances of these devices. Each section of this training day will take you through concrete design examples that illustrate new implementation techniques enabled by FD-SOI technologies at the 28nm and 22nm nodes – and beyond. The design examples will cover basic building blocks through SoC implementations. A global Q A session will close the day. Here's a little more info on how the day will unfold. Click on the slides to see them in full screen. Morning sessionsFDSOI-specific design techniques for analog, RF and mmW applications - Andreia Cathelin, Fellow, STMicroelectronics [caption id="attachment_11714" align="alignleft" width="300"] Quick preview from Andreia Cathelin's FD-SOI training session (Courtesy: STMicroelectronics, SOI Consortium)[/caption] Andreia Cathelin is ST's key design scientist for all advanced CMOS technologies, and is arguably the world's leading expert on leveraging FD-SOI in high-performance, low-power RF/AMS SoCs. Her course will first present a very short overview of the major analog and RF technology features of 28nm FDSOI technology. Then the focus moves to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits. She'll give design examples such as analog low-pass filters, inverter-based analog amplifiers and 30GHz and 60GHz Power Amplifiers, as well as mmW oscillators. There will be particular focus on the advantages of body biasing and special design techniques offering state-of-the-art performance. Circuit Design Techniques in 22nm FD-SOI for 5G 28GHz Applications - Frank Zhang, Principal Member of Technical Staff, GlobalFoundries [caption id="attachment_11716" align="alignright" width="300"] Quick preview from Frank Zhang's FD-SOI training session (Courtesy: GlobalFoundries, SOI Consortium)[/caption] Frank Zhang has designed chips using GF's 22nm FD-SOI (22FDX) process for WLAN, 5G cellular and automotive radar applications. His course will focus on how to take advantages of FD-SOI’s high-frequency performance at relatively low-current density to design high performance RF/mmWave circuits. Examples circuits include a 28GHz LNA, a 28GHz PA and an RF switch for 5G applications. The FD-SOI advantages such as low capacitance, high breakdown voltage and high-output impedance will be exploited in these design examples. This course will also discuss how to extend these techniques to applications at higher frequencies and/or higher current densities that are subject to extreme temperatures and EM requirements. Afternoon sessionsEnergy-Efficient Design in FDSOI - Bora Nikolic, Professor, UC Berkeley [caption id="attachment_11715" align="alignleft" width="300"] Quick preview from Bora Nikolić's FD-SOI training session (Courtesy: UC Berkeley, SOI Consortium)[/caption] Borivoje (“Bora”) Nikolić is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI.) If you missed it, his team's RISC-V chip was cited as one of Dr. Cathelin's “Outstanding 28nm FD-SOI Chips Taped Out Through CMP” – read more about that here. His talk at the training day will present options for energy-efficient mixed-signal and digital design in FD-SOI technologies. He'll explain how to generate body bias and use it to improve efficiency, with examples in RF and baseband building blocks, temperature sensors, data converters and voltage regulators. The techniques will be presented in the context of UC Berkeley's latest RISC-V-based SoC, designed to operate in a very wide voltage range using 28nm FD-SOI. mm-Wave and Fiber-Optics Design in FD-SOI CMOS Technologies - Sorin Voinigescu, Professor, University of Toronto [caption id="attachment_11713" align="alignright" width="300"] Quick preview from Sorin Voinigescu's FD-SOI training session (Courtesy: U. Toronto, SOI Consortium)[/caption] Sorin Voinigescu is a world renowned expert on millimeter-wave and 100+Gb/s ICs and atomic-scale semiconductor device technologies. His lecture will cover the main features of FD-SOI CMOS technology and how to efficiently use its unique features and suitable circuit topologies for mm-wave and broadband SoCs. He'll begin with an overview of the impact of the back-gate bias and temperature on the measured I-V, transconductance, fT, and fMAX characteristics. Then he'll compare the maximum available gain, MAG, of FDSOI MOSFETs with those of planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz. Next, he'll provide biasing, sizing and step-by-step design examples for VCO, doubler, switches, PA, large swing optical modulator drivers and quasi-CML circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of 20nm and 12nm FD-SOI CMOS technologies. Sign Up Now!With over 100 attendees filling every chair in the auditorium, last year's training day was sold out. Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.” 2018 will be no different – except that it's sure to sell out even faster. Please note, though, that this is not a free event, so only the attendees will get copies of the slide decks. Here's key info you need to sign up. See you there!What: SOI Consortium's FD-SOI Training DayWhen: 27 April 2018, 7:30am – 5pm.Where: Crowne Plaza San Jose, Milpitas CA (parking is free)Registration fee: US $485.00 (includes training book, breakfast, box lunch and refreshments during breaks)How to sign up: Click here to go directly to the registration site.

Co-author: Sungho Yoon, Senior Market Research Analyst at SEMIChip makers continue to struggle to secure more silicon wafers to meet market demand as production capacity has reportedly fallen short of their needs, particularly in the 300mm wafer segment – a trend that has led to record-low DOI(1) (Days of Inventory) levels since the second half of 2017.The DOI level has shown no significant improvement since August 2017, as depicted in figure 1(2). Unlike the inventory rebound in 2007, the current inventory trough shows no signs of significant recovery soon.Figure 1 - Silicon Wafers Days of InventorySource: Processed data extracted from data reported by METI (Ministry of Economy, Trade, and Industry) Japan.The boom-and-bust cycles typical of the semiconductor industry are driven by large capital spending increases, followed by cutbacks. The industry has seen a number of these cycles since 2000. However, before 2017, the particularly low level of wafer inventory we now see had never lasted longer than six months.There are three major reasons for the persistently low levels.First, on the silicon wafer demand side, fab equipment investments reached a record high in 2017, driven by large-scale memory fab investments by Samsung and SK Hynix in Korea that accounted for 32 percent of global total investments. Additionally, Korea’s year-over-year (YoY) equipment billing growth rate saw a sharp increase of 135 percent in 2017, as shown in figure 2.Figure 2 - Equipment Billings in KoreaSource: SEMI/SEAJ WWSEMSWhat’s more, the 12-month moving average of equipment billings in China has trended upward since the Made in China 2025 plan was released in 2015, a marked difference from past equipment investment trends in China that followed typical up-and-down industry cycles, as represented in figure 3.Figure 3 - Equipment Billings in ChinaSource: SEMI/SEAJ WWSEMSKorea’s soaring investments in memory and China’s massive, ongoing government investments to beef up fab production are key drivers of the stubbornly low wafer inventory levels throughout 2017 and, now, into 2018.The second reason is the time lag between investments by silicon wafer manufacturers and chip makers. Spikes in wafer processing equipment spending have preceded tops in wafer manufacturing equipment investments since the 2008 financial crisis, as shown in figure 4. Prior to 2008, silicon wafer manufacturing investments preceded or tracked chip manufacturing investments, minimizing periods of tight wafer suppler.Silicon wafer inventory surged during the financial crisis, triggering a steep drop in silicon wafer pricing. The fallout is that wafer manufactures have been hesitant to expand manufacturing facilities without first securing chip makers’ commitments to new fab investments or capacity expansions of their existing fabs. Finally, wafer supply failed to keep pace with demand in 2017, and inventory levels continue to lag chip makers’ expectations.Figure 4 - YoY growth rate of wafer manufacturing and wafer processing equipment Source: SEMI/SEAJ WWSEMSThe third reason is technical: Memory demand is growing across all end applications, but rising technical challenges that reduce yield and output tend to restrict memory bit supply growth. The upshot is that, in the absence of technology breakthroughs, memory makers need more cleanroom space in order to fulfill market demand for memory bits. The investments needed to build additional cleanroom space further accelerates wafer demand.When will the industry wafer inventory conundrum improve? That depends on how fast memory device makers expand capacity despite tenaciously low wafer inventories and how, in turn, wafer manufacturers cope with the current acceleration of fab investments by device makers through expanding wafer manufacturing capacity.Low wafer inventory levels could potentially hamper growth for semiconductor equipment market as it would be difficult for device makers to expand fab capacity without securing stable wafer supply chain in advance.(1) Days in inventory is calculated as the number of days in the period divided by the inventory turnover(2) Value of estimated relative DOI was removed in the left axis and DOI data was calculated based on 3MMA (3-month moving average). Dan Tracy is senior director and Sungho Yoon is senior research analyst in Industry Research and Statistics at SEMI.

Fueled by heavy government investment, IC packaging and testing in China generated $29 billion in revenue in 2017, making China the world’s largest consumer of packaging equipment and materials, according to SEMI’s recent China Semiconductor Packaging Industry Outlook report. The report, based on research conducted between July 2017 through the end of January 2018, also revealed that China’s IC packaging and testing industry is more mature than its IC manufacturing and design sectors, though IC packaging and testing revenue growth has slowed in recent years. SEMI surveyed 87 semiconductor packaging- and assembly-related companies for the research report, including key semiconductor packaging manufacturers in China. More than 100 companies compete in China’s packaging and assembly market, including leading multinational companies and emerging domestic players. More than half of China’s packaging companies are located in the Yangzi delta region, while midwestern China has emerged as a hotbed for packaging plants.Additional report highlights: Compared to other world regions, China’s investments in IC packaging and testing saw the fastest growth over the past decade, with domestic manufacturers securing strong support from both national and local governments to ramp capacity and technical capabilities. The top three domestic packaging companies – JCET, Huatian, and TFME – all entered the top 10 global OSAT rankings following expansions and acquisitions from 2012 to early 2016. Packaging companies such as SPIL, TFME, NCAP continue to build new plants. As a major manufacturing region for LED products, China has become more prominent within the semiconductor packaging industry. China’s LED product sector grew to $13.4 billion (half of IC packaging) in 2017. In 2017, China accounted for about 26 percent of the global packaging materials market, with China’s packaging materials revenue forecast to exceed $5.2 billion in 2018. In 2017, the China assembly equipment market reached $1.4 billion in revenue, remaining the world’s largest with 37 percent share. In 2017, assembly equipment manufactured in China (including assembly equipment made by foreign-owned companies and JVs) accounted for 17 percent of China’s assembly equipment market. With the fast growth in the semiconductor packaging market, domestic packaging materials suppliers are expanding with the industry and now starting to serve leading international packaging houses. The SEMI report also elucidates the importance of both central and local government support, guidelines and policies on China’s semiconductor industry. The National Fund and local IC funds, created in 2014, and the Made in China 2025 policy provided a second boost to China’s IC industry growth. For packaging and testing enterprises, maintaining strong communications and relations with relevant government bodies and industry associations is essential to securing both political and financial support, in part because China’s semiconductor manufacturers and IC assembly and packaging companies are expected to purchase equipment and materials made in China.To learn more about this new report, click here.

Artificial intelligence (AI) is making headlines everywhere, offering a range of capabilities, including location and motion awareness — determining whether a user is sitting, walking, running or sleeping. Behind the scenes, AI is capturing volumes of data. Makers of smartphones and fitness and sports trackers, along with application developers, are all clamoring for this data because it helps them analyze real-world user behavior in depth. Manufacturers gain a competitive edge by tapping this intelligence: Using it to improve user engagement, they increase the perceived value of their devices, potentially reducing customer churn. How can consumer-product manufacturers tap the built-in capabilities of MEMS inertial sensors — which are already ubiquitous in end-user devices — to make the most of AI? Machine learningProduct manufacturers can easily build an activity classification engine using commonly available smart sensors and open-source software. Activity trackers, for example, use raw data first collected via the MEMS inertial sensors that are already installed in smartphones, wearables and other consumer products.With the building blocks in place, consumer-product manufacturers can apply machine learning techniques to classify and analyze this data. There are several possible approaches, ranging from logistic regression to deep learning neural networks.One well-documented method used for classifying sequences in AI is Support Vector Machines (SVM). Physical activities, whether walking or playing sports, consist of specific sequential repetitive movements that MEMS sensors gather as data. MEMS sensors make good use of this collected data, which can be easily processed into well-structured models that are classifiable with SVMs.Consumer-product manufacturers have gravitated toward the SVM model since it is easy to use, scale and predict. Using an SVM to set up multiple simultaneous experiments for optimizing classification over diverse, complex real-life datasets is far simpler than with other approaches. An SVM also introduces a wide range of size and performance optimization opportunities for the underlying classifier.Cost impacts of processing, storage and transmissionIn practice, recognizing user activity hinges on accurate live classification of AI data. Therefore, the key to optimizing product cost is to balance transmission, storage and processing costs without compromising classification accuracy.This is not as simple as it sounds. Storing and processing AI data in the cloud would leave users with a substantial data bill. A WiFi, Bluetooth or 4G module would drive up device costs and require uninterrupted internet access, which is not always possible.Relegating all AI processing to the main processor would consume significant CPU resources, reducing available processing power. Likewise, storing all AI data on the device would push up storage costs.Resolving the issuesTo resolve these technology conflicts, we need to do four things to marry the capabilities of AI with MEMS sensors.First, decouple feature processing from the execution of the classification engine to a more powerful external processor. This minimizes the size of the feature processor size while eliminating the need for continuous live data transmission.Next, reduce storage and processing demands by deploying only the features required for accurate activity recognition. In one example created by UC Irvine Machine Learning Repository (UCI), when an AI model was trained using a dataset of activities with 561 features, it identified user activity with an accuracy of 91.84 percent. However, using just the 19 most determinative features, the model still achieved an impressive accuracy of 85.38 percent. Notably, pre-processing alone could not identify these determinative features. Only sensor fusion enabled the data reliability required for accurate classification. Third, install low-power MEMS sensors that can incorporate data from multiple sensors (sensor fusion) and enable pre-processing for always-on execution. A low-power or application-specific MEMS sensor hub can slash the number of CPU cycles that the classification engine needs. The onboard software can then directly generate fused sensor outputs at various sensor data rates to support efficient feature processing.Finally, retrain the model with system-supported data that can accurately identify the user’s activities.Additionally, cutting the data capture rate can reduce the computational and transmission resource requirements to a bare minimum. Typically, a 50 Hz sample rate is adequate for everyday human activities. This may soar, however, to 200 Hz for fast-moving sports. Reducing dynamic data rate selection and processing in this way lowers manufacturing costs while making the product lighter and/or more powerful for the consumer.High efficiency in processing AI data is key to fulfilling its potential, driving down costs and delivering the most value to consumers. MEMS sensors, in combination with sensor fusion and software partitioning, are critical to driving this efficiency. Operating at very low power, MEMS sensors simplify application development while accurately analyzing motion sensor data.Combining AI and MEMS sensors into a symbiotic system promises a new world of undreamt-of opportunities for designers and end users.This blog post is based on an original article that first ran in EDN. It appears here with the permission of the publisher.