This year’s Advanced Lithography TechXPOT at SEMICON West will explore the progress on extreme ultra-violet lithography (EUVL) and its economic viability for high-volume manufacturing (HVM), as well as other lithography solutions that can address the march to 5nm and onward to 3nm. Several session speakers offered their insights into the readiness of EUVL for 5nm and how other lithography solutions will enable 3nm. See the full list of speakers and program agenda at http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Diverging viewpoints on EUVL readiness for 5nmMike Lercel, Director of Strategic Marketing at ASMLASML expects its first customer to start volume manufacturing with EUV at the 7nm logic node and the mid-10nm DRAM node in the 2018/2019 timeframe. “EUV will replace the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future,” said Lercel. “For the 5nm logic node, more layers are expected to migrate to EUV.”Three ASML customers have early-access versions of the next-generation TWINSCAN NXT:2000i for the development of advanced logic and DRAM nodes. “This system delivers 2.0nm cross-matched on-product overlay, achieved through several hardware advancements,” noted Lercel. “It is also significant because this mix-and-match use with EUV features a significantly different hardware platform.” TWINSCAN NXT:2000i features a new alignment sensor and improved wafer table flatness, endurance, and clamping mechanism to enhance matching to EUV.ASML has achieved good industrialization progress of its pellicle, with tests confirming that pellicles can withstand 245W source power and an offline power lifetime test indicating 400W capability. Compared to the 7nm logic node, the requirements for EUV masks will become tighter at 5nm, but Lercel noted that ASML sees good progress with the industry infrastructure to support 5nm in areas such as reducing mask blank defects. “We will continue to improve pellicle transmission for enhanced throughput, but there are no fundamental changes in pellicle requirements for 5-3nm logic nodes. We see no infrastructure showstoppers for the introduction of EUVL at the 5nm node.”Stephen Renwick, Director of Imaging Physics at Nikon Research Corporation of AmericaRenwick said that the 7nm logic node is expected to be fabbed mostly using 193i lithography. “EUV will struggle to be ready for 5nm, limited by yield issues caused by stochastic effects in the resist,” said Renwick. “Ready or not, though, it will be used.” Renwick suggests that introducing multiple-patterning with EUV may be needed but would increase costs. “193i lithography will continue to be used with quadruple-patterning and in combination with other techniques – there is no single solution.”Figure 1. Normalized cost/layer vs. lithography method. SOURCE: Nikon Research Corporation of America When choosing between immersion lithography and EUV for different customer segments at 5nm, Renwick noted that the cost depends on the layer. “Some time ago, we calculated that the costs of either 193i triple-patterning or 193i SADP with two cuts were roughly equal to single-patterning with EUV,” explained Renwick (Figure 1). “That agreed with chipmakers' public estimates and meant that the choice of lithography method depended more on the performance tradeoffs involved, such as 193i's better line-edge roughness. At the 5nm node, we are probably faced with quad-patterning from 193i, double-patterning from existing EUV tools, or single-patterning from as-yet undelivered high-numerical aperture (NA) EUV tools.” Renwick believes that the competition between low-NA EUV double-patterning and 193i quad-patterning will be similar to the current situation (i.e., comparison of 193i triple-patterning or 193i SADP with two cuts vs. single-patterning with EUV), but for high-NA EUV tools he believes it's too early to say.Other challenges Renwick sees on the horizon for EUVL at 5nm are stochastic effects in EUV resists. “They cause yield problems on contact arrays and unacceptable line-edge roughness on line/space patterns,” said Renwick. “It's unlikely that these effects will go away without increasing the litho dose, which will further challenge throughput performance.” He also questions whether EUV pellicles, though under development, will be “ready for prime time.”Harry Levinson, Sr. Director of Strategic Lithography Technology and Sr. Fellow at GLOBALFOUNDRIESLevinson said additional fundamental engineering work is needed to ready EUV lithography for 5nm. “Among the top problems are stochastics-induced resist defects, which increase significantly as dimensions shrink below those for 7nm,” explained Levinson (Figure 2). “Higher exposure doses will be required to address these issues related to stochastics at 5nm, which will require higher source output” (than 7nm).Levinson said there will be greater motivation to use EUVL at the 5nm node vs. at 7nm to offset the large number of exposures associated with 193nm immersion multiple-patterning solutions. “The primary application of EUV lithography at 7nm will be for contact, via and cut layers,” Levinson noted. “It will be important to enable EUVL for metal masks at the 5nm node, which increases the need for an ample supply of very low defect EUV mask blanks.” Levinson added that the 7nm node is already stressing defect inspection capabilities, and no actinic defect inspection system is yet available for patterned masks. “This situation becomes more problematic with widespread application of EUVL to metal layers.” Mask development for 5nmChristopher C. Progler, CTO Strategic Planning at PhotronicsProgler said that the basic infrastructure for delivering EUV masks is available, especially for dark field layers and near in nodes. “The interconnected or more open frame patterns will need refinements to the processes and two to three nodes out will need certain new infrastructure,” said Progler. Overall, the main challenges for initial insertion are about creating a cost-effective and rapid-turn EUV mask process, he said. “The industry can certainly deliver EUV masks in some form. It is more a question of doing it efficiently and productively to match the stated value proposition of EUV over other lithographic methods. We don’t want a pick two of ‘cost, cycle time, capability’ sort of mask solution.” More specifically, Progler explained that after the initial EUV mask development for 5nm focused on contacts and block layers, the major push for N5 switched to delivering single-exposure EUV metal patterning as early as possible. “This has opened some new challenges for masks given the resolution, critical pattern density and tight pitch defect requirements of the re-aggregated single-layer metal mask designs,” said Progler. “For example, on the resolution side, we are accelerating the insertion of higher dose photoresists and also driving patterning module improvements in CD control, mask LER and sidewall angle.” Progler added that at N5, the mask 3D structure itself – including the sidewall – will have a greater impact on lithography because it is tied to stochastic error rates on the wafer.“Reliable, wide-area metrology for some of these 2D and 3D mask parameters is currently hard to come by. We may see an evolution of the blank structure at some point in N5, including hard mask options for pattern stability and expect earlier insertion of EUV mask process correction with model-based hot spot detection and rule checking as well. We also hope mask-scanner dedication is not needed, but there are some indications process sensitivity may push us earlier in this direction.” He added that to reduce metal layer defects, more attention needs to be devoted to advanced repair and model-based validation. “We are, unfortunately, still in a situation of blurry vision and high native defect counts alongside possible in situ contamination during mask changes.” Figure 2. Resist stochastics-induced defects. Graph courtesy of Peter DeBisschop, imec; SOURCE: GLOBALFOUNDRIES Progler pointed out that, with the advent at 5nm, metal masks will require some level of actinic blank inspection for yield, increasing the cost of an already expensive mask technology. “So, unless we want to contend with double and triple photomasks’ starts to deliver a single metal layer, it will be very important to tighten the multi-sensor inspection, defect abatement, and repair loops,” said Progler. He does see some clouds forming around high-volume manufacturing pellicles for metal layers. “This remains an open question, mainly for thermal and materials reasons, not to mention cost and cycle time,” Progler said. “We may be pessimistic, but we do not see an HVM pellicle solution converging in the required timeframe, which means leaning even more on a wafer-level inspection in the validation loop.” He believes that streamlining validation will be a differentiator. “I can imagine one losing most of the EUV cycle time benefits by endlessly circling masks around if this is not done well.” How does the industry get to 3nm? ASML plans to ship its first high-NA EUV prototope/pilot systems between 2020 and 2023 to support 3-2nm process development. “System designs are now being finalized and the platform is starting to come to life,” said Lercel. ASML supplier ZEISS is building a high-NA cleanroom for optics production. ASML believes that EUV, high-NA and DUV systems will be used together at the most advanced nodes and is designing to account for this mixed environment. “As chipmakers drive toward smaller geometries in the most advanced nodes like 3nm, they face unprecedented challenges in devices and materials. This will make the process control requirements even more challenging.” ASML is tackling these challenges with its YieldStar metrology platform, e-beam metrology (HMI) and computational lithography solutions that are designed to expand the process window, enhance process control, and improve patterning defect detection. “This ‘Holistic Lithography’ approach will become increasingly important to ensure throughput and yield at the most advanced nodes.”Levinson said that the issues he projects for 5nm will need to be addressed further at 3nm. “The challenges associated with resists at 3nm dimensions are such that it isn’t clear that chemically amplified resists will be capable of meeting requirements,” said Levinson. “If true, we would be seeing the most significant change in resist platforms in a quarter of a century. Potentially cost-reducing technologies such as directed self-assembly (DSA) are always welcome, but EUVL will be the lithographic workhorse through the 3nm node, and likely beyond.”At 3nm, mask makers will confront the realities of higher EUV NA tools. “We will need to implement thinner mask absorbers, new films, and perhaps hard masks,” Progler said. “This puts us in a new materials regime for masks, and history has shown us the mask industry takes a long time to refine processes and tools for new mask materials.” He explained that the small scale of the mask ecosystem and the small number of large suppliers available to address the challenges accounts for this lengthy time frame. Still, looking ahead, Progler noted that Photronics has already done a few studies on the impact of proposed half-field, high NA anamorphic optics on masks. "We uncovered some challenges that need to be addressed, particularly at boundaries and within the overall mask flow,” said Progler. As mask resolution continues to scale down, the industry will need fundamentally higher resolution mask making and inspection processes, requiring next-generation multi-beam mask writing and electron beam inspection, he explained.At 3nm and below, Progler noted that the metrology needs for masks, while not as severe as that for wafers at these nodes, will test the mask equipment infrastructure in ways that could challenge the relatively small mask industry. “Of course, EUV multi-patterning comes into play as well, and with that, the SRAF sizes will drop below 20nm, requiring an asymmetric compensation over a much wider influence area than the OPC people are used to considering.” With EUV multi-patterning, Progler explained that it will be increasingly important to match or pair EUV masks and to consider how 3D effects and stochastics will drive new technology to enable new requirements for high-speed metrology and simulation components. “All the justifiable hand-wringing over EPE with ArF multi-patterning today gets introduced to the EUV scene when masks are ganged together to make a single device layer,” said Progler.Debra Vogler, SEMI

Years of industry consolidation in the critical subsystems market appears to be coming to an end.The top 10 suppliers’ share of the critical subsystems market has stabilised at around 50 percent after many years of industry consolidation. Through a combination of acquisitions and organic growth, this percentage has been increasing steadily from 38 percent at the turn of the millennium. However, in recent years the trend has slowed considerably as medium and smaller sized suppliers are starting to provide stiffer competition for incumbents. Driven by a number of factors, consolidation produces a number of benefits that accrue to the resulting larger suppliers, including the following: Economies of scale Combined research and development budgets Improved access to global markets through strategic regional acquisitions Stronger financial backing that can facilitate any required rapid scale up in production For their part, buyers must rely on a smaller pool of larger suppliers and face these downsides: Less innovation Less flexibility In some cases, dependency on a single supplier for a particular subsystem that can lead to supply chain bottlenecks Until 2014, the balance was clearly in favour of consolidation, but since then the trend has stalled and there is strong evidence that over the next few years the trend may even revert, favouring medium and smaller sized suppliers. The current industry upswing has already allowed these companies, versatile and nimble enough to quickly develop and deliver innovative solutions, to gain market share from overstretched incumbents. What’s more, OEMs and chipmakers, increasingly concerned about having to rely on a single or dominant source for their most critical subsystems, are effectively imposing a spending cap with some large suppliers while collaborating with medium and smaller sized suppliers and encouraging them to step up.The data supporting these observations suggests that the main beneficiaries are companies ranked between 11th and 30th in size, with many of these organizations’ market share growth slightly outpacing that of the top 10 in recent years.For more information about VLSI Research and Critical Subsystems, visit www.vlsiresearch.com. Julian West is a technical and marketing analyst at VLSI Research Europe.

Some really innovative start-ups presented chips they're doing on FD-SOI at the SOI Consortium’s 2018 SOI Symposium in Silicon Valley. We'll cover those here in Part 3 of ASN's coverage, as well as a presentation on China by wafer-maker Simgui and the final panel discussion. BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it. And in the afternoon the foundry partners provided excellent insight into who's designing chips on FD-SOI, and VLSIresearch explained why. You can read that here. Some of the presentations are posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here. Start-upsIneda Systems began as an ADAS start-up, and are now working on developing low-power SoCs for use in consumer and enterprise applications. They're using FD-SOI for their current family of chips. SVP Ramkumar Subramanian emphasized that NRE costs are really important for smaller designs. 22FDX, he said, enabled them to move from 40nm, and ramp to larger volumes. In February, GreenWaves Technologies, a fabless semiconductor startup designing disruptive ultra-low power embedded solutions for image, sound and vibration AI processing in sensing devices, announced its GAP8 IoT application processor. GAP8 evaluation boards can now be ordered. The GAP8 agile power management architecture combined with IOT low duty cycling is a perfect fit for FDSOI processes. CEO Loic Lietar talked about how it would be used in AI applications at the very edge, wherein only the necessary data should be uploaded to the cloud. Also in February, Dream Chips’ announced that its ADAS SoC fabbed in GlobalFoundries’ 22FDX (FD-SOI) technology was posting record power efficiency (you can read more about it in ASN's coverage at the time here.) Dream Chips is Germany’s largest independent Engineering Service Provider. At the symposium, CEO Jens Benndor's talked about their roadmap. [caption id="attachment_11865" align="alignleft" width="300"] (Courtesy: eVaderis, SOI Consortium)[/caption] eVaderis CEO Jean Pascal Bost talked about how data-intensive IoT applications are enabled with FD-SOI and embedded magnetoresistive non-volatile memory (eMRAM) technology. You can get the slides from his talk here. eVaderis has eflash-like and eSRAM-like eMRAM IP that covers most MCU applications. They also have an eMRAM compiler tool and high-value-added IP for 22FDX. They foresee impressive power savings at the system level with body biasing: 25x this year and up to 45x in 2020, so that intelligence can be brought to IoT. In February they announced that they are co-developing an ultra-low power MCU reference design using GF’s eMRAM technology on the 22FDX® platform. And in March eVaderis and Mentor/Siemens announced that eVaderis proprietary Magnetic Tunnel Junction (MTJ) model would be co-optimized with AFS to speed-up simulations and generations of embedded MRAM IPs and compiler products with good accuracy.An 22FDX MCU reference design project is underway, with tape-out in July '18. Reduced Energy Microsystems (REM) CEO William Coven talked about realizing near-threshold computing with 22FDX and low-power memories. REM has two products on 22FDX: their Neuron Vision SoC and 64-bit RISC-V IP cores. 22FDX, he says, has been fantastic. Simgui Jeffrey Wang, the CEO of wafer-maker Simgui looked at why China is promoting its IC industry. (In the SOI ecosystem, Simgui is particularly known for its RF-SOI wafers, which it produces using Soitec's Smart CutTM process.) This was more of an overview talk, not necessarily specific to the SOI ecosystem, but certainly interesting. In terms of worldwide semiconductor sales, he said, about half end up in China. The CICF – aka the Big Fund – is currently running at about $74 billion. Having realized that mergers acquisitions would not solve the problem, they've opened a second round, targeting another $160 billion. China's two biggest innovation success stories are Huawei (with its Kirin processor), and China Rail, which is now a global Fortune 500 company. The CAGR for the China semiconductor industry is 19%, though they need 20% to reach their goals. IC design is a particularly successful area, posting a CAGR of 29%, with two players in China in the top 10 worldwide. Packaging and assembly/test are also very strong. Zing is working on increasing the supply of 300mm silicon wafers, while Simgui is expanding in both 200 and 300mm capex, due to “big demand”, he said. Panel Discussion [caption id="attachment_11866" align="alignleft" width="300"] SOI Symposium Panel Discussion: (left to right): Giorgio Cesana (Co-Director SOI Consortium), Dave Eggleston (VP GF), Tim Saxe (CTO, Quicklogic), Wayne Dai (CEO, Verisilicon), Samir Patel, (CEO Sankalp Semi), Kelvin Low (VP, ARM), Mahesh Tirupattur (EVP, Analog Bits)[/caption] The day wrapped up with an excellent panel discussion moderated by SOI Consortium Executive Co-Director Giorgio Cesana. Here are a few of the observations made by the panelists. QuickLogic CTO Tim Saxe said that FD-SOI made their designs more compact. With FD-SOI for FPGAs, you've got one set of IP, and you can decide at runtime where you're going for low power or high performance. With a lot of power domains, you see the benefits at the system level. GF VP Dave Eggleston said they're seeing early adopters of eMRAM, especially for wearables with RF and low power. ARM VP Kelvin Low said people should do more than just migrate to FD-SOI. If they use back biasing, it can replace the need for big/little cores. Body biasing makes things easier, maintained Verisilicon CEO Wayne Dai. His teams find that with body biasing, you can tape out for “typical” instead of “worst case”. It's not too late for FD-SOI: it's perfect timing for the MCU market, which is still at 40nm, said Sankalp Semi CEO Samir Patel. As designers, they're happy to focus on companies still on the older nodes. The IP ecosystem should be more enthusiastic about FD-SOI, said Analog Bits EVP Mahesh Tirupattur. You've got more potential customers, and your volume runs can be bigger. In his closing remarks, SOI Consortium Executive Co-Director Carlos Mazure reminded the audience of the day's three take-aways: power consumption is driving even systems companies FD-SOI is penetrating fields like MCUs and SoCs where more intelligence is needed China is still a really big opportunity.

Testifying before a U.S. interagency panel weighing trade tariffs against China, Jonathan Davis, global vice president of industry advocacy at SEMI, yesterday called for the removal of more than 100 products from the list of tariffs proposed by the Trump administration, stressing that an escalation of the U.S.-Sino dispute could trigger a full-blown trade war and hasten deep, unintended damage including higher consumer prices, an expanded U.S. trade deficit, and a slowdown in U.S. economic growth.Representing the electronics manufacturing supply chain, Davis threw the industry’s weight behind protections for valuable intellectual property but argued that “if implemented as proposed, these tariffs will potentially cost tens of millions annually in additional taxes and lost revenue owing to reduced exports, threaten thousands of high-paying U.S. jobs, and not solve U.S. concerns with China.” Davis said the undue harm will ultimately undercut the ability of U.S. chipmakers to sell overseas, stifling innovation and curbing U.S. technological leadership.In testimony at the hearing before the government panel that included representatives from the U.S. Trade Representative (USTR), Departments of Treasury, Commerce, State and Defense, and the Council of Economic Advisers, Davis explained that more than 100 lines – products defined for the purpose of setting import duties – of the proposed tariffs would hamstring the semiconductor supply chain. The tariff lines include fundamental components of the semiconductor manufacturing process that are oxygen for the chip industry. As part of his testimony, Davis also submitted comments on the impact of the tariffs.Charles Gray, general counsel at Teradyne, who also testified at the hearing, said the tariffs will threaten growth while penalizing U.S. companies with supply chains that touch China. Gray and Davis were among more than 100 industry leaders who provided more than 3,000 comments in the May 15-17 hearing to evaluate the impact and efficacy of the proposed tariffs.The hearing followed the Trump administration’s heated, longstanding criticism of China for what it considers unfair trade practices, focusing specifically on intellectual property violations. In recent months, the administration has begun implementing trade actions against China that will increase tariffs, restrict cross-border investment, and introduce significant uncertainty for U.S. businesses.The Section 301 investigation that determined China’s forced transfer of technology and intellectual property discriminated against U.S. firms prompted a proposed 25 percent tariff on $50 billion in U.S. imports from China – a punitive measure that would squarely hit the semiconductor manufacturing industry.SEMI continues to educate policymakers on the deep damage tariffs would exact on the long-term health of the semiconductor industry and the critical importance of balanced trade to the future of the semiconductor industry.For more information on trade or how to participate in SEMI’s public policy program, please contact Jay Chittooran, SEMI public policy manager, at [email protected].

Broad Global U.S. Electronic Supply Chain GrowthThe first quarter of this year was very strong globally, with growth across the entire electronics supply chain. Although Chart 1 is based on preliminary data, every electronics sector expanded – with many in double digits. The U.S. dollar-denominated growth estimates in Chart 1 have effectively been amplified by about 5 percent by exchange rates (as stronger non-dollar currencies were consolidated to weaker U.S. dollars), but the first quarter global rates are very impressive nonetheless. U.S. growth was also good (Chart 2) with Quarter 1 2018 total electronics equipment shipments up 7.2 percent over the same period last year. Since all the Chart 2 values are based on domestic (US$) sales, there is no growth amplification due to exchange rates.We expect continued growth in Quarter 2 but not at the robust pace as the first quarter.Chip Foundry Growth ResumesTaiwan-listed companies report their monthly revenues on a timely basis – about 10 days after month end. We track a composite of 14 Taiwan Stock Exchange listed chip foundries to maintain a “pulse” of this industry (Chart 3).Chip foundry sales have been a leading indicator for global semiconductor and semiconductor capital equipment shipments. After dropping to near zero in mid-2017, foundry growth is now rebounding.Chart 4 compares 3/12 (3-month) growth rates of global semiconductor and semiconductor equipment sales to chip foundry sales. The foundry 3/12 has historically led semiconductors and SEMI equipment and is pointing to a coming cyclical upturn. It will be interesting to see how China’s semiconductor industry buildup impacts this historical foundry leading indicator’s performance. Passive Component Shortages and Price IncreasesPassive component availability and pricing are currently major issues. Per Chart 5, Quarter 1 2018 passive component revenues increased almost 25 percent over the same period last year. Inadequate component supplies are hampering many board assemblers with no short-term relief in sight.Peeking into the FutureLooking forward, the global purchasing managers index (a broad leading indicator) has moderated but is still well in growth territory.The world business outlook remains positive but requires continuous watching!Walt Custer of Custer Consulting Group is an analyst focused on the global electronics industry.

Here’s why the embedded community should care whether the chips they use are built on FD-SOI. FD-SOI has “…dramatically improved the landscape for power efficiency,” NXP VP Joe Yu explains in a recent Embedded Systems Engineering piece (you can read it here). He gets into the hows and whys of the i.MX7ULP chip design, taking a deep dive into the things that the embedded folks really care about. He details how FD-SOI decreases leakage and dynamic power, including the roles played by forward and reverse body biasing. He then goes on to explain why it’s better for analog, and how it prevents latch-up. FD-SOI enables new features, too, he points out, like ultra-low power consumption and deep sleep suspend. And perhaps most importantly, he explains how bursty high-performance and ultra energy efficiency are dynamically traded off on an as-needed basis. “Engineers no longer face a forced selection: low-power processor or high-performance processor,” he say. “Rather, the selection for performance or power efficiency can be made instantaneously, as needed, without having to reconfigure.” All of this plus the rich graphics and user interface FD-SOI enables makes the i.MX 7ULP perfect for “…IoT edge devices, as well as smart home controls, building automation, portable patient monitoring, wearables, and portable scanners.” This is an excellent read: highly recommended. Of course, ASN covered the i.mX7ULP when it was first announced (on Samsung's 28nm FD-SOI) last year – you can still read our coverage here. But it’s good to see the company explaining to their customers how FD-SOI will change the way they build products. BTW, you can get all the i.MX7ULP product details on the NXP website here. NXP has also put together a nifty video on the i.MX7ULP – see it here.

Do you email your doctor when you have a tickle in your throat? Wear a fitness tracker or use an app to monitor your sugar levels, exercise or nutrition? If so, congratulations! You are a part of the rapid growth of digital medicine.Since you’re on the leading edge of this trend to enhance the efficiency of healthcare delivery, you might enjoy learning more about how the medical industry is transforming healthcare in this collection of podcast episodes and video. These are my top picks and just the tip of the proverbial iceberg in how modern medicine is taking today’s technology and applying it to best practices for remote patient monitoring, medical diagnosis, rural healthcare and more.Enjoy! And let me know if you find any others worth the listen!1. Inside Angle: 3M Health Information Systems - Telemedicine: Enhancing Access to Improve OutcomesAccess to healthcare can be a matter of life or death. For some patients, this may mean taking a day off work and driving for hours because services are not available in their hometown.Inside Angle host Dr. Gordon Moore interviews Barb Johnston, co-founder and CEO of HealthLinkNow, about the implementation of telemedicine programs. They discuss how technology impacts telemedicine adoption and related regulations and benefits clinicians and patients in the telepsychiatry and mental health industry. 2. NPR’s The Salt: What’s On Your Plate – This Chef Lost 50 Pounds and Reversed Prediabetes With A Digital ProgramThis short audio clip and article dives into lifestyle and wellness apps designed to motivate users to eat healthier, exercise more and – in some cases – save them from a preventable disease, like diabetes.Wellness apps like Omada Health rely on smartphones, e-coaching, electronic nudging and other methods to encourage users to make and, more importantly, stick to changes that can improve their health. And it’s catching on as other organizations, such as The Centers for Disease Control and Prevention, recognize the difference lifestyle-change programs designed to prevent diabetes are making. 3. Red Hot Healthcare: Episode 57 - Bluer Skies for TelemedicineLast year alone, venture capitalists poured $7 billion into telemedicine. As an emerging concept, telemedicine has a long road ahead until it’s fully integrated and adopted into modern medical practices. Nathaniel Lacktman, partner and health care lawyer with Foley Lardner LLP, discusses legal issues and hurdles surrounding telemedicine today with Red Hot Healthcare host Dr. Steve Ambrose.Lacktman pointed to healthcare providers such as Mercy Virtual Care Center, Mayo Clinic and MDLive that are likely to lead the telemedicine race. This podcast episode is a great listen for entrepreneurs and medical professionals who are interested in learning about compliance and business considerations for the implementation of telemedicine. 4. Digital Health Today: Episode 56 – Eren Bali on Building the World’s Largest Connected Care NetworkEren Bali, CEO and co-founder of Carbon Health, is out to change our fragmented traditional healthcare system with his aim to build the world’s largest connected care network.For Bali, it all started with his sister’s experience consolidating his mother’s health records – scattered over 20 different systems. And from that challenge, his idea to create a universal network that aggregates patient medical records was born.Bali and Digital Health Today host Dan Kendall discuss Bali’s launch of Carbon Health, the new medical records system’s first implementation in a San Francisco primary care clinic, and how providers and patients can get on board with this model. 5. Digital Health Today: Episode 58 – Brennan Spiegel Gets Real About Virtual RealityThis episode of Digital Health Today centers on how Virtual Reality (VR) is being used to enhance patient care. Host Dan Kendall speaks with Dr. Brennan Spiegel, Director of Health Services Research at Cedars-Sinai Health System and Professor of Medicine and Public Health at UCLA, about how immersive technology like VR and Augmented Reality (AR) can improve patients’ experience as well as alleviate pain, anxiety, depression, addiction and more. In a particularly interesting segment, Dr. Spiegel calls the hospital a biopsychosocial jail cell and underscores its importance in not just treating physical ailments but, more wholistically, also addressing the psychological and social wellbeing of patients. 6. TED2017: Raj Panjabi – No one should die because they live too far from a doctor What do you do when access to a doctor means rowing a boat for hours? Millions of people around the world lack access to health care because they live in a remote town or village.In this TED talk, Raj Panjabi, physician in the Division of Global Health Equity at Harvard Medical School, Brigham and Women’s Hospital, and co-founder of Last Mile Health, offers a solution to the problem of healthcare access in the form of the Community Health Academy, a global platform to train and connect community health workers by leveraging devices like smartphones to bring preventative healthcare to even the most far-flung regions of the world. 7. GeekWire’s Health Tech Podcast: How AI is making humans the ‘fundamental thing in the internet of things’Can AI predict which patients are at risk for chronic diseases using their old medical records? This episode of Health Tech Podcast dives deep into the future of healthcare with a look at the potential for AI -- “augmented intelligence” or “assistive intelligence” – to improve patient outcomes, the focus of Ankur Teredesai, a data scientist at the University of Washington and co-founder and CTO of health AI startup KenSci.Clare McGrane, host of GeekWire’s Health Tech Podcast, speaks with numerous experts in this field. They compare precision health to a modern car constantly monitored by microprocessors. The minute something is wrong, you get a warning to take the car to a shop to resolve the issue. The same concept can be applied to humans and deliver big healthcare impacts as research in AI and machine learning continues to evolve. 8. NPR’s Shots: Can Home Health Visits Help Keep People Out Of The ER?In Washington D.C., the city with the highest per capita 911 call volume in all of the U.S., Mary’s Center is piloting a program to provide primary care telemedicine to patients who cannot, or in some cases, do not want to visit the clinic. NPR covers the story of Medicaid patient Dennis Lebron Dolman, who is currently receiving a mix of home visits and virtual treatment.Besides providing healthcare access to rural regions, telemedicine has the potential to reduce emergency room visits in cities as well as improve the health of patients in the long run. Learn more at SEMICON West’s Smart MedTech TechXPOT on Digital Medicine and Remote Patient Monitoring. Hosted by NBMC on July 12, 2018, from 10:30 AM to 12:30 PM, the event will feature healthcare industry leaders exploring state-of-the-art healthcare practices and the future of medical technology. Registration is now open!Amy Ly is a Technical Programs Marketing Coordinator at SEMI.

Good news: there are far fewer bigoted extremists out there when it comes to FD-SOI vs. FinFETs. People want the best technology for their application. It's that simple. That's a key piece of news from the updated survey by Dan Hutcheson, CEO of VLSI Research, which he presented in the afternoon session of the SOI Consortium's 2018 SOI Symposium in Silicon Valley The afternoon then featured presentations by foundry partners, which I'll cover here. Also in the afternoon were presentations by wafer-maker Simgui, some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion. I'll cover those in Part 3 of this series. BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it. The presentations are starting to be posted on the SOI Consortium Events page – but some won't be. Either way, I'll cover them here. VLSI Research A couple years ago at the annual SOI Symposium in Silicon Valley, Dan Hutcheson presented results of a survey he did (ASN covered it – you can still read about it here). At the 2018 event, he presented an update, which is now posted. You can get it here. The FD-SOI roadmap and IP availability are no longer issues for decision makers, he found. The 14nm branch – do you go FinFET or FD-SOI? – is gone. “Fins and FD are complementary,” he observed. Most people said they'd consider using both and running two roadmaps, choosing whichever technology is appropriate to a given design. [caption id="attachment_11841" align="alignnone" width="1000"] (Courtesy: VLSI Research, SOI Consortium)[/caption] From a transistor viewpoint, the top reasons to choose FD-SOI is that it's better for analog and has lower leakage/parastics. It's perceived as better for complex, high mixed-signal SoCs, and especially for RF and sensor integration. In fact, people see RF as the new mixed-signal, wherein FD-SOI is uniquely positioned for 5G and mmWave. From a business viewpoint, FD-SOI is perceived to have real advantages. In particular, FD-SOI wins when it comes to keeping down design costs, manufacturing costs and time-to-market. IoT is still the hottest target market for FD-SOI, to which he adds high growth expected in automotive and medical. Samsung With 20 tape-outs in 2018, Samsung is seeing an acceleration in its FD-SOI business. “The trend is healthy,” said Hong Hoa, SVP of the company's foundry business. FD-SOI, he continued, is on a “differentiation path.” Samsung's 28nm FD-SOI process, called 28FDS is at full maturity with very strong yields. They're seeing more customers and a wider range of applications. The design infrastructure, silicon-verified IP and methodologies are also all mature. They have optimal implementation and verification guidelines for body bias design, a body bias memory usage guide, and a body bias generator integration guide. The process supports Grade 1 automotive, and will be qualified for Grade 2 in a few weeks. FD-SOI, Hoa reminded the audience, offers superior RF performance compared to both planar bulk and 14nm FinFET. The Samsung strategy is to first provide a base for for the FD-SOI process, then add RF and eMRAM. The base for 28nm was done in 2016; they added RF in 2017 and eMRAM this year. The Samsung platform for IoT applications integrates both RF and eMRAM to support multi-function needs in a single platform. Lead customers are already working with eMRAM in their designs, he added. (BTW, Samsung has a really nice video explaining their eMRAM offering – you can see it on YouTube here.) The basic PDK for the Samsung 18nm FD-SOI process (18FDS) will be available in September 2018, with full production slated for fall of 2019. It will deliver a 24% increase in performance, a 38% decrease in power, and a 35% decrease in area for logic. RF for the 18FDSplatform will be ready by the end of this year, and eMRAM beginning in 2019. GlobalFoundries With design wins from 36 customers underway, 12 of which are taping out in 22FDX (GF's 22nm FD-SOI process) this year, the market has validated FDX for differentiation, said GF SVP Dr. Bami Bastani. And indeed, designers are using it for a wide array of applications across North America, Europe, Asia/Pacific and Japan. Customers in the North America are designing in 22FDX for NB-IoT, industrial, RF/analog, mobile, network switches and cryptocurrency applications. In Europe, it's more or less the same plus automotive/mmWave, optical transmission, wireless BTS and AI/ML. In Asia Pacific/Japan the mix is similar to Europe. Bastani sees the three big enablers as the the strengths of the roadmap, the ecosystem and multi-sourcing from Dresden and Chengdu (where they're already equipping the cleanrooms). He also tipped his hat in acknowledgment to the partnership with FD-SOI wafer supplier Soitec, noting that they have gone the extra mile to match GF's requirements. So that was the first part of a great afternoon. As mentioned above, my next post (part 3) will cover a very informative presentation by wafer-maker Simgui on the markets in China, plus talks by some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion.

The growth of China’s semiconductor industry outstripped sector expansion in many other regions in 2017 thanks in part to heavy government investments and supportive state policies. But China’s chip industry also struggled under the weight of overheated investment, inconsistent project quality, insufficient investment in research and development, a poor ability to innovate, and barriers to international cooperation. To overcome these headwinds to growth, China must identify global trends in the development of global semiconductor industry and better understand the forces it needs to mobilize to further expand its own semiconductor sector. AI and 5G fuel global semiconductor industry growthIn 2017, global semiconductor industry revenue reached a seven-year peak, expanding 22 percent to nearly USD 420 billion, and entered a new growth phase with artificial intelligence (AI), 5G and other new technologies leading the surge with greater market segmentation, diversification and decentralization. The emergence of smart automobiles, smart cities, smart medicine, AR/VR and other new markets headed the list of new applications. In the next three to five years, semiconductor industry growth is expected to remain stable, with no marked declines. In 2018, the growth rate is expected to fall to between 5 percent and 8 percent, with the expansion more comprehensive and balanced. The memory market, in particular, will find it hard to match its 2017 blistering growth rate. The market’s expected growth of 10 percent to 20 percent will be chiefly driven by DRAM and 3D NAND Flash. In 2019, NAND growth will continue but DRAM shipments could decline. Emphasis on both innovation and investment key to sustainable growth of Chinese IC Under the China government’s Guidelines to Promote National IC Industry Development, designed to provide key policy guidance and capital support for the development of China’s IC industry, the Chinese semiconductor industry is seeing particularly rapid growth that is expected to be a key contributor to continuing global industry expansion. In IC design, HiSilicon and Unigroup Spreadtrum RDA ranked among the top 10 in the world. In wafer fabrication, Chinese IC manufacturing accounted for 13 percent to 15 percent of global market capacity despite SMIC and Huahong Group lagging international competition in advanced processing. In packaging and testing – China’s strongest segment – JCET, NFME and Huatian Technology also ranked in the global top 10. The Guidelines to Promote National IC Industry Development has fueled a boom in capital investments. However, investments must go well beyond fab construction to add new capacity for China’s semiconductor industry to flourish. A strategy for sustainable, long-term chip industry growth must focus more on technology innovation while continuing heavy capital investments, though it takes time for innovation to lead to higher capacity demand and GPD growth and more jobs. Despite large investments by the 02 Special Project in semiconductor equipment and materials, China trails other regions of the world in advanced technologies. Global spending on semiconductor equipment reached a record-breaking USD 56 billion in 2017, with Korea a major driver. In 2017, Samsung alone invested USD 25 billion in semiconductor equipment, followed by TSMC (USD 10.8 billion), Intel (USD 11.5 billion), Hynix (USD 8.5 billion), Micron (USD 0.5 billion), SMIC (USD 2.3 billion) and YMTC (USD 2 billion). In 2018, Samsung’s equipment spending is expected to drop slightly, to USD 24 billion, while investments by Intel and TSMC will be remain roughly equal. China’s equipment spending will continue to grow in 2018, with SMIC and YMTC maintaining investment levels similar to last year’s and other China semiconductor manufacturers starting to ramp up investments. In 2018, China is expected to surpass Taiwan in equipment spending to claim the number two position after Korea. SIIP China dedicated to international connection and cooperation The huge investments in China’s semiconductor industry need to be supported by robust business strategies, greater international cooperation, deeper expertise in advanced technologies, and more skilled workers. China lags the global industry in all of these areas. The rapid rise of China’s semiconductor industry has raised concerns among many countries over China’s growing influence, with some, most notably the United States, going so far as to implement containment measures. Other regions including Japan, Korea and Taiwan followed suit. The continued growth of China’s semiconductor industry hinges on technological innovation enabled by international cooperation, as well as strong international communication to allay concerns and misunderstandings over the rising prominence of China’s chip sector. China must overcome these obstacles. One partial solution is for China to convince the rest of the world that its need a thriving semiconductor industry if only to meet enormous demand for electronics products within its own borders. As the largest international semiconductor industry association, SEMI enjoys a unique ability to strengthen the connection between China’s semiconductor sector and its international counterparts. SEMI is well-known for its vital support of the traditional semiconductor equipment and materials markets, but SEMI’s work also spans IC design, manufacturing, packaging and testing. What’s more, SEMI has expanded into innovative market vertical applications such as AI, smart manufacturing, smart transportation and smart automotive as it aims to bring together supply chains across these growth areas. For its part, SEMI China remains dedicated to improving communications and cooperation between the Chinese and global semiconductor industries. SEMI China will also continue to encourage deeper collaboration among individual enterprises and government institutions in the interest of industry growth while making full use of SEMI’s international, professional and localization platform to promote the development of China’s semiconductor industry. Last year, we established SEMI Innovation Investment Platform (SIIP) China to help grow China’s pool of skilled workers, promote advanced technology, generate industry capital, and expand China’s semiconductor industry while developing stronger connections with chip sectors in other regions. SIIP China is focused on the following: Promoting sustainable development of the Chinese semiconductor industry Establishing stronger connections to help take advantage of global technology and investment opportunities Providing a platform for open communications between the Chinese and global semiconductor industries Promoting greater coordination between China and its global partners Helping newly enterprises secure funds for expansion Encouraging greater cooperation with foreign semiconductor manufacturers in the interest of openness and mutual benefit will be the best way for China to overcome obstacles to the development of its semiconductor industry. Meanwhile, China will continue to strive to merge into the global semiconductor industry and become a key partner. SEMICON China has witnessed the development of Chinese semiconductor industry SEMICON China marked its 30th anniversary this year. Over the past three decades, China’s semiconductor industry has seen remarkable growth. This year’s SEMICON China was the largest ever. SEMICON China and FPD China 2018 numbered 3,628 booths, covered 74,000 square meters of exhibition space and attracted 1,116 exhibitors from 21 countries and regions and 91,252 professional attendees from 58 countries and regions. Most of China’s top device makers and global leading packaging houses, together with their equipment and materials suppliers, exhibited at SEMICON China and FPD China 2018, representing the global IC manufacturing ecosystem. The number of SEMICON China and FPD China 2018 visitors jumped 32.3 percent from last year, with representation by professionals from the design, manufacturing, assembly and test, equipment and materials sectors. Lung Chu is President of SEMI China.

Thanks to you and the more than 5,000 other industry experts who contribute your time and brainpower, the SEMI Standards Program is celebrating its 45th anniversary in 2018. The first SEMI Standards meeting was held in 1973 to create a dimensional specification for silicon wafers. At the time, the proliferation of more than 2,000 different wafer specifications had led to major inefficiencies as the industry was just getting underway. To address this problem, wafer suppliers gathered under the auspices of SEMI and quickly developed consensus specifications for 2-inch wafers, and by the mid-1970s over 80 percent of wafers being shipped conformed to the new standard.Since that time, the SEMI Standards Program has expanded both geographically and technically. The program now has 20 technical committees in China, Europe, Japan, Korea, North America, and Taiwan, tackling manufacturing challenges across the electronics supply chain. Critical milestones include the development of SEMI S2, the comprehensive safety guideline that has drastically reduced industry incidents and continues to be updated to keep up with the hazards associated with semiconductor manufacturing, and the SECS/GEM and EDA suites of equipment communication standards, which are the backbone of modern day semiconductor “Smart Manufacturing.”As we commemorate our 45th year, there has never been a more diverse and active agenda as we look to solving issues in new areas such as Fan-Out Panel Level Packaging, Electron Microscopy Workflow, and flexible hybrid electronics. Of course, the Standards Program owes its success and longevity to you. I am repeatedly amazed by the dedication of Standards Members, and look forward to continuing the industry collaboration – together we can make the next 45 years as fun and productive as the first!As SEMI president and CEO Ajit Manocha has stated, “SEMI Standards is the oxygen of the industry.”SEMI Standards has saved the industry untold billions of dollars by defining interoperability specifications, guidelines and test methods that have streamlined semiconductor manufacturing and ensured the smooth operation of hundreds of pieces of equipment – all working automatically 24X7.What's more, SEMI Standards has enabled the production of more than 2.2 billion wafers and 1.8 trillion IC devices. Referenced more than 10 million times in production fab purchases, more than 25 SEMI Standards, on average, are cited in each purchase order for semiconductor equipment and materials in the electronic manufacturing ecosystem.