The Advanced Lithography TechXPOT at this year’s SEMICON West will explore progress in extreme ultraviolet lithography (EUVL), its economic viability for high-volume manufacturing (HVM) and other lithography solutions that will address the march to 5nm and onward to 3nm.As a prelude to the event, SEMI asked Mary Ann Hockey, director for Advanced Emerging Lithography at Brewer Science Inc., and a speaker at the TechXPOT, for insights into the status of directed self-assembly (DSA) as it applies to the industry’s march to patterning for the 3nm node and beyond. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Mary Ann Hockey, director for Advanced Emerging Lithography at Brewer Science Inc.SEMI: What is the current status of materials development for DSA?Hockey: We are currently working with strategic customers to implement high-quality DSA chemical material solutions. We are both addressing near-term implementation of standard PS-b-PMMA block copolymers (28-30nm Lo) by leveraging our strategic partnership with Arkema, France, and building a library of high-chi block copolymers for long-term device requirements (Figure 1). SEMI: How do those developments prepare the technology for 5nm, 3nm or beyond?Hockey: We have engaged the strategy of engineering a library of novel high-chi block copolymer (BCP) platforms for next-generation DSA technology requirements of 3-5nm devices. One key objective is a global focus on easing implementation into a manufacturing environment. This objective requires large process windows for guided alignment (accommodating pitch and guide size target variability), minimizing BCP microphase anneal times (short anneal time supports high throughput), and streamlining the total number of process steps required for volume production (Figure 2).SEMI: How will industry’s use of DSA be intertwined with immersion lithography?Hockey: We envision immersion lithography as the foundation enabler with strategic use of optical lithography for generating consistent critical dimension (CD) sizes of DSA guides/templates for low cost of ownership.SEMI: What about the combination of DSA and extreme ultraviolet lithography (EUVL) to fabricate devices at 5nm, 3nm, and beyond?Hockey: EUVL and DSA can potentially work in harmony to support next-generation device technology. DSA can be made with the capability of lithography rectification or enhancing EUVL photoresist sidewalls and targeting low line-edge roughness and line-width roughness (LER/LWR) values.Debra Vogler, SEMI

Christian G. Dieseldorff, Industry Research Statistics Group, SEMI (June 12, 2018)The semiconductor industry is nearing a third consecutive year of record equipment spending with projected growth of 14 percent (YOY) in 2018 and 9 percent in 2019, a mark that would extend the streak to a historic fourth consecutive growth year, according to the latest update of the World Fab Forecast report published by SEMI. The industry last saw four consecutive years of equipment spending growth in the mid 1990s.Korea and China are leading the growth, with Samsung dominating global spending and ascendant China on a fast, steep rise, surging ahead of all other markets. See figure 1.Figure 1: equipment spending by region (includes new and refurbished)Samsung is expected to reduce equipment investments in 2018. Despite the ebb, the company still accounts for a dominant 70 percent of all investment in Korea. At the same time, SK Hynix is increasing its equipment spending in Korea.China’s equipment spending is forecast to jump a whopping 65 percent in 2018 and 57 percent in 2019. Notably, 58 percent of investments in China in 2018 and 56 percent in 2019 stem from companies with headquarters in other regions such as Intel, SK Hynix, TSMC, Samsung, and GLOBALFOUNDRIES. Domestic, Chinese-owned companies – backed by large government initiatives – are building an impressive number of new fabs that will start equipping in 2018. The companies will double their equipment investments in 2018 and again in 2019.Meanwhile, other regions are also ramping up investments. Japan is beefing up equipment spending by 60 percent in 2018, with the largest increases by Toshiba, Sony, Renesas and Micron.The Europe and Mideastern region will boost investments by 12 percent in 2018, with Intel, GLOBALFOUNDRIES, Infineon and ST Microelectronics as the largest contributors. Southeast Asia will increase investments by more than 30 percent in 2018, although total spending is proportionately smaller than in other regions owing to its size. The main contributors are Micron, Infineon and GLOBALFOUNDRIES, though companies including OSRAM and ams are also increasing investments.The SEMI World Fab Forecast, which also includes information on other companies, covers data and predictions through the end of 2019, including milestones, detailed investments by quarter, product types, technology nodes and capacities down to fab and project level.Learn more about the SEMI fab databases at:www.semi.org/en/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats.

With chipmakers looking toward 5nm manufacturing, it’s clear that traditional scaling is not dead but continuing in combination with other technologies. The industry sees scaling enabled by 3D architectures such as die stacking and the stacking of very small geometry wafers. Interconnect scaling also comes into play. This year’s Scaling Technologies TechXPOT at SEMICON West (Scaling Every Which Way! – Thursday, July 12, 2:00PM-4:00PM) will provide an update on the evolution of scaling and describe how the various players (foundry, IDM, fabless, and application developers) are jockeying for innovation leadership. As a prelude to the event, SEMI asked speakers to provide insights on important scaling trends. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/scaling-every-which-way.Challenges for gate-all-around (GAA) and FinFET devicesDiederik Verkest, imec Distinguished Member of Technical Staff, Semiconductor Technology and Systems“During the processing of GAA devices, there are ‘non-line-of-sight’ hidden features that are difficult to control and characterize and may also lead to new defect mechanisms that would impact yield, and possibly product reliability.”Common performance boosters for gate-all-around (GAA) FETs and FinFETs include lower access resistance, lower parasitic capacitance, and stress. “However, one specific performance booster that only applies to GAA is the reduction of the spacing between the vertical wires or sheets,” says Diederik Verkest, imec distinguished member of technical staff, Semiconductor Technology and Systems. “This reduces parasitic capacitance without affecting drive current and hence benefits both performance and power.” He further notes that imec demonstrated the first stacked gate-all-around (GAA) devices in scaled nodes. “In fact, we are the only ones that published working circuits – ring oscillators in a scaled node using industry-standard processes – in our case replacement metal gate (RMG), and embedded in situ doped source/drain (S/D) epitaxy.”“There are two elements of the stacked GAA architecture that need to be addressed,” says Verkest. “The first is that this architecture uses epitaxially-grown layers of Si and SiGe to define the device channel. The use of grown materials for the channel and the lattice mismatch between the two materials represent a departure from the traditional fabrication of CMOS devices, so the industry needs to develop and gain confidence in novel metrology that allows for good control of the layers and also proves their low defectivity.” The second aspect is the three-dimensional nature of the GAA devices. “During the processing of these devices, we have ‘non-line-of-sight’ hidden features that are difficult to control and characterize and may also lead to new defect mechanisms that would impact yield, and possibly product reliability.”Huiming Bu, Director, Advanced Logic/Memory Research - Integration and Device, IBM Research, Semiconductor Group"A new device architecture beyond FinFET is required to provide a full technology node scaling benefit (i.e., density, power and performance) at 5nm and 3nm.”Huiming Bu, director, Advanced Logic/Memory Research - Integration and Device, IBM Research, Semiconductor Group, says that naming of technology nodes has been used extensively for marketing strategies in “foundry land,” but the designations have lost much of their meaning as technology scaling differentiators. “That said, when it comes to technology innovation and value proposition, IBM, in conjunction with Samsung and GLOBALFOUNDRIES, has developed the GAA NanoSheet transistor for 5nm to provide a full technology node scaling benefit in density, power and performance,” says Bu (Figure 1). The key parameters for intrinsic device optimization when scaling to the 3nm node, explains Bu, are the NanoSheet width for better electrostatic characteristics, and the number of sheets for increased current density. Also necessary are strain engineering for carrier transport enhancement, and interconnect innovations for parasitic RC reduction. “Beyond that, the industry needs to look into something different, something more disruptive.”Figure 1. TEM cross section of stacked NanoSheet transistors. SOURCE: IBM Research Materials challengesMaterials challenges are also a concern as the industry moves to 5nm and below. “We see increasing complexity in the material systems that are being used,” explains Verkest. One example he cites in scaled FinFET or GAA technologies is the use of two to three layers of different materials – typically metals such as TiN – to which small amounts of other elements are added to set device characteristics such as the threshold voltage. “At the same time, the requirements for the thickness of these materials, driven by gate dimensions for example, or the distance between the wires, are increasingly challenging.” Other examples of materials challenges are the use of two to three different types of insulators in the middle-of-the-line, each with different etch contrasts. “We use novel materials such as carbon containing oxides or oxynitrides that have lower dielectric constants in order to boost the performance of circuits,” he says, noting that the materials list “is quite long.”Several critical dimensions in transistors at advanced technology nodes have already reached a few monolayers of atoms, fueling expectations for innovation at the material level for transistor scaling, Bu notes. “The other argument is that there is a growing gap between computing demand and the slowdown of technology advancement driven by conventional scaling,” says Bu. One trend that addresses this gap is integrating more computing functions that make the technology solution more modular, which naturally leads to the incorporation of more materials for more applications. Bu cautions, however, that introducing new materials in semiconductor technology has never been easy. “It takes many years of R D to reach this implementation point, if it ever happens. So, do we need new materials when the industry moves to 5nm and 3nm? Yes, though I expect new material implementation to be a lot faster in interconnect and packaging at these nodes rather than intrinsic to the transistor.” Challenges in developing atomic-level processesThere will be challenges in developing atomic-level processes used in scaling, such as atomic layer depositions (ALD) and atomic layer etches, notes Verkest. “These classes of processes are both required to handle the scaled dimensions at the 5nm and 3nm nodes, and also the 3D nature of the scaled technologies – and here we are talking about logic and memories,” Verkest says. “With respect to depositions, we would need to develop thermal ALD processes (not plasma-based) that enable accurate and conformal depositions in non-line-of-sight structures.” Adhesion and wetting, smoothness, and throughput would also need to be addressed. “Longer term, these processes need to facilitate selectivity and self-alignment to address gap-fill challenges in highly scaled structures,” he says. Other concerns he notes with respect to atomic layer etches are selectivity to various materials, and fidelity requirements that increase the requirements for metrology accuracy. “Throughput is also a concern.”Bu believes that a new device architecture beyond FinFET is required to provide a full technology node scaling benefit (i.e., density, power and performance) at 5nm and 3nm. “Beyond 3nm, we may need to continue the transistor scaling in the vertical direction and start to stack them together,” Bu says. He also cites the need for parasitic R/C reduction in the interconnect to take advantage of the intrinsic transistor benefit at the circuit and chip levels. “We see a lot of opportunity in atomic-level processes, especially in atomic layer etch and selective material deposition, to address these challenges in the transistor and the interconnect.” Debra Vogler, SEMI

The fast-maturing hardware and software that are enabling practical applications of equipment intelligence and machine learning mean disruptive change for microelectronics manufacturing. But first comes the basic work of building the basic infrastructure, figuring out IP separation, and learning to solve physical problems in the digital world. Just how much can the semiconductor industry leverage industrial IoT practices from other industries? Common wisdom may be that industrial software solutions aren’t well suited to the IC sector’s complex needs. But GE Digital enterprise account executive Luke Smaul, currently working with Intel, argues that semiconductor fabs and toolmakers are dealing with similar issues as GE did when it first started working with Delta Airlines to monitor the GE engines on Delta planes. Smaul will speak at SEMICON West about GE’s work with Intel over the past few years and, in particular, how its solution for cloud security and IP separation can work for ICs. “GE learned to provide IP security and separation in the aviation space with its suppliers, which moved us all up the value chain, providing a big engine for growth,” says Smaul, who started his career as an IC engineer. “GE Aviation saw a 25 percent increase in issue detection rates by leveraging the same common platform. We’ve shown that we can protect Intel intellectual property in its own cloud space and control who can access what.” A toolmaker can access only particular fab data as needed for analysis, and then can reveal only the output from the analysis and a subset of supporting data. “IP separation has to happen, and it will unlock huge added value,” Smaul says. GE’s Predix solution aims to supply an easy-to-use, plug-and-play system for analytics to enable a yield engineer without a deep data background to select a supported sensor, a gateway to connect automatically to the cloud, and an analytics application to test a hypothesis of how the collected data relates to yield. “This empowers the yield engineer to use and unlock information for a quick improvement, even for simple things such as looking at the impact of degradation of fan performance over time on yield,” says Smaul. “Though the scope may be small, the impact on yield in aggregate, and when scaled, is large.” “There needs to be much more collaboration across the industry to make this work, and to share best practices,” says Smaul. “Just as GE moved from selling gas turbines to selling power-as-a-service, vendors of other big, expensive assets like IC equipment will likely change their business model from selling tools towards selling yield-as-a-service. This will simplify life for the fab while bringing the toolmaker more opportunity to sell improved capabilities on existing tools.” More human intelligence makes AI smarter Applying AI neural network approaches such as deep learning to predict outcomes from digital models is enabling disruptive advances in speech and image recognition, but applying it to complex IC manufacturing problems such as predictive maintenance has been a challenge. These neural networks require massive amounts of data to train, and the IC sector doesn’t really have big data, just a lot of little data clusters due to the dynamics and context richness of processes. This data is difficult to combine for analysis. In addition, the neural network provides only an answer but can’t explain why, notes Michael Armacost, managing director of advanced service engineering at Applied Materials. “We’ve learned that it works better if we do not ignore what we know already, but rather incorporate expert knowledge in a structured way to help us focus on the key features and the key data,” says Armacost, who will also speak in the program. This includes choosing the most important steps to include in the model, identifying the limited data to collect and how to filter the data for outliers, and then selecting the final parameters and features, adjusting the limits, and making adjustments as results drift change over time. The less data needed, the better for the complicated issue of IP protection as well. The big gains from these new analysis approaches will likely require data from more than one company and supporting security for remote connectivity. “Some end users are attempting to do the AI all themselves, but in the long term there will need to be collaboration across companies,” says James Moyne, University of Michigan professor and consultant to Applied Materials, another speaker. Collaboration will need to balance the value of the solution against the risk of compromising IP. “The low-hanging fruit are applications such as predictive maintenance in areas that do not involve high-priority IP. Another approach will be to limit the amount of shared data needed – to first build the model on a wide range of data, but then to use only a very small amount of data to operate the models.” Ready-made models could speed the process Coventor’s semiconductor process models are finding initial applications in R D whereby companies use the simulation to understand the effect of process variation on their complex designs. Instead of running dozens of actual wafers to optimize semiconductor processes, users can instead quickly simulate the results of complex process interactions on their design. Going forward, the process models could find a wide range of applications, from accelerating stabilization of new processes in the fab to enabling real-time co-optimized control across previously independent unit steps to improve wafer uniformity. “This improved uniformity across wafers and equipment could potentially reduce the need for costly physical silicon validation,” suggests Joseph Ervin, Coventor director, semiconductor process and integration, another SEMICON speaker. “Making use of in-situ metrology for real-time control also demands a digital model to process and analyze the collected data for quick response. This area has tremendous potential for improving semiconductor process control.” SEMICON West features a Smart Manufacturing Pavilion with displays and three full days of speakers on building the infrastructure needed to enable disruptive artificial intelligence in the microelectronics sector. www.semiconwest.org The SEMICON West Smart Manufacturing Pavilion features interactive Touch Liquid Crystal Displays (TLCD) and working production equipment on the floor from Bosch Rexroth, Cimetrix, Rudolph Technologies, Inficon/Final Phase Systems, OMRON, DISCO and Edwards Vacuum. For information on the SEMI Smart Manufacturing Initiative and how to get involved, please click here. Paula Doe, SEMI

Hope springs eternal. And it was with collective open arms that many U.S. businesses welcomed the recent talks between U.S. and Chinese officials to resolve their trade differences and downplay the specter of a full-blown trade war. Treasury Secretary Steven Mnuchin went so far to say that trade war with China was “on hold.”Hope and optimism soon fizzled. On May 29th, the White House released a statement contradicting Sec. Mnuchin, announcing that the Trump Administration would indeed move forward with a 25 percent tariff on $50 billion worth of goods imported from China. Besides focusing on goods that the U.S. has deemed are tied to “Made in China 2025” – the Chinese initiative to produce more advanced manufacturing goods domestically – the Administration also announced stiffer investment restrictions and enhanced export controls related to the acquisition of industrially significant technology. The final tariff list will be published by June 15th, and the proposed list of investment restrictions and export controls will be announced by June 30th.Tariffs and New Focus on Export ControlsAll of this comes as the White House and Capitol Hill have heated up their activity in recent months to curb commerce with China through tariffs and investment restrictions.The Section 301 investigation, a key component of this push, has zeroed in on China’s trade practices related to intellectual property violations. Following a months-long inquiry, the Office of the U.S. Trade Representative (USTR) determined in March 2018 that China’s forced transfer of technology and intellectual property has discriminated against U.S. firms. The finding prompted President Trump to respond with a number of remedial actions including a proposed 25 percent tariff on $50 billion worth of U.S. imports from China.More than 100 lines of the proposed tariff list directly impact the semiconductor supply chain, hitting fundamental components of the semiconductor manufacturing process. SEMI has fought back, strongly urging the removal of these tariff lines from the proposed tariff list. At a bare minimum, the tariffs against China will cost the U.S. tens of millions annually in additional taxes, create lost revenue as a result of reduced exports, threaten thousands of high-paying U.S. jobs, stifle innovation and curb U.S. technological leadership – all while not directly addressing U.S. concerns with China.These tariffs, plus the new focus on export controls, is particularly troubling for the semiconductor supply chain. The recent move comes on the heels of other trade actions, including tariffs on steel, aluminum, and solar cells that will not only limit trade and opportunities for U.S. economic growth, but also will introduce significant uncertainty for U.S. businesses. CFIUS Reform Moves Ahead, But Concerns RemainAt the same time, other government efforts that could encumber investment continue. Both the Senate Banking and House Financial Services Committees unanimously passed the Foreign Investment Risk Review Modernization Act (FIRRMA). The legislation aims to upgrade the Committee on Foreign Investment in the United States (CFIUS) – the interagency body that reviews inbound foreign investment for national security concerns. With such rare bipartisan agreement on a major bill, it is expected to be passed by both chambers and signed into law later this year.The current version of the bill is certainly an improvement on earlier drafts. The legislation no longer contains problematic language that would have given CFIUS the authority to review joint ventures between U.S. and foreign companies. The language would have, for the first time ever, expanded CFIUS’s jurisdiction to include outbound foreign investment. Given the semiconductor industry’s deep reliance on expansive global supply chains, this language was particularly concerning to our industry.However, broad concerns remain about how CFIUS functions. In recent months, CFIUS has been used seemingly to evaluate transactions based on economic security, rather than the Congressional intent of national security. Should this trend continued, we worry that this could curb otherwise acceptable investments, stifling innovation and limiting growth, especially in the semiconductor industry.SEMI Educates Lawmakers on Industry ImpactsWith tensions likely continue to rise and efforts to wall off commerce with China ongoing, SEMI is engaging with policymakers to educate them on how these restrictions will potentially undermine the long-term health of the semiconductor industry. SEMI will continue to meet with policymakers about the critical importance of trade and investment to the continued success of the semiconductor industry. If you are interested in more information on trade, or how to be involved in SEMI’s public policy program, please contact Jay Chittooran, Public Policy Manager, at [email protected].

With Southeast Asia’s semiconductor industry expected to grow up to 12 percent this year, the stakes at SEMICON Southeast Asia were high. The challenge: to drive industry connection, collaboration and innovation across a broad range of technologies to accelerate growth in the electronics manufacturing supply chain.SEMICON Southeast Asia 2018 delivered.The region's premier gathering of the global electronics manufacturing supply chain, SEMICON Southeast Asia drew an event record of more than 7,500 visitors and over 300 exhibitors to its debut at the Malaysia International Trade and Exhibition Centre (MITEC) in Kuala Lumpur. The Market Trends Briefing, an event favourite, offered insights into the latest trends and developments on forward-thinking topics as diverse as the machine as an integral part of human society (NXP Semiconductors Singapore) and intelligent robots (Festo Robotics). Key industry topics including semiconductor fab investments (SEMI) and drivers and applications for Fan-Out Wafer-Level Packaging (TechSearch International) also highlighted the briefing. 2018 Year to Date Statistics from the Market Trends Briefing For the first time, SEMICON Southeast Asia convened policy makers and industry leaders in a panel – the CXO Speaks session – that provided insights into how the region can strengthen its manufacturing ecosystem, capture new opportunities in IoT, and build a resilient and growing electronics industry. The panelists agreed that the Southeast Asia semiconductor market will continue to grow exponentially in the digital era, and that regional players must not only collaborate to sustain this growth momentum but build a strong talent pipeline to continue to drive IoT innovation.With connection clearly critical to the industry’s growth, the event’s Business-Matching sessions and industry VIP networking brought business leaders together to find new partners and opportunities.Themed ‘Think Smart, Make Smart,’ SEMICON Southeast Asia featured few devices smarter and more innovative than Festo’s AirJelly, a radio-controlled airborne jellyfish. The first indoor flying object with peristaltic drive mimics the movement of a real jellyfish – except in the air. The device’s eight tentacles adapt to its environment, just like its 500-million-year-old sea-roaming cousin. A lithium-ion battery, an electric motor and a bit of helium are its wings, allowing it to take flight.The ‘World of IoT,’ a show-within-a-show, highlighted enabling applications and technologies for the IoT revolution. This interactive experience was helmed by seven Malaysian technology start-ups that showcased present and near-future consumer technologies such as autonomous vehicles, smart AI devices and virtual reality applications enabled by semiconductor innovations.In an effort to attract STEM talent to the industry, SEMICON Southeast Asia for the first time staged a panel with 11 experts from the public sector and seven from the private sector to discuss strategies for encouraging young graduates to pursue engineering careers and building a talent pipeline. For their part, the SEMICON Southeast Asia university programme and the Electronics Talent Career Fair focused on helping to build the global semiconductor industry as it faces a worker shortage.At SEMICON Southeast Asia’s Technology Innovation Forum, thought leaders from across the industry answered the question: What does Smart Manufacturing mean to the electronics manufacturing supply chain? While presenters from GLOBALFOUNDRIES, Amkor, PricewaterhouseCoopers, Infineon, Lam, IBM, Omron, and OSRAM looked at Smart Manufacturing from very different positions in the supply chain, they shared common issues with data sharing and data protection, and decision-making methodologies when monitoring a huge influx of sensor data. Samivel Krishnamoorthy, Director of Digital Manufacturing Industrialization at OSRAM, closed the session with a real-world look at the work necessary to transition a cluster of production lines with different systems to Smart Manufacturing capable lines following common systems and data handling techniques. OSRAM embraces SEMI Standards for use in conventional silicon front-end manufacturing in for Osram’s LED production. Krishnamoorthy detailed an exceptional analysis process to benchmark and adapt best practices to complex, multi-stakeholder technology production environments.Those looking for a highly influential audience from every segment of the global microelectronics manufacturing supply chain found it as SEMICON Southeast Asia. Technology and business leaders from segments including semiconductors, LEDs, MEMS, printed/flexible electronics, and other adjacent industries were a powerful presence at the event.Held for the first time in Kuala Lumpur, the event remained true to its mission to connect electronics industry innovators and thought leaders from business, academia and research from both region and all over the world. SEMICON Southeast Asia 2019 will once again be held at MITEC.Kai Fai Ng is President, SEMI Southeast Asia.

“GlobalFoundries, TowerJazz, TSMC and UMC are expanding or bringing up RF SOI processes in 300mm fabs in an apparent race to garner the first wave of RF business for 5G, the next-generation wireless standard,” writes Mark Lapedus of Semiconductor Engineering. His recent piece, RF-SOI Wars Begin, explains why demand across the supply chain is currently tight. Rest assured, the supply situation is being addressed fast. By next year, 300mm-based RF-SOI manufacturing (vs. 200mm) will increase from 5% to 20%. But with insatiable end-user demand for greater throughput, overall RF-SOI device demand is increasing in the double-digit range, so 200mm-based manufacturing is also expanding fast. [caption id="attachment_11905" align="alignleft" width="300"] The front-end modules in all smartphones are built on Soitec's RF-SOI wafer technology. The most advanced, for LTE/LTE-A, are built on Soitec's RFeSI-SOI wafers, which have four layers to meet the demands of devices with high linearity requirements. (Courtesy: Soitec)[/caption] SOI wafer manufacturer Soitec has 70% of the RF-SOI wafer market share. The other RF-SOI wafer manufacturers – Shin-Etsu, GlobalWafers and Simgui – all use Soitec's RF-SOI wafer manufacturing technology. This is an excellent, comprehensive piece, that clearly explains the complexities of the markets, the devices, the manufacturing and the supply chain. It's a highly recommended read. BTW, the SOI Consortium is organizing a 4G/5G SOI supply chain workshop during Semicon West (July '18). Sign up or get more information on that under the Events tab here on the consortium website. Of course, here at ASN, we've been covering RF-SOI for over a decade. You can use our RF-SOI tag to access most of the pieces we've done over the years.

This year’s Advanced Lithography TechXPOT at SEMICON West will explore the progress on extreme ultra-violet lithography (EUVL) and its economic viability for high-volume manufacturing (HVM), as well as other lithography solutions that can address the march to 5nm and onward to 3nm. Several session speakers offered their insights into the readiness of EUVL for 5nm and how other lithography solutions will enable 3nm. See the full list of speakers and program agenda at http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Diverging viewpoints on EUVL readiness for 5nmMike Lercel, Director of Strategic Marketing at ASMLASML expects its first customer to start volume manufacturing with EUV at the 7nm logic node and the mid-10nm DRAM node in the 2018/2019 timeframe. “EUV will replace the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future,” said Lercel. “For the 5nm logic node, more layers are expected to migrate to EUV.”Three ASML customers have early-access versions of the next-generation TWINSCAN NXT:2000i for the development of advanced logic and DRAM nodes. “This system delivers 2.0nm cross-matched on-product overlay, achieved through several hardware advancements,” noted Lercel. “It is also significant because this mix-and-match use with EUV features a significantly different hardware platform.” TWINSCAN NXT:2000i features a new alignment sensor and improved wafer table flatness, endurance, and clamping mechanism to enhance matching to EUV.ASML has achieved good industrialization progress of its pellicle, with tests confirming that pellicles can withstand 245W source power and an offline power lifetime test indicating 400W capability. Compared to the 7nm logic node, the requirements for EUV masks will become tighter at 5nm, but Lercel noted that ASML sees good progress with the industry infrastructure to support 5nm in areas such as reducing mask blank defects. “We will continue to improve pellicle transmission for enhanced throughput, but there are no fundamental changes in pellicle requirements for 5-3nm logic nodes. We see no infrastructure showstoppers for the introduction of EUVL at the 5nm node.”Stephen Renwick, Director of Imaging Physics at Nikon Research Corporation of AmericaRenwick said that the 7nm logic node is expected to be fabbed mostly using 193i lithography. “EUV will struggle to be ready for 5nm, limited by yield issues caused by stochastic effects in the resist,” said Renwick. “Ready or not, though, it will be used.” Renwick suggests that introducing multiple-patterning with EUV may be needed but would increase costs. “193i lithography will continue to be used with quadruple-patterning and in combination with other techniques – there is no single solution.”Figure 1. Normalized cost/layer vs. lithography method. SOURCE: Nikon Research Corporation of America When choosing between immersion lithography and EUV for different customer segments at 5nm, Renwick noted that the cost depends on the layer. “Some time ago, we calculated that the costs of either 193i triple-patterning or 193i SADP with two cuts were roughly equal to single-patterning with EUV,” explained Renwick (Figure 1). “That agreed with chipmakers' public estimates and meant that the choice of lithography method depended more on the performance tradeoffs involved, such as 193i's better line-edge roughness. At the 5nm node, we are probably faced with quad-patterning from 193i, double-patterning from existing EUV tools, or single-patterning from as-yet undelivered high-numerical aperture (NA) EUV tools.” Renwick believes that the competition between low-NA EUV double-patterning and 193i quad-patterning will be similar to the current situation (i.e., comparison of 193i triple-patterning or 193i SADP with two cuts vs. single-patterning with EUV), but for high-NA EUV tools he believes it's too early to say.Other challenges Renwick sees on the horizon for EUVL at 5nm are stochastic effects in EUV resists. “They cause yield problems on contact arrays and unacceptable line-edge roughness on line/space patterns,” said Renwick. “It's unlikely that these effects will go away without increasing the litho dose, which will further challenge throughput performance.” He also questions whether EUV pellicles, though under development, will be “ready for prime time.”Harry Levinson, Sr. Director of Strategic Lithography Technology and Sr. Fellow at GLOBALFOUNDRIESLevinson said additional fundamental engineering work is needed to ready EUV lithography for 5nm. “Among the top problems are stochastics-induced resist defects, which increase significantly as dimensions shrink below those for 7nm,” explained Levinson (Figure 2). “Higher exposure doses will be required to address these issues related to stochastics at 5nm, which will require higher source output” (than 7nm).Levinson said there will be greater motivation to use EUVL at the 5nm node vs. at 7nm to offset the large number of exposures associated with 193nm immersion multiple-patterning solutions. “The primary application of EUV lithography at 7nm will be for contact, via and cut layers,” Levinson noted. “It will be important to enable EUVL for metal masks at the 5nm node, which increases the need for an ample supply of very low defect EUV mask blanks.” Levinson added that the 7nm node is already stressing defect inspection capabilities, and no actinic defect inspection system is yet available for patterned masks. “This situation becomes more problematic with widespread application of EUVL to metal layers.” Mask development for 5nmChristopher C. Progler, CTO Strategic Planning at PhotronicsProgler said that the basic infrastructure for delivering EUV masks is available, especially for dark field layers and near in nodes. “The interconnected or more open frame patterns will need refinements to the processes and two to three nodes out will need certain new infrastructure,” said Progler. Overall, the main challenges for initial insertion are about creating a cost-effective and rapid-turn EUV mask process, he said. “The industry can certainly deliver EUV masks in some form. It is more a question of doing it efficiently and productively to match the stated value proposition of EUV over other lithographic methods. We don’t want a pick two of ‘cost, cycle time, capability’ sort of mask solution.” More specifically, Progler explained that after the initial EUV mask development for 5nm focused on contacts and block layers, the major push for N5 switched to delivering single-exposure EUV metal patterning as early as possible. “This has opened some new challenges for masks given the resolution, critical pattern density and tight pitch defect requirements of the re-aggregated single-layer metal mask designs,” said Progler. “For example, on the resolution side, we are accelerating the insertion of higher dose photoresists and also driving patterning module improvements in CD control, mask LER and sidewall angle.” Progler added that at N5, the mask 3D structure itself – including the sidewall – will have a greater impact on lithography because it is tied to stochastic error rates on the wafer.“Reliable, wide-area metrology for some of these 2D and 3D mask parameters is currently hard to come by. We may see an evolution of the blank structure at some point in N5, including hard mask options for pattern stability and expect earlier insertion of EUV mask process correction with model-based hot spot detection and rule checking as well. We also hope mask-scanner dedication is not needed, but there are some indications process sensitivity may push us earlier in this direction.” He added that to reduce metal layer defects, more attention needs to be devoted to advanced repair and model-based validation. “We are, unfortunately, still in a situation of blurry vision and high native defect counts alongside possible in situ contamination during mask changes.” Figure 2. Resist stochastics-induced defects. Graph courtesy of Peter DeBisschop, imec; SOURCE: GLOBALFOUNDRIES Progler pointed out that, with the advent at 5nm, metal masks will require some level of actinic blank inspection for yield, increasing the cost of an already expensive mask technology. “So, unless we want to contend with double and triple photomasks’ starts to deliver a single metal layer, it will be very important to tighten the multi-sensor inspection, defect abatement, and repair loops,” said Progler. He does see some clouds forming around high-volume manufacturing pellicles for metal layers. “This remains an open question, mainly for thermal and materials reasons, not to mention cost and cycle time,” Progler said. “We may be pessimistic, but we do not see an HVM pellicle solution converging in the required timeframe, which means leaning even more on a wafer-level inspection in the validation loop.” He believes that streamlining validation will be a differentiator. “I can imagine one losing most of the EUV cycle time benefits by endlessly circling masks around if this is not done well.” How does the industry get to 3nm? ASML plans to ship its first high-NA EUV prototope/pilot systems between 2020 and 2023 to support 3-2nm process development. “System designs are now being finalized and the platform is starting to come to life,” said Lercel. ASML supplier ZEISS is building a high-NA cleanroom for optics production. ASML believes that EUV, high-NA and DUV systems will be used together at the most advanced nodes and is designing to account for this mixed environment. “As chipmakers drive toward smaller geometries in the most advanced nodes like 3nm, they face unprecedented challenges in devices and materials. This will make the process control requirements even more challenging.” ASML is tackling these challenges with its YieldStar metrology platform, e-beam metrology (HMI) and computational lithography solutions that are designed to expand the process window, enhance process control, and improve patterning defect detection. “This ‘Holistic Lithography’ approach will become increasingly important to ensure throughput and yield at the most advanced nodes.”Levinson said that the issues he projects for 5nm will need to be addressed further at 3nm. “The challenges associated with resists at 3nm dimensions are such that it isn’t clear that chemically amplified resists will be capable of meeting requirements,” said Levinson. “If true, we would be seeing the most significant change in resist platforms in a quarter of a century. Potentially cost-reducing technologies such as directed self-assembly (DSA) are always welcome, but EUVL will be the lithographic workhorse through the 3nm node, and likely beyond.”At 3nm, mask makers will confront the realities of higher EUV NA tools. “We will need to implement thinner mask absorbers, new films, and perhaps hard masks,” Progler said. “This puts us in a new materials regime for masks, and history has shown us the mask industry takes a long time to refine processes and tools for new mask materials.” He explained that the small scale of the mask ecosystem and the small number of large suppliers available to address the challenges accounts for this lengthy time frame. Still, looking ahead, Progler noted that Photronics has already done a few studies on the impact of proposed half-field, high NA anamorphic optics on masks. "We uncovered some challenges that need to be addressed, particularly at boundaries and within the overall mask flow,” said Progler. As mask resolution continues to scale down, the industry will need fundamentally higher resolution mask making and inspection processes, requiring next-generation multi-beam mask writing and electron beam inspection, he explained.At 3nm and below, Progler noted that the metrology needs for masks, while not as severe as that for wafers at these nodes, will test the mask equipment infrastructure in ways that could challenge the relatively small mask industry. “Of course, EUV multi-patterning comes into play as well, and with that, the SRAF sizes will drop below 20nm, requiring an asymmetric compensation over a much wider influence area than the OPC people are used to considering.” With EUV multi-patterning, Progler explained that it will be increasingly important to match or pair EUV masks and to consider how 3D effects and stochastics will drive new technology to enable new requirements for high-speed metrology and simulation components. “All the justifiable hand-wringing over EPE with ArF multi-patterning today gets introduced to the EUV scene when masks are ganged together to make a single device layer,” said Progler.Debra Vogler, SEMI

Years of industry consolidation in the critical subsystems market appears to be coming to an end.The top 10 suppliers’ share of the critical subsystems market has stabilised at around 50 percent after many years of industry consolidation. Through a combination of acquisitions and organic growth, this percentage has been increasing steadily from 38 percent at the turn of the millennium. However, in recent years the trend has slowed considerably as medium and smaller sized suppliers are starting to provide stiffer competition for incumbents. Driven by a number of factors, consolidation produces a number of benefits that accrue to the resulting larger suppliers, including the following: Economies of scale Combined research and development budgets Improved access to global markets through strategic regional acquisitions Stronger financial backing that can facilitate any required rapid scale up in production For their part, buyers must rely on a smaller pool of larger suppliers and face these downsides: Less innovation Less flexibility In some cases, dependency on a single supplier for a particular subsystem that can lead to supply chain bottlenecks Until 2014, the balance was clearly in favour of consolidation, but since then the trend has stalled and there is strong evidence that over the next few years the trend may even revert, favouring medium and smaller sized suppliers. The current industry upswing has already allowed these companies, versatile and nimble enough to quickly develop and deliver innovative solutions, to gain market share from overstretched incumbents. What’s more, OEMs and chipmakers, increasingly concerned about having to rely on a single or dominant source for their most critical subsystems, are effectively imposing a spending cap with some large suppliers while collaborating with medium and smaller sized suppliers and encouraging them to step up.The data supporting these observations suggests that the main beneficiaries are companies ranked between 11th and 30th in size, with many of these organizations’ market share growth slightly outpacing that of the top 10 in recent years.For more information about VLSI Research and Critical Subsystems, visit www.vlsiresearch.com. Julian West is a technical and marketing analyst at VLSI Research Europe.

Some really innovative start-ups presented chips they're doing on FD-SOI at the SOI Consortium’s 2018 SOI Symposium in Silicon Valley. We'll cover those here in Part 3 of ASN's coverage, as well as a presentation on China by wafer-maker Simgui and the final panel discussion. BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it. And in the afternoon the foundry partners provided excellent insight into who's designing chips on FD-SOI, and VLSIresearch explained why. You can read that here. Some of the presentations are posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here. Start-upsIneda Systems began as an ADAS start-up, and are now working on developing low-power SoCs for use in consumer and enterprise applications. They're using FD-SOI for their current family of chips. SVP Ramkumar Subramanian emphasized that NRE costs are really important for smaller designs. 22FDX, he said, enabled them to move from 40nm, and ramp to larger volumes. In February, GreenWaves Technologies, a fabless semiconductor startup designing disruptive ultra-low power embedded solutions for image, sound and vibration AI processing in sensing devices, announced its GAP8 IoT application processor. GAP8 evaluation boards can now be ordered. The GAP8 agile power management architecture combined with IOT low duty cycling is a perfect fit for FDSOI processes. CEO Loic Lietar talked about how it would be used in AI applications at the very edge, wherein only the necessary data should be uploaded to the cloud. Also in February, Dream Chips’ announced that its ADAS SoC fabbed in GlobalFoundries’ 22FDX (FD-SOI) technology was posting record power efficiency (you can read more about it in ASN's coverage at the time here.) Dream Chips is Germany’s largest independent Engineering Service Provider. At the symposium, CEO Jens Benndor's talked about their roadmap. [caption id="attachment_11865" align="alignleft" width="300"] (Courtesy: eVaderis, SOI Consortium)[/caption] eVaderis CEO Jean Pascal Bost talked about how data-intensive IoT applications are enabled with FD-SOI and embedded magnetoresistive non-volatile memory (eMRAM) technology. You can get the slides from his talk here. eVaderis has eflash-like and eSRAM-like eMRAM IP that covers most MCU applications. They also have an eMRAM compiler tool and high-value-added IP for 22FDX. They foresee impressive power savings at the system level with body biasing: 25x this year and up to 45x in 2020, so that intelligence can be brought to IoT. In February they announced that they are co-developing an ultra-low power MCU reference design using GF’s eMRAM technology on the 22FDX® platform. And in March eVaderis and Mentor/Siemens announced that eVaderis proprietary Magnetic Tunnel Junction (MTJ) model would be co-optimized with AFS to speed-up simulations and generations of embedded MRAM IPs and compiler products with good accuracy.An 22FDX MCU reference design project is underway, with tape-out in July '18. Reduced Energy Microsystems (REM) CEO William Coven talked about realizing near-threshold computing with 22FDX and low-power memories. REM has two products on 22FDX: their Neuron Vision SoC and 64-bit RISC-V IP cores. 22FDX, he says, has been fantastic. Simgui Jeffrey Wang, the CEO of wafer-maker Simgui looked at why China is promoting its IC industry. (In the SOI ecosystem, Simgui is particularly known for its RF-SOI wafers, which it produces using Soitec's Smart CutTM process.) This was more of an overview talk, not necessarily specific to the SOI ecosystem, but certainly interesting. In terms of worldwide semiconductor sales, he said, about half end up in China. The CICF – aka the Big Fund – is currently running at about $74 billion. Having realized that mergers acquisitions would not solve the problem, they've opened a second round, targeting another $160 billion. China's two biggest innovation success stories are Huawei (with its Kirin processor), and China Rail, which is now a global Fortune 500 company. The CAGR for the China semiconductor industry is 19%, though they need 20% to reach their goals. IC design is a particularly successful area, posting a CAGR of 29%, with two players in China in the top 10 worldwide. Packaging and assembly/test are also very strong. Zing is working on increasing the supply of 300mm silicon wafers, while Simgui is expanding in both 200 and 300mm capex, due to “big demand”, he said. Panel Discussion [caption id="attachment_11866" align="alignleft" width="300"] SOI Symposium Panel Discussion: (left to right): Giorgio Cesana (Co-Director SOI Consortium), Dave Eggleston (VP GF), Tim Saxe (CTO, Quicklogic), Wayne Dai (CEO, Verisilicon), Samir Patel, (CEO Sankalp Semi), Kelvin Low (VP, ARM), Mahesh Tirupattur (EVP, Analog Bits)[/caption] The day wrapped up with an excellent panel discussion moderated by SOI Consortium Executive Co-Director Giorgio Cesana. Here are a few of the observations made by the panelists. QuickLogic CTO Tim Saxe said that FD-SOI made their designs more compact. With FD-SOI for FPGAs, you've got one set of IP, and you can decide at runtime where you're going for low power or high performance. With a lot of power domains, you see the benefits at the system level. GF VP Dave Eggleston said they're seeing early adopters of eMRAM, especially for wearables with RF and low power. ARM VP Kelvin Low said people should do more than just migrate to FD-SOI. If they use back biasing, it can replace the need for big/little cores. Body biasing makes things easier, maintained Verisilicon CEO Wayne Dai. His teams find that with body biasing, you can tape out for “typical” instead of “worst case”. It's not too late for FD-SOI: it's perfect timing for the MCU market, which is still at 40nm, said Sankalp Semi CEO Samir Patel. As designers, they're happy to focus on companies still on the older nodes. The IP ecosystem should be more enthusiastic about FD-SOI, said Analog Bits EVP Mahesh Tirupattur. You've got more potential customers, and your volume runs can be bigger. In his closing remarks, SOI Consortium Executive Co-Director Carlos Mazure reminded the audience of the day's three take-aways: power consumption is driving even systems companies FD-SOI is penetrating fields like MCUs and SoCs where more intelligence is needed China is still a really big opportunity.