Administrator, Iris Rith

Here’s why the embedded community should care whether the chips they use are built on FD-SOI. FD-SOI has “…dramatically improved the landscape for power efficiency,” NXP VP Joe Yu explains in a recent Embedded Systems Engineering piece (you can read it here). He gets into the hows and whys of the i.MX7ULP chip design, taking a deep dive into the things that the embedded folks really care about. He details how FD-SOI decreases leakage and dynamic power, including the roles played by forward and reverse body biasing. He then goes on to explain why it’s better for analog, and how it prevents latch-up. FD-SOI enables new features, too, he points out, like ultra-low power consumption and deep sleep suspend. And perhaps most importantly, he explains how bursty high-performance and ultra energy efficiency are dynamically traded off on an as-needed basis. “Engineers no longer face a forced selection: low-power processor or high-performance processor,” he say. “Rather, the selection for performance or power efficiency can be made instantaneously, as needed, without having to reconfigure.” All of this plus the rich graphics and user interface FD-SOI enables makes the i.MX 7ULP perfect for “…IoT edge devices, as well as smart home controls, building automation, portable patient monitoring, wearables, and portable scanners.” This is an excellent read: highly recommended. Of course, ASN covered the i.mX7ULP when it was first announced (on Samsung's 28nm FD-SOI) last year – you can still read our coverage here. But it’s good to see the company explaining to their customers how FD-SOI will change the way they build products. BTW, you can get all the i.MX7ULP product details on the NXP website here. NXP has also put together a nifty video on the i.MX7ULP – see it here.

Good news: there are far fewer bigoted extremists out there when it comes to FD-SOI vs. FinFETs. People want the best technology for their application. It's that simple. That's a key piece of news from the updated survey by Dan Hutcheson, CEO of VLSI Research, which he presented in the afternoon session of the SOI Consortium's 2018 SOI Symposium in Silicon Valley The afternoon then featured presentations by foundry partners, which I'll cover here. Also in the afternoon were presentations by wafer-maker Simgui, some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion. I'll cover those in Part 3 of this series. BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it. The presentations are starting to be posted on the SOI Consortium Events page – but some won't be. Either way, I'll cover them here. VLSI Research A couple years ago at the annual SOI Symposium in Silicon Valley, Dan Hutcheson presented results of a survey he did (ASN covered it – you can still read about it here). At the 2018 event, he presented an update, which is now posted. You can get it here. The FD-SOI roadmap and IP availability are no longer issues for decision makers, he found. The 14nm branch – do you go FinFET or FD-SOI? – is gone. “Fins and FD are complementary,” he observed. Most people said they'd consider using both and running two roadmaps, choosing whichever technology is appropriate to a given design. [caption id="attachment_11841" align="alignnone" width="1000"] (Courtesy: VLSI Research, SOI Consortium)[/caption] From a transistor viewpoint, the top reasons to choose FD-SOI is that it's better for analog and has lower leakage/parastics. It's perceived as better for complex, high mixed-signal SoCs, and especially for RF and sensor integration. In fact, people see RF as the new mixed-signal, wherein FD-SOI is uniquely positioned for 5G and mmWave. From a business viewpoint, FD-SOI is perceived to have real advantages. In particular, FD-SOI wins when it comes to keeping down design costs, manufacturing costs and time-to-market. IoT is still the hottest target market for FD-SOI, to which he adds high growth expected in automotive and medical. Samsung With 20 tape-outs in 2018, Samsung is seeing an acceleration in its FD-SOI business. “The trend is healthy,” said Hong Hoa, SVP of the company's foundry business. FD-SOI, he continued, is on a “differentiation path.” Samsung's 28nm FD-SOI process, called 28FDS is at full maturity with very strong yields. They're seeing more customers and a wider range of applications. The design infrastructure, silicon-verified IP and methodologies are also all mature. They have optimal implementation and verification guidelines for body bias design, a body bias memory usage guide, and a body bias generator integration guide. The process supports Grade 1 automotive, and will be qualified for Grade 2 in a few weeks. FD-SOI, Hoa reminded the audience, offers superior RF performance compared to both planar bulk and 14nm FinFET. The Samsung strategy is to first provide a base for for the FD-SOI process, then add RF and eMRAM. The base for 28nm was done in 2016; they added RF in 2017 and eMRAM this year. The Samsung platform for IoT applications integrates both RF and eMRAM to support multi-function needs in a single platform. Lead customers are already working with eMRAM in their designs, he added. (BTW, Samsung has a really nice video explaining their eMRAM offering – you can see it on YouTube here.) The basic PDK for the Samsung 18nm FD-SOI process (18FDS) will be available in September 2018, with full production slated for fall of 2019. It will deliver a 24% increase in performance, a 38% decrease in power, and a 35% decrease in area for logic. RF for the 18FDSplatform will be ready by the end of this year, and eMRAM beginning in 2019. GlobalFoundries With design wins from 36 customers underway, 12 of which are taping out in 22FDX (GF's 22nm FD-SOI process) this year, the market has validated FDX for differentiation, said GF SVP Dr. Bami Bastani. And indeed, designers are using it for a wide array of applications across North America, Europe, Asia/Pacific and Japan. Customers in the North America are designing in 22FDX for NB-IoT, industrial, RF/analog, mobile, network switches and cryptocurrency applications. In Europe, it's more or less the same plus automotive/mmWave, optical transmission, wireless BTS and AI/ML. In Asia Pacific/Japan the mix is similar to Europe. Bastani sees the three big enablers as the the strengths of the roadmap, the ecosystem and multi-sourcing from Dresden and Chengdu (where they're already equipping the cleanrooms). He also tipped his hat in acknowledgment to the partnership with FD-SOI wafer supplier Soitec, noting that they have gone the extra mile to match GF's requirements. So that was the first part of a great afternoon. As mentioned above, my next post (part 3) will cover a very informative presentation by wafer-maker Simgui on the markets in China, plus talks by some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion.

“The ecosystem is ready. The focus is now on applications and products.” And with those words, SOI Consortium Executive Director Carlos Mazure opened the annual Silicon Valley SOI Symposium. As promised, the day was packed with presentations about products on FD-SOI – some from big players like NXP and Sony, some from names new to the FD-SOI ecosystem like Audi and Airbus, and some from start-ups just getting into the game. The event got excellent coverage in EETimes/EDN – including in their editions across the globe in China, Japan, Taiwan, India and more. Samsung, GF Ramp FD-SOI, heralded the headlines. It was a full day of excellent presentations. In this post, I'll chronicle the morning presentations. The next post(s) will cover the afternoon session. Note that as of this writing, the ppts are not yet posted on the SOI Consortium website, but many will be. Keep checking back under the Events tab, and look under “past Events”. Andes Technology As semiwiki noted a few years back, Andes Technology is “...the biggest microprocessor IP company you've never heard of.” Based in Taiwan, Mediatek is one of their big customers; they've got a strong client base across Asia/Pacific, and are now making inroads into North America. Last year they announced with GF their 32-bit CPU IP cores had been implemented on GF's 22FDX® FD-SOI technology. In his symposium keynote, CEO Frankwell Lin said that in the test chip they're doing with GF and Invecus, they're seeing a 70% power savings compared with what they'd gotten in 28ULP. Their newest products are the N25 32bit and NX25 64bit RISC-V based cores, and in July they'll announce a core that runs on Linux. NXP “With FD-SOI we're enabling the future of embedded processing,” the always-quotable (and keynote speaker) NXP VP/GM Ron Martino told us. NXP's i.MX7ULP, i.MX8, i.MX8X and i.MXRT are all FD-SOI based. They all share fundamental building blocks, so NXP can build platforms, scale and re-use IP. “It's better than any technology I've worked on in my 30 years in the industry,” he said. They're seeing much higher performance with on-chip flash. And the RT “crossover” processor boasts 3x higher computing performance than today's competing MCUs. This is going to be critical for edge computing going forward, to which end NXP is working very closely with foundry partner Samsung. FD-SOI is not just helpful for the logic part of these chips – memory technologies also share in the benefits. They get much higher performance with on-chip flash. Leakage is cut by a factor of ten with biasing techniques, and the enhancements mean that memory can operate at very low voltages. NXP is increasingly sophisticated with how they use body biasing, applying high-granularity techniques to independent domains in different parts of the chips. Getting sub-0.6 Vmin delivers value at multiple levels: on battery life, on total system cost, and on system enablement. Invest in body biasing if you want to get leadership results, advised Martino. Edge computing – including machine learning and neural networks for things like image classification – is a big target, he continued. At the last CES they did a proof-of-concept “foodnet” where two appliances talked to each other without having to go to the cloud. In that case it was an i.MX8 in a fridge and an i.MXRT in a microwave, but he explained that the same concept can be applied to a car for driver awareness, where you don't want to take the extra time for or don't have a connection to the cloud. iMX and FD-SOI enable scalable solutions, he concluded. Audi What's a metal-bending company doing talking about electrons? asked Audi Project Manager Dr. Andre Blum. And why SOI? Well, for Audi, he said, SOI stands for Solutions, Opportunities and Innovation. [caption id="attachment_11790" align="alignleft" width="300"] Audi Project Manager Andre Blum says SOI stands for Solutions, Opportunities and Innovation -- at the 2018 SOI Symposium in Silicon Valley.[/caption] Audi is working on the various levels of autonomous driving, and they want it to be without design limitations. That means being able to hide sensors wherever they're needed. They'll create a cocoon around the car for the best driver experience. He showed a fun video Audi's made to illustrate their concept – it's the Invisible Man video, which you can check out on YouTube. But those new architectures can't up the power budget (think heat): rather they need to cut power drastically while increasing performance. And with FD-SOI, they see an opportunity to do just that, he said, while integrating the sensors. Audi is one of 25 partners in a heavily funded ( 100 million Euros) brand new EU Horizon 2020 program called Ocean12 (lead by Soitec). The launch was only May 1st 2018 (so as of today it doesn't even have a website yet), and it will run for about 4 years. It is described by ECSEL (a public-private entity that puts together the big EU research projects) as an “opportunity to carry European autonomous driving further with FDSOI technology up to 12nm node”. One to watch! Airbus For Airbus, it's all about increased connectivity and communications that are trusted and secure, said company expert Olivier Notebaert. Since their chip runs are low, NRE – non-recurring engineering costs – are very important; and they need flexible systems. SOI has a long history in aerospace – in fact that's originally where it got its start, since it can handle radiation and is immune to latch-up. Notebaert says that even for Airbus, IoT is their future. The developments they pioneer will be part of it. Airbus is a partner in the EU Horizon 2020 DAHLIA project – which stands for Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic. The project is, “...developing a Very High Performance microprocessor System on Chip (SoC) based on STMicroelectonics European 28nm FDSOI technology with multi-core ARM processors for real-time applications, eFPGA for flexibility and key European IPs, enabling faster and cost-efficient development of products for multiple space application domains. The performance is expected to be 20 to 40 times the performance of the existing SoC for space.” According to another recent presentation, DAHLIA is prototyping an FPGA this year that will be in production in 2019. Sony For Sony GM Kenichi Nakano, FD-SOI has big potential for low-power products. And he should know. Sony has been an FD-SOI pioneer, using it as the basis for GPS chips that are now in a growing number of cool products, especially watches. They're getting good feedback from the market and see good opportunities across a diversified global customer base, he said. Their CXD5603, for example, is the lowest power GNSS (GPS) chip worldwide. In mass production since 2015, it is now dominating world wearable markets like trackers -- such the popular Amazfit line. Running through their various FD-SOI based GPS offerings, he noted that the GPS is a pretty simple chip. But now customers are asking for more, like for it to work in the water (where a GPS typically doesn't). So Sony has partnered with triathalon teams and are seeing good results. With success, of course, comes greater demands: for greater accuracy, for more precise positioning in motion, for increased height accuracy, for even lower power – and Sony is meeting these demands with FD-SOI, in solutions like the new CXD5602. The CXD5602 product configuration covers audio/video/communications: key factors in IoT. A camera version is releasing this summer, as are main and extension boards. An LTE module will be released at the end of 2018. And now they're using those FD-SOI chips in audio applications. You'll find it in the Xperia™ Ear Duo, he said. The MWC press release noted that Xperia Ear Duo “... is driven by Sony’s ultra-low power consuming “CXD5602” chip and a sophisticated multi-sensor platform, the “Daily Assist” feature will recognize time, location and activities to offer relevant information throughout the day – reminding you what time your next meeting is when you reach the office or narrating the latest news headlines.” Also in that PR, Hiroshi Ito,Deputy Head of Smart Product Business Group at Sony Mobile Communications, said, “Ear Duo is the first wireless headset to deliver a breakthrough Dual Listening experience – the ability to hear music and notifications simultaneously with sounds from the world around you.” The highly anticipated wireless “open-ear” stereo headset started rolling out to select markets in Spring 2018. There's a great info page with video here. https://youtu.be/1lKo9acJDPs So that's what we heard in the morning. My next post (or posts?) will cover the afternoon. That includes Dan Hutcheson's excellent talk updating his FD-SOI survey, presentations from Samsung, Globalfoundries and Simgui, plus some from very cool start-ups, and the final panel presentation.

Automakers are currently evaluating prototypes of Viper from AdaSky, a Far Infrared (FIR) thermal camera that embeds custom silicon co-designed with and manufactured by ST in 28nm FD-SOI. The complete sensing solution aims to enable autonomous vehicles to see and understand the roads and their surroundings in any condition. “With the help of ST, we have created the first high-resolution thermal camera for autonomous vehicles with minimal size, weight, and power consumption--and no moving parts. ST’s access to, and expertise in, ultra-low-power design, IP that is fully qualified for automotive applications, and 28nm FD-SOI technology have been vital to meeting the severe power constraints that would challenge our sensors’ performance,” said Amotz Kats, Vice President Hardware, AdaSky. “We’re in a position to deliver a breakthrough solution to revolutionize and disrupt the autonomous vehicle market because of ST’s mastery of automotive qualification and its strong manufacturing supply chain, which grants reliability, long-term support, and business continuity to car makers throughout the whole life of their production.” Passive infrared vision, like that in AdaSky’s Viper, when used in a fusion solution, can help close the gaps to provide accurate sight and perception without fail in dynamic lighting conditions, in direct sunlight, in the face of oncoming headlights, and in harsh weather. The new camera uses an FIR micro-bolometer sensor to detect the temperature of an object. In an ADAS solution, Viper uses proprietary algorithms based on Convolutional Neural Networks to classify obstacles and show them in a cockpit display to give the driver an early warning. This warning comes several seconds earlier than it would when using a conventional sensor in the visible wavelength and is even faster than what is possible with the human eye. The two companies say that the Far-Infrared thermal camera extends ADAS sensor fusion capability with a new layer of information, helping pave the way to fully-autonomous driving in any condition. Prototypes are now under evaluation by carmakers with initial production targeted for 2020. (Read the full press release here.)

GlobalFoundries' new ecosystem partner program, called RFwave™, aims to simplify RF design and help customers reduce time-to-market for a new era of wireless devices and networks (read the full press release here). The program aims to give designers a low-risk, cost-effective path to highly optimized solutions that leverage GF's platforms including RF on FD-SOI and RF-SOI. The target is wireless applications such as IoT across various wireless connectivity and cellular standards, standalone or transceiver integrated 5G front end modules, mmWave backhaul, automotive radar, small cell and fixed wireless and satellite broadband. As such, the RFwave™ partner program provides GF customers with IP design elements, EDA tools, design consultation and services and OSAT product packaging and test solutions. These products and services are validated, and comprise a plug-and-play catalog of design solutions. With this level of integration, GF customers can create high-performance designs while minimizing development costs. Bami Bastani, senior vice president of GF’S RF Business Unit, says, “As a leader in RF, GF’s RFwave program takes industry collaboration to a new level, enabling our customers to build differentiated, highly integrated RF-tailored solutions that are designed to accelerate the next wave of technology.” Initial members of the RFwave Partner Program are: asicNorth, Cadence, CoreHW, CWS, Keysight Technologies, Spectral Design, and WEASIC.

Following the immense success of last year's FD-SOI training day in Silicon Valley, the SOI Consortium has another one planned for the end of April this year. If you want to start learning how to leverage FD-SOI in your chip designs, this is a great place to start. Click here for information on how to sign up. ST Fellow Dr. Andreia Cathelin has put together another great line-up. World renowned professors and experts from industry will deliver a series of four training sections of 1.5 hours each, focused on energy efficient and low-power, low-voltage design techniques for analog, RF, high-speed, mmW and mixed-signal design. You'll learn about design techniques that take full advantage of the unique features of FD-SOI, including body biasing capabilities that further enhance the excellent analog/RF performances of these devices. Each section of this training day will take you through concrete design examples that illustrate new implementation techniques enabled by FD-SOI technologies at the 28nm and 22nm nodes – and beyond. The design examples will cover basic building blocks through SoC implementations. A global Q A session will close the day. Here's a little more info on how the day will unfold. Click on the slides to see them in full screen. Morning sessionsFDSOI-specific design techniques for analog, RF and mmW applications - Andreia Cathelin, Fellow, STMicroelectronics [caption id="attachment_11714" align="alignleft" width="300"] Quick preview from Andreia Cathelin's FD-SOI training session (Courtesy: STMicroelectronics, SOI Consortium)[/caption] Andreia Cathelin is ST's key design scientist for all advanced CMOS technologies, and is arguably the world's leading expert on leveraging FD-SOI in high-performance, low-power RF/AMS SoCs. Her course will first present a very short overview of the major analog and RF technology features of 28nm FDSOI technology. Then the focus moves to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits. She'll give design examples such as analog low-pass filters, inverter-based analog amplifiers and 30GHz and 60GHz Power Amplifiers, as well as mmW oscillators. There will be particular focus on the advantages of body biasing and special design techniques offering state-of-the-art performance. Circuit Design Techniques in 22nm FD-SOI for 5G 28GHz Applications - Frank Zhang, Principal Member of Technical Staff, GlobalFoundries [caption id="attachment_11716" align="alignright" width="300"] Quick preview from Frank Zhang's FD-SOI training session (Courtesy: GlobalFoundries, SOI Consortium)[/caption] Frank Zhang has designed chips using GF's 22nm FD-SOI (22FDX) process for WLAN, 5G cellular and automotive radar applications. His course will focus on how to take advantages of FD-SOI’s high-frequency performance at relatively low-current density to design high performance RF/mmWave circuits. Examples circuits include a 28GHz LNA, a 28GHz PA and an RF switch for 5G applications. The FD-SOI advantages such as low capacitance, high breakdown voltage and high-output impedance will be exploited in these design examples. This course will also discuss how to extend these techniques to applications at higher frequencies and/or higher current densities that are subject to extreme temperatures and EM requirements. Afternoon sessionsEnergy-Efficient Design in FDSOI - Bora Nikolic, Professor, UC Berkeley [caption id="attachment_11715" align="alignleft" width="300"] Quick preview from Bora Nikolić's FD-SOI training session (Courtesy: UC Berkeley, SOI Consortium)[/caption] Borivoje (“Bora”) Nikolić is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI.) If you missed it, his team's RISC-V chip was cited as one of Dr. Cathelin's “Outstanding 28nm FD-SOI Chips Taped Out Through CMP” – read more about that here. His talk at the training day will present options for energy-efficient mixed-signal and digital design in FD-SOI technologies. He'll explain how to generate body bias and use it to improve efficiency, with examples in RF and baseband building blocks, temperature sensors, data converters and voltage regulators. The techniques will be presented in the context of UC Berkeley's latest RISC-V-based SoC, designed to operate in a very wide voltage range using 28nm FD-SOI. mm-Wave and Fiber-Optics Design in FD-SOI CMOS Technologies - Sorin Voinigescu, Professor, University of Toronto [caption id="attachment_11713" align="alignright" width="300"] Quick preview from Sorin Voinigescu's FD-SOI training session (Courtesy: U. Toronto, SOI Consortium)[/caption] Sorin Voinigescu is a world renowned expert on millimeter-wave and 100+Gb/s ICs and atomic-scale semiconductor device technologies. His lecture will cover the main features of FD-SOI CMOS technology and how to efficiently use its unique features and suitable circuit topologies for mm-wave and broadband SoCs. He'll begin with an overview of the impact of the back-gate bias and temperature on the measured I-V, transconductance, fT, and fMAX characteristics. Then he'll compare the maximum available gain, MAG, of FDSOI MOSFETs with those of planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz. Next, he'll provide biasing, sizing and step-by-step design examples for VCO, doubler, switches, PA, large swing optical modulator drivers and quasi-CML circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of 20nm and 12nm FD-SOI CMOS technologies. Sign Up Now!With over 100 attendees filling every chair in the auditorium, last year's training day was sold out. Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.” 2018 will be no different – except that it's sure to sell out even faster. Please note, though, that this is not a free event, so only the attendees will get copies of the slide decks. Here's key info you need to sign up. See you there!What: SOI Consortium's FD-SOI Training DayWhen: 27 April 2018, 7:30am – 5pm.Where: Crowne Plaza San Jose, Milpitas CA (parking is free)Registration fee: US $485.00 (includes training book, breakfast, box lunch and refreshments during breaks)How to sign up: Click here to go directly to the registration site.

RF-SOI innovators Jean-Pierre Raskin of UCL and Bernard Aspar of Soitec changed the course for key RF chips. The industry has long recognized their contributions: their solution for “trap-rich” RF-SOI wafers is now the starting point to virtually every FEM in every smart phone on the planet (really!). And of course here at ASN we've been following their work for over a decade. Now more accolades are coming in. The latest is the 2017 European SEMI Award, which was given at ISS Europe 2018 for “...their seminal work with radio frequency silicon-on-insulator (RF-SOI) substrates” (read the press release here). As SEMI notes, the “...award winners’ pioneering research and collaboration with academia and industry led to major advances in RF switches and ushered RF-SOI technology from concept to worldwide adoption.” Aspar and Raskin were nominated and selected by their peers within the international semiconductor community. [caption id="attachment_11677" align="alignleft" width="150"] Bernard Aspar, Executive Vice President, Communication Power BU at Soitec Aspar founded CEA-Leti spinoff Tracit Technologies in 2003. He was appointed senior vice president of the Tracit Division (now the Communication Power business unit) when Soitec acquired Tracit in 2006. He has more than 15 years of experience in direct wafer-bonding and layer transfer. Aspar has filed more than 35 patents and co-authored some 100 scientific articles. He holds engineering and Ph.D. degrees in materials sciences and a master’s degree in microelectronics from the University of Montpellier, France.[/caption] [caption id="attachment_11678" align="alignleft" width="150"] Jean-Pierre Raskin, professor, Université catholique de Louvain (UCL) Raskin contributed to pioneering scientific studies demonstrating that silicon-based MOS technology could enable affordable, high-quality mobile devices. His findings led to the advent of RF-SOI technology and today impact the global microelectronics industry. He is an IEEE Senior Member, EuMA Associate Member and Member of the Research Center in Micro and Nanoscopic Materials and Electronic Devices of the Université catholique de Louvain, where he has been a full professor since 2007. He is author or co-author of more than 350 scientific articles.[/caption] Their advanced RF-SOI technology is now behind a wide range of applications and systems in areas including mobile devices, satellite communications, IoT, automotive radar and aerospace. If you want to better understand all this, a few years ago UCL and Soitec teams contributed an excellent article to ASN. It clearly explains how and why these new substrates came to be. You can still read it here. (Or if you're still a little confused about RF-SOI vs. RF on FD-SOI, here's a piece we did back in 2015 that explains the basics.)

China Mobile is the world's largest* telco. So when Danni Song, one of the company's high-level project managers presented at the SOI Consortium's 5th International RF-SOI Workshop in Shanghai, you can bet people listened. With each new slide, a glowing sea of cell phone cameras rose over the heads of the audience in the huge, packed ballroom. [caption id="attachment_11612" align="alignleft" width="300"] (Photo courtesy: SOI Consortium, Simgui)[/caption] Over the last month, there's been a lot more coverage of 5G in the press (especially after the recent Mobile World Congress (MWC) – check out Junko Yoshida's EETimes piece for example). For ASN readers who want to know more about 5G and RF-SOI in China, here's a reminder that Song's presentation, and many of the others given by leading companies at the RF-SOI Workshop last fall, are now posted on and freely available the Consortium website Events page. Click here for the listing and links.The theme of the workshop was IoT, mobile, 5G connectivity, and mmW. As Dr. Xi Wang, Director General of SIMIT/CAS (the Shanghai Institute of Microsystem Information Technology in the Chinese Academy of Sciences), said in his opening keynote, China is strong in RF-SOI. RF-SOI will be growing at a CAGR of over 15% for the next five years, and China has production, design, wafer manufacturing and good momentum. “We will make a great contribution to the whole IC industry,” he predicted.Of note, too, Russell Ellwanter, CEO of TowerJazz, gave what turned out to be a very inspirational keynote about Value Creation, and the importance of treating your suppliers with respect. He credits his company's close relationship with RF-SOI wafer-supplier Soitec for TJ's claim to the world's best linearity. Five of their seven fabs do RF-SOI. LNA (low-noise amplifers) are a big market driver, and with RF-SOI they can integrate the LNA with the switch.Here are some more highlights from the day – but by all means check out the presentations for details. (You can click on the illustrations to see them in full screen.)China MobileIn her presentation, Embrace a Brand New Cooperation in 5G Era, Song asked where RF-SOI could help in her wish list. Could it increase integration and decrease cost and power consumption? Can it help improve NB-IoT device performance? The supply chain needs to come back around into a circle, so that the telcos are connected to and get insights from the wafer substrate providers, she said. [caption id="attachment_11608" align="alignright" width="300"] (Courtesy: China Mobile, SOI Consortium)[/caption] China Mobile has a 5G Innovation Center, and has established test labs in 8 cities. And the government has announced a 5G launch in 2020, with pre-commercial trials now going into 20 cities. So she was at the RF-SOI Workshop as much to listen and learn as to share China Mobile's vision.Sony [caption id="attachment_11613" align="alignleft" width="300"] (Courtesy: SOI Consortium and Sony)[/caption] The presentation by Kidetoshi Kawasaki, GM of Sony Semiconductor Solutions, focused on antenna tuning, which he said is one of the fastest growing things in cell phones. Antenna Tuning Progress SOI Single Chip Integration for 4G/5G UE (note that UE = user equipment) looks at antenna aggregation, and why it is important for carrier aggregation (CA) and MIMO. Sony has developed an SOI-based next-gen process for 5G integrating passive components. That's why RF-SOI is important and will be continued to be used in the mobile market, he said.GlobalFoundriesGF has developed demo vehicles to help customers, said Sr. Director of the RF Business Unit, Peter Rabbeni. (Over the years they've shipped over 32 billion RF-SOI devices, btw.) In his presentation, RF-SOI: Delivering Performance Integration for the Next Generation of Mobile,he noted that RF is becoming more complex than digital. As a result there is a need to integrate to help reduce cost: this is a direct correlation to the standards that are driving complexity. At the same time, performance requirements are increasing, so the challenge is driving increased performance at the same or lower cost than previous generations of products. [caption id="attachment_11609" align="alignright" width="300"] (Courtesy: GlobalFoundries and SOI Consortium)[/caption] To meet 4G/LTE and 5G's evolving performance demands, GF has recently introduced two new RF-SOI platforms, which he detailed in the presentation. 8SW enables increased integration of front-end modules (FEMs), while 45RFSOI is for mmWave FEMs. (In a separate presentation, IDDO-IC CEO Denis Masliah presented a Differential Complementary Millimeter Wave Power Amplifier for 5G using 45RFSOI process, which is currently being fabbed by GF.)RF-SOI Wafer SuppliersThe two leading RF-SOI wafer suppliers, Soitec and partner Simgui, both gave excellent presentations. Though Soitec EVP Bernard Aspar's presentation Engineered Substrates as Foundation of Innovation in RF is not posted, he made some important points. Up til now, RF-SOI has mainly been about switches and tuners, he said, but there are other opportunities that offer the potential for huge growth. The full supply chain needs to be prepared, he said, and suppliers need to understand each other. Each technology requires the right substrate – and even as we move into sub-6GHz 5G, there is still work to be done in 4G. In fact Soitec is now offering services to help customers better understand new substrate options. [caption id="attachment_11611" align="alignright" width="300"] (Courtesy: Simgui, SOI Consortium)[/caption] Soitec's partner in China, Simgui, now uses Soitec's Smart CutTM technology for RF-SOI wafer production. Together the two are now producing over a million 200mm RF-SOI wafers/year, said Simgui Sr. Director, Kerui Wang. His presentation, RF-SOI – a Secured Substrate Supply Chain, looked at their strategic partnership with Soitec, wherein they use the same tools and processes to deliver the same products meeting the same specs.Fabs and FablessTwo leading fabless companies – RDA Microelectronics (which was acquired by Spreadtrum) and SmarterMicro also presented their RF-SOI activities. Although their ppts are not posted, here are a few highlights.Longtime ASN readers will recall that RDA has been shipping high-volume, RF-SOI based chips to Samsung and others for over five years. In the presentation, RF-SOI in Current and Future RFFE Solutions, Engineering AVP Joseph Jia said that over last two years alone they've released almost 50 RFFE (front end) chips on RF-SOI. They see RF-SOI as the right match for switches, tuners and NB-IoT because of the low-voltage and tunability advantages.SmarterMicro's CTO, Peter Li, sees RF-SOI as a cornerstone of 5G. In his presentation, Reconfigurable RFFE in 5G, he said the goal is smart systems on fewer dies to decrease size and cost.Jeff Zhu, assistant director at SMIC, presented SMIC, 0.13um RF-SOI Platform Updates. Mainland China's largest foundry has recently moved its RF-SOI process from 180 to 130um, and he walked us through some chip designs.Throughout the day, presenters noted that RF is a great opportunity for China to take a leadership position. As one panelist at the end of the day noted, RF depends more on expertise and talent than digital, which depends more on manpower.Nanjing: A China RF CapitalJust before the Shanghai events, there was a 2-day event sponsored by the City of Nanjing, co-organized by SOI Industry Consortium and the City of Nanjing. Over 200 participants attended the workshop and tutorials on SOI applications, SoC development and manufacturing, EDA IP ecosystem, as well as a design tutorial for More than Moore SOI ecosystem. Almost all of those presentations are now posted on the Consortium – click here to get them.Some of the participants in the SOI Consortium's delegation also had the opportunity to visit the enormous Nanjing Sofware Park. Nanjing, we learned, is often considered China's “RF capital”. The list of the world's major RF players working in partnership there is certainly an international who's who.So, lots of good RF-SOI/5G info on the SOI Consortium website – check it out!~ ~ ~*in terms of market value and subscribers.

ST Fellow Dr. Andreia Cathelin gave a terrific presentation at the recent CMP Annual Meeting. Now posted and freely available, Performance of Recent Outstanding 28nm FD-SOI Circuits Taped Out Through CMP highlighted eight examples – though she told ASN that she had easily over 50 from which to choose.CMP is a Multi-Project Wafer (MPW) service organization in ICs, Photonic ICs and MEMS. They’ve been organizing prototyping and low volume production in cooperation with foundries for over 37 years. In partnership with ST since 1994, in the fall of 2012 they opened access to MPW runs in the 28nm FD-SOI process. More than 180 tape-outs have been fabricated since then using the process.As Dr. Cathelin said, this lets ST show their industrial clients just how good the technology is. The chips she chose to cover in her presentation get “spectacular performance”, she said, especially for low-power or power-sensitive SoCs.Here’s a quick recap of what she presented (some of which she co-authored), followed by some other SOI-related updates from the CMP meeting.8 (of Many) Great ChipsFD-SOI, said Dr. Cathelin, “...is unmatched for cost-sensitive markets requiring digital and Mixed Signal SoC integration and performance.” In the first dozen slides of her presentation, she gave the technical details on the advantages of FD-SOI in analog, RF/millimeter wave, Analog/Mixed-Signal and digital design. If you're a designer, you'll want to check those out.Then she ran through eight great chips – all manufactured by ST on 28nm FD-SOI through CMP's MPW services. Here they are. (You can click on the illustrations to see them in full screen.)1. A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI [caption id="attachment_11559" align="alignnone" width="768"] (Courtesy: CMP, ST, ISEN)[/caption] This chip was presented at ESSCIRC '16 by a team from ISEN Lille, Professors Andreas Kaiser and Antoine Frappé (you can get the complete paper by I.Sourikopoulos et al on IEEE Xplore – click here.) As noted in the abstract, “Delay controllability has always been the major concern for the reliable implementation of circuits whose purpose is timing.” By leveraging body biasing in FD-SOI, this novel low-power design architecture for 60GHz receivers enables very high bandwidth together with fine-grain wide range delay flexibility, for implementing Delay Feedback Equalizer techniques in the Intermediate Frequency (IF) reception path. The results are state-of-the-art: ultra wide range, linear control, fs/mV sensitivity and energy efficient controllable delay cells. 2. 28FD-SOI Distributed Oscillator at 134 GHz and 202GHz [caption id="attachment_11560" align="alignnone" width="768"] (Courtesy: CMP, ST, ims)[/caption] Presented at RFIC '17 by a team from the IMS Bordeaux lab, Professor Yann Deval and STMicroelectronics, this chip demonstrates the highest oscillation frequency attainable so far at the 28nm node, be it planar bulk or FD-SOI. (Click here to get the full paper by R. Guillaume et al from IEEE Xplore.) As noted in the abstract, solutions on silicon for mmW and sub-mmW applications have been demonstrated for high-speed wireless communications, compact medical and security imaging. The main challenges are for the signal generation at high frequencies, and this implementation demonstrates spectacular oscillation frequencies close to the transistor’s transition frequency (fT). In this chip, they used body bias tuning to optimize the phase noise, demonstrated very low on-wafer variability, and simulation methods that permit measurement prediction precision within 0.1%.3. A 128 kb Single-Bitline 8.4 fJ/bit 90MHz at 0.3V 7T Sense-Amplifier-less SRAM in 28nm FD-SOI [caption id="attachment_11561" align="alignnone" width="768"] (Courtesy: CMP, ST, Lund U.)[/caption] Extremely energy efficient SoCs are key for the IoT era – but SRAM gets very tricky at ultra-low voltages (ULV). Presented at ESSCIRC '16 by B. Mohammadi et al (on IEEE Xplore here) from Professor Joachim Rodrigues' team at the Lund University, this is a 128 kb ULV SRAM, based on a 7T bitcell. The minimum operating voltage VMIN is measured as just 240mV and the retention voltage is as low as 200mV. FD-SOI enabled them to overcome ULV performance and reliability challenges by letting the Lund U.-lead team selectively overdrive the bitline and wordline with a new single-cycle charge-pump. Plus they came up with a new scheme so it doesn't need a sense amplifier, yet delivered 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access.4. Matched Ultrasound Receiver in 28FDSOI [caption id="attachment_11562" align="alignnone" width="768"] (Courtesy: CMP, ST, Stanford U.)[/caption] Presented at ISSCC '17 (with an extended relative paper at JSSC '17) by M-C Chen et al with Professor Boris Murmann's team at Stanford, the full title of the paper about this chip is A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI. (Click here to get it on IEEE Xplore.) It's a a proof-of-concept for a big ultrasound receiver: a “pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging.” PA is “...an emerging medical imaging modality based on optical excitation and acoustic detection.” It's used in studying cancer progression in clinical research, for example. As noted in the paper abstract, “The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation.” One of the (many) advantages of FD-SOI in this context is for front-end signal conditioning in each pixel. This unique type of pixel pitch-matched architecture implementation is possible only in a 28nm (or less) node of an FD-SOI technology, as it is matched with the pitch sizing needed for the ultrasound transducers in order to generate signals for a 3-D reading.5. SleepTalker - 28nm FDSOI ULV WSN Transmitter: RF-mixed signal-digital SoC [caption id="attachment_11563" align="alignnone" width="768"] (Courtesy: CMP, ST, UCL)[/caption] Presented at VLSI '16 and JSSC '17 by G. de Streel et al from Professor David Bol’s team at Université Catholique de Louvain la Neuve, the full title of the paper about this chip is SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping (get it on IEEE Xplore here). This chip tackles the IoT requirement for sensing functions that can operate in the ULV context. That means creating wireless sensor nodes (WSN) that can be powered on an energy harvesting power budget – and that's a real challenge if you want to incorporate an RF component that can handle medium data rates (5-30 Mb/s) for vision or large distributed WSN networks. The energy efficiency has to be better than 100 pJ/b. To get there, the UCL-lead team used wide-range on-chip adaptive forward back biasing for “...threshold voltage reduction, PVT compensation, and tuning of both the carrier frequency and the output power. [...] Operated at 0.55 V, it achieves a record energy efficiency of 14 pJ/b for the transmitter (TX) alone and 24 pJ/b for the complete SoC with embedded power management. The TX SoC occupies a core area of 0.93 mm2.”6. A 128x8 Massive MIMO Precoder-Detector in 28FDSOI [caption id="attachment_11564" align="alignnone" width="768"] (Courtesy: CMP, ST, Lund U.)[/caption] This massive MIMO chip was presented at ISSCC '17 by a team from Professors Liang Liu and Ove Edforss at the Lund University in a paper entitled 3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI (H. Prabhu, et al; get it from IEEEE Xplore here). While Massive MIMO (MaMi) will be needed for next-gen communications, it can't be achieved by just scaling MIMO – that would be too costly in terms of flexibility, area and power. As noted in the Lund U. team's intro, “Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.”7. ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI [caption id="attachment_11565" align="alignnone" width="768"] (Courtesy: CMP, ST, KU Leuven)[/caption] Today's solutions for always-on visual recognition apps are an order of magnitude too power hungry for wearables. Running at 10's to several 1OO's of GOPS/W, they use classification algorithms called ConvNets, or Convolutional Neural Networks (CNN). The paper about this chip was presented at ISSCC '17 by a team from professor Marian Verhelst at Katoliek Universiteit Leuven (B. Moons, et al, get it from IEEE Xplore here), and it changes everything. Leveraging FD-SOI and body-biasing, the KU Leuven team solved the power challenge with, “...the concept of hierarchical recognition processing, combined with the Envision platform: an energy-scalable ConvNet processor achieving efficiencies up to 10TOPS/W, while maintaining recognition rate and throughput. Envision hereby enables always-on visual recognition in wearable devices.”8. Fine-Grained AVS in 28nm FDSOI Processor SoC [caption id="attachment_11566" align="alignnone" width="768"] (Courtesy: CMP, ST, UC Berkeley)[/caption] As we learned at SOI Consortium FD-SOI Tutorial Day in SiValley last year, Professor Borivoje “Bora” Nikolic of UC Berkeley is known as one of the world's top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI!) They presented the RISC-V chip here at ESSCIRC '16 and JSSC '17, in a paper entitled Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC (B.Keller, et al, on IEEE Xplore here). As they noted in the intro, a major challenge for mobile and IoT devices is that their workloads are highly variable, but they operate under very tight power budgets. If you apply adaptive voltage scaling (AVS), you can improve energy efficiency by scaling the voltage to match the workload. But in the current gen of SoCs, the AVS timescales of hundreds of microseconds is too slow. The chip the Berkeley team presented brought that down to sub-microseconds by aggressively applying body-biasing throughout the chip, including to workload measurement circuits and integrated power management units. The result is “... extremely fine-grained ( 1μs) adaptive voltage scaling for mobile devices.” (BTW, they expand on some of the details in another paper published in 2017.) These design techniques are now taught at UC Berkeley, as this kind of implementation is the subject of a course in SoC design (including the RF part of transceivers); a first educational chip has already been taped-out and successfully measured. (BTW, Professor Nikolic will once again join Dr. Cathelin and other luminaries in teaching at the SOI Consortium's FD-SOI Training Day in Silicon Valley, 27 April 2018 - click here for sign-up information.)More SOI Through CMPAt the meeting, CMP also made a presentation on all their MPW offerings – you can get it here. On ST's SOI (in addition to 28nm FD-SOI, of course), that includes the new 160nm SOIBCD8s: Bipolar-CMOS-DMOS Smart Power (for automotive sensor interface ICs, 3D ultrasound, MEMS micro-mirror drivers); and 130nm H9-SOI-FEM: Front-End Module (for radio receiver/transceiver, cellular, WiFi, and automotive keyless systems).CMP also provides tutorials that are used by institutions across the globe. A new update to the tutorial, RTL to GDS Digital Design Flow in 28nm FD-SOI Process is now available – you can see the presentation they did about that here. (It now includes LVS and DRC steps with Mentor/Calibre or Cadence/PVS.) Other services, like the 2-day, hands-on THINGS2DO FD-SOI training days at the end of March are always fully booked almost immediately, but don't hesitate to inquire, as they'll be adding more. For some more examples of 28nm FD-SOI chips run through CMP over the years, see their website pages on Examples of Manufactured ICs. There are also some nice examples on pages 21 and 23 of their most recent annual report. For those in the photonics world, CMP has teamed up with Leti to offer Si-310 PHMP2M, a 200mm CMOS SOI platform. CMP is cooperating with Tyndall for the photonics packaging – see that presentation here. Training kits and tutorials will be available in Q3 of this year. And in partnership with MEMSCAP, CMP offers Multi-User MEMS Processes (aka MUMPs) for SOI-MEMS.So lots of terrific SOI resources for CMP – check it out!~ ~ ~Note: special thanks to Andreia Cathelin of ST and Kholdoun Torki of CMP for their help on this piece.

They've got initial silicon of Dream Chips' ADAS SoC fabbed in GlobalFoundries' 22FDX (FD-SOI) technology, and it's got record power efficiency (read the full press release here). The chip offers high performance image acquisition and processing capabilities and supports AI / Neural Network (NN) vision operation with a total of 1 TOPS at 500 MHz on 4 parallel engines. With all functions including quad-core Arm® Cortex®-A53, Tensilica DSPs, and INVECAS’ LPDDR4-Interfaces activated, the SoC shows single digit power dissipation without the need for forced cooling, which is of significant importance for embedding in automotive environments. [caption id="attachment_11538" align="alignleft" width="277"] Courtesy: Dream Chips Technologies[/caption] Targeting automotive computer vision applications, the SoC was created in close cooperation with Arm, ArterisIP, Cadence, GF, and INVECAS as part of the European Commission’s ENIAC THINGS2DO reference development platform, where about 40 partners in Europe cooperated to propel the FDSOI-Design Ecosystem. Of particular importance is the new and reduced power footprint of this SoC in 22FDX-technology from GF. AI/NN-operation for image recognition is available today, but most of the solutions need active cooling. Implementation of Dream Chip Technologies’ SoC on GF’s 22FDX platform demonstrated single digit Watt and cooling targets for designers managing power dissipation. If needed, the SoC bears the potential to increase the performance even further up to 2 TOPS at 1.0 GHz by applying GLOBALFOUNDRIES’s forward body-bias capabilities and other optimization techniques. The jointly developed ADAS SoC platform from Dream Chip Technologies is available now. Part of GF’s FDXcelerator™ Partner Program, Dream Chip is the largest independent German Design Service company specialized in the development of large ASICs, FPGAs, embedded software and systems with a strong application focus on automotive vision systems (ADAS).