A Communication ProblemAs the industry ventures towards a more connected world, the semiconductor test community is facing increasingly stringent performance, quality and reliability targets, particularly in the high-stakes automotive, communications, and medical sectors. It is, therefore, important for device makers to know how their components will perform before their products hit the road, reach for the skies, or get placed inside the body. Access to test data is critical to mitigating failure risks. Yet many challenges are associated with accessing test and manufacturing data. One hurdle is that component suppliers are often reluctant to provide test data for fear of revealing sensitive information about their design and/or manufacturing IP. With customers sourcing their components from multiple vendors, IP leakage is a valid concern and, consequently, a barrier to access. Certainly, these issues can be negotiated contractually, but only after striking the delicate balance between access and cost. Beyond access, the quality of test data itself – which can be fragmented and even corrupted – is not always assured. As a device moves through the typical product flow (i.e., fab to sort to assembly to test), it inevitably changes hands (e.g., from foundry to OSATs). As a result, information about the device can become a patchwork of data where formats vary and certain fields, at times, may get overwritten. These potential gaps in test data flow underscore the need for consistent communications of manufacturing information from one process or stakeholder to the next. While standardization could help, it is currently lacking in many of these critical data-flow chains in the manufacturing, test, and assembly areas. An Industry Alliance Aimed at Solving Test Industry ProblemsEfforts to establish standardized solutions to these test industry issues are under way by the SEMI Collaborative Alliance for Semiconductor Test (CAST) Special Interest Group. CAST activities are currently structured around establishing standards on data formats, communication protocols, and chip traceability.Rich Interactive Test Database (RITdb)While Standard Test Data Format (STDF) is widely used in the semiconductor industry, it does not directly support the new use models in today’s test environment, such as real-time or pseudo real-time queries, adaptive test and streaming access. The STDF V4 record format is not extendible and, because the standard itself can be imprecise, it tends to result in many interpretations. These limitations become apparent when there is a need for more efficient and flexible format to manage “big test data.”The RITdb group has been working on the next-generation format following STDF to allow more flexibility in data types and support for adaptive test. The group aims to provide a standards-driven data environment for semiconductor test including simple standards-based data capture, transport and relationship model for eTest, probe, and final test data. Its work also seeks to support equipment configuration management and operational performance data. More importantly, RITdb enables a real-time streaming model that provides the ability to collect and monitor data/systems from sand to landfill.Real Time Adaptive Test (Courtesy HIR)Work by the RITdb group will ultimately be developed into SEMI Standards. The SEMI Standard spec will be in MS Word while the database itself in a different format. A spec editor will help ensure it is used correctly. The group also plans to expand the spec beyond probe and final test. Meanwhile, the group is working to streamline RITdb and implement different extensions (e.g., tester log, streaming). Additional work will be needed on probe maps and test cases (i.e., be able to run verifiers to validate the spec).Tester Event Messaging for Semiconductors (TEMS)Today, semiconductor testing continues to see a surging demand for real-time data analysis, real-time ATE input and control of the test flow to improve test yield, throughput, efficiency, and product quality. At the same time, test equipment and test operations around the world use a diverse range of data formats, specifications, and interface requirements that drive up customer service and application engineering costs for ATE vendors, OSAT companies, IDM test operations, software providers, and handler equipment. A common ATE hardware and software communications interface would help reduce the cost, time and complexity of integrating ATE equipment into data-intensive test operations.Overview of Test Cell CommunicationThe TEMS group was chartered to develop a standardized ATE data messaging system based on industry-standard internet communication protocols between a test cell host and a server. The standard will be limited to ATE data messaging, using RITdb entity types as applicable, standard data format, and control requirements. It will have no impact on other test communication interfaces such as those involving handlers, probers, test instrumentation, and other systems covered by existing standards (e.g., SEMI E30, E4, E5, STDF). The group is developing a set of standards to define a vendor-neutral way to collect test cell data. The primary spec defines the model while a subordinate spec defines the transport layer to maintain consistency with prior standards.Chip ID TraceabilityChip ID Traceability is the most recent group formed under CAST. The group’s formation came on the heels of the 2017 CAST Workshop that focused on Component System Level Test. SLT is widely considered a burden that most chip manufacturers prefer to avoid, but it is essential to achieving lower DPPM (Defective Parts Per Million) goals at system level. The cost to develop and maintain SLT equipment in-house and at OSATS is significant. SLT test engineering requires different skills than regular ATE test engineering. The engineers must understand the final application environment and the data flow that is subjected to the component. Defect causes need to be isolated and communicated back to the vendor or ATE test engineer for corrective action. Mapping such SLT failures back to the ATE production tests is a big, labor-intensive challenge.Component traceability is a big concern. Most newer technologies have ECID (Electronic Chip Identification). However, many product types representing significant volumes do not provide ID traceability. Without component-level traceability, it is extremely difficult to analyze failures and drive corrective action. Additionally, there is basic manufacturing data, including chip ID, that is needed across the supply chain, but this is often blocked and difficult to obtain from suppliers. Such data analysis is difficult across "silos" due to sharing/security barriers. Die-level Identification Traceability (I T) ModelThe Chip ID Traceability group was chartered to develop a standardized approach for enabling traceable die-level identification (ID) throughout the IC manufacturing, test, and assembly processes to the point of use in the final system. The approach defines the use of a simple, unique identifier that IC suppliers and board-level manufacturers can use to communicate about a specific device for the purposes of performance or failure analysis. The identifier will enable suppliers and customers to communicate specific component information and, with NDAs (non-disclosure agreements) in place, send manufacturing data back and forward through the supply chain for data analysis. The group is developing a standardized model focusing on key concepts, behaviors, and requirements for enabling die ID and traceability. The model defines minimum chip ID and traceability for new design and manufacturing implementation as well as for backwards compatibility with existing methods. The resulting standard would apply to different chip configurations ranging from single integrated circuits to multi-chip/3D structures. It can be adapted for use with a range of technologies, ranging from legacy systems to the latest in electronic chip identification (ECID). A copy of the draft proposal can be downloaded here. The Chip ID Traceability group is soliciting feedback to the document. Please contact Paul Trio at SEMI ([email protected]).

Since 2010, 474 companies worldwide have poured $51 billion into developing artificial intelligence (AI) devices, with the bulk of these investments targeting autonomous driving and in-vehicle experiences, according to a McKinsey Company report. With the extraordinary growth potential of AI and automotive electronics, it’s no surprise that IHS Market predicts the Advance Driver Assistance Systems (ADAS) market will reach $67.43 billion by 2025. By 2040, the market research firm expects 33 million autonomous vehicles enabled by AI to be on the road worldwide. Lured by the immense business opportunity, more semiconductor manufacturers are jumping into the automotive market knowing that autonomous driving ICs will face far more stringent reliability requirements than traditional devices. Testing, then, will be crucial for level 5 autonomous driving to materialize since a fully autonomous system will need to rival the behind-the-wheel performance of a human driver even in extreme road conditions like snow and iceWith testing vital to the development of chips for autonomous driving, SEMI Taiwan recently convened experts from IC design and testing-related fields to facilitate cross-discipline collaboration and help inspire innovative solutions to current testing challenges. The early February AI IC and Automotive IC Test Seminar is part of a series of SEMI Taiwan events focused on hot topics including like AI, IoT, smart automotive, smart data and smart MedTech. Following are a key takeaways from the seminar.Paradigm Shift Needed in Automotive Electronics Testing StrategiesDesigners of automotive electronics need to transform their test strategies to match the technical rigors of autonomous driving. The traditional process of build, test, and then fix-for-compliance must change in the era of self-driving vehicles. Adding AI to already electronically complex automotive systems will dramatically increase the number of ICs and sensors in vehicles. Traditional component testing for points of failure is far less rigorous than vetting devices under the countless driving scenarios where they could fail. Testing, therefore, must be holistic. Starting in the development phase of their own electronics systems, automotive electronics designers must work closely with component and other technology suppliers to ensure that designs are tightly integrated and exhaustively tested for interoperability and points of failure under any conditions a human driver would face. Wafer-level Test is A TrendThe cost and time for IC testing have steadily increased to meet the relentless scaling requirements of highly integrated advanced technologies, placing immense pressure on current wafer-level packaging and testing methodologies to maintain cost efficiencies, chip yields and time-to-market speed. The challenges will intensify with the multiple-component parallel testing required for autonomous vehicles. Demands on automotive electronics manufacturers to maintain DDPM quality levels key to smart functionalities, powertrain operation, safety and reliability will also complicate current IC testing methodologies. Nearly 300 professionals from IC design and related fields gathered at the SEMI Taiwan forum to tackle the challenges of autonomous vehicle testing Beyond TechnologyTo fulfill the promise of autonomous automobiles and other AI applications, industry, academia, and government in Taiwan must work together to solve underlying technical challenges, create profitable business models and develop a strong programming and system integration workforce. Taiwan's strong semiconductor manufacturing industry and advanced IC testing capabilities put it in the pole position to help drive the development of advanced automotive electronics essential for autonomous vehicles.Emmy Yi is a senior marketing specialist at SEMI Taiwan.

With less than one week before ISS Europe 2018, 4-6 March in Dublin, Ireland, industry growth is on the minds of the leading industry analysts, researchers, economists and technologists who will come together for critical insights into the forces shaping the electronics manufacturing supply chain.The three-day flagship business conference will feature a panel discussion on the role of Europe in the global electronics manufacturing supply chain and related business and technology trends. The Day 2 panel discussion will home in on critical strategies for growing Europe across the supply chain and elevating the region’s influence in Artificial Intelligence (AI) and other potential enablers of European competitiveness and technology leadership.SEMI Europe caught up with two industry leaders presenting at ISS Europe 2018 for their insights on technology and talent – two pillars of future industry expansion.Google: AI, Machine Learning and Ethical SolutionsDavid Sneddon, Director of Large Customer Sales for Central EuropeSEMI: As a Director of Large Customer Sales for Central Europe what is your primary focus? Sneddon: Right now my focus is mainly on advertising and marketing sales. For instance, I look after the advertising reviews for Google and YouTube for the DACH/CEE region. Our team offers both digital marketing advice as well as advice on logistics, translation of advertising and web assets, localisation of web/app assets and payment solutions.SEMI: What do you think are going to be the main challenges for the industry in the next two years?Sneddon: I think our industry will face two main challenges. For the technology industry as a whole, and in particular for the advertising sector, the first challenge will be to recognize the perception of the growing power of technology. Google, Facebook, and other big players should work closely with governments and regulatory officers in order to build trust. This is gaining importance within today’s users and leaders should commit to building trust. A second challenge is related to the growing importance of big data, AI and machine learning: industry players should be able to develop useful technologies but, most of all, ethical solutions.SEMI: Industry wide, what work/technology/trend has excited you this year? Sneddon: Innovations in machine learning and AI show how much machines can do to improve our daily life. Think about how Google Translate has developed. The first version was not so accurate but since the introduction of Google Neural Machine Translation system (GNMT), which takes advantage of deep neural networks, translations and sound are more accurate. If 2017 was huge for advancements in artificial intelligence and machine learning, 2018 may deliver even more. SEMI: What do you expect from ISS Europe strategic discussions and why would you recommend attending the event? Sneddon: I am attending SEMI ISS Europe for the first time and expect to hear peers’ high-level debates on the future of the industry, to be inspired and contribute myself. Top industry players should attend this event to stimulate the exchange of strategic discussions around innovation and technology. The key message that we, as leaders of this exciting industry, should deliver refers to the ethical aspects I have mentioned before. It is up to us to be prosperous and ethical at the same time and deliver positive messages for the year ahead. CEI-Europe AB: Smart Training for Smarter EngineersAnn-Charlotte Johannesson, CEOSEMI: As a CEO for CEI-Europe what is your primary focus?Johannesson: At the moment, my main focus is to refresh our approach in e-learning. CEI-Europe has organised classroom courses since 1980. We see now that there is a major need for e-learning courses and digital platform, so this is what I have been doing recently. Very soon a new website with a refreshed look and feel will be available.SEMI: What do you think are going to be the main challenges for the industry in the next decade?Johannesson: The industry must keep employees educated to keep them motivated and happy. As we all know, there is a lack of engineers in Europe. Fewer people are doing more work and, as a result, there is less time to stay on track with innovations, updates and trends. The investment in learning is happening but it is not enough. The industry’s main challenges will be: How do I train my team? How do I attract new people? Traveling to attend courses might be expensive and time-consuming, but a good alternative is to set targets for the training, learn what your company needs and offer individualized solutions. This is the way to prosper and stimulate people working in a fast-growing industry.SEMI: In what ways do you think the industry can change for the better?Johannesson: When it comes to education, it’s important for businesses to see it as an investment, not merely a cost. Think about the future, and invest in the future.SEMI: What do you expect from ISS Europe strategic discussions and why would you recommend attending the event?Johannesson: I’ve collaborated with SEMI a long time and am excited about presenting our perspectives for the future. I expect to meet and network with key leaders and discuss the main challenges for Europe and how to overcome those. How do we train smarter engineers? See you in Dublin!The combination of insightful presentations and unparalleled networking opportunities amongst senior industry leaders at ISS Europe promises to help stimulate ideas and strategies to take advantage of the opportunities that are rapidly developing in our industry.For full program details, please visit the ISS Europe 2018 agenda page online. To register, please visit: www.semi.org/eu/iss-europe-2018-registration

Foreign investment, which fuels technological innovation, productivity, and broad-based growth, is critical to the semiconductor industry’s long-term success. That stream of billions of dollars in investment, however, is at risk of narrowing as a result of the industry’s growing scrutiny by the Committee on Foreign Investment in the United States (CFIUS).Over the last two years, CFIUS, a government body formed to review sales and transfer of ownership of U.S. companies to foreign entities, has denied sales of Aixtron and Lattice Semiconductor to Chinese investors because of national security concerns. More recently, CFIUS rejected the sale of Xcerra to a Chinese company, and the Committee has reportedly become involved in Broadcom’s bid to take over Qualcomm.As highlighted recently, the Foreign Investment Risk Review Modernization Act (FIRRMA) was introduced by Sen. John Cornyn (R-TX) and Rep. Robert Pittenger (R-NC) in November to reform CFIUS, whose form and function have remained unchanged for over a decade. In the spirit of more effective governance that matches global trends, we welcome efforts to ensure that CFIUS better balances global commerce and national security. FIRRMA contains important reforms to drive new efficiencies within CFIUS to help alleviate its rising workload, including devoting badly needed resources to the committee. Among those reforms is the codification of regulations to ensure that a Senate-confirmed appointee with direct responsibility for investment reviews is installed in each CFIUS agency. Notably, however, FIRRMA fails to adequately address several existing problems with CFIUS and, in some cases, creates new ones. First, this legislation dramatically expands CFIUS’s authority, including allowing it to review any non-passive investment by a foreign investor in a U.S. critical technology or critical infrastructure company, even if the investor does not have control over the company. By defining businesses as a critical technology or critical infrastructure company, FIRRMA would subject companies, and not transactions, to review. This means that transactions from a critical technology company that involve non-critical technologies would be subject to unnecessary, time-consuming, and costly CFIUS review. Second, FIRRMA would require the committee to review joint ventures or any other common arrangements that involve sharing intellectual property with a non-U.S. partner. As a result, CFIUS, for the first time ever, would be charged with reviewing outbound international commercial activity. We believe that this is a serious flaw in the bill that would only duplicate the existing U.S. export control regime while adding another layer of regulatory burden. Third, FIRRMA would create different tracks for CFIUS scrutiny based on the origin of the investors. Countries of special concern, like China or Russia, would be subject to enhanced review while other countries with an approved CFIUS-like body, or that have a defense treaty with the United States, would be fully exempt from CFIUS review. This inherent bias seems to challenge the central tenet of U.S. investment policy – non-discrimination. Lastly, FIRRMA establishes provisions for expanded consultation and information sharing with allies. These provisions could lead, even if unintentionally, to needlessly divulging proprietary information and technology. Over the past year, there’s been greater focus on the stronger enforcement on foreign commerce and the protection of U.S. industries. FIRRMA fits squarely in this area. However, instead of creating sweeping barriers with economy-wide implications, a better approach would be to have higher fences around select items. This would help maintain the current investment stream that is vital nourishment for the semiconductor industry and the broader economy while also protecting national security. SEMI will continue working to open new markets while reducing the regulatory burden that can stifle cross-border trade and commerce. In addition, SEMI will continue to educate policymakers on the critical importance of unobstructed trade and investment in advancing semiconductors and the emerging technologies they enable. If you are interested in more information on foreign investment, CFIUS, or FIRRMA, or in how to be involved in SEMI’s public policy program, please contact Jay Chittooran, Manager, Public Policy, at [email protected].

The White House has released its fiscal year (FY) 2019 budget proposal just as Congress secured a two-year budget deal that will begin the process of wrapping up the rest of FY 2018 and set the government’s top line spending for FY 2019 as well. Included in both of these plans are funding levels for government agencies that are crucial to the basic research underpinning many of the building blocks for future innovation in the semiconductor industry. Funding for the National Science Foundation (NSF) and the National Institutes for Standards and Technology (NIST) are two of the biggest drivers for basic research in the U.S. government, with many other smaller agencies playing a role as well.In a bipartisan compromise, Congressional leaders agreed to a deal that would lift their self-imposed spending caps for FY 2018 and pump an additional $68 billion into non-defense discretionary spending for FY 2019. They now have until March 23 to approve a detailed spending plan for the rest of this fiscal year before moving on to complete the FY 2019 plan by the end of September. While the final spending levels for individual agencies have yet to be finalized for FY 2018, the additional funding bodes well for both NSF and NIST, which had seen cuts of between 2 percent and 9 percent in earlier drafts of spending bills.Meanwhile, the president’s FY 2019 budget plans to flat fund NSF for the next year, while making cuts to NIST of over 30 percent. Included in these cost reductions are proposals to eliminate the popular Hollings Manufacturing Extension Partnership, which provides assistance to small and medium-size manufacturers throughout the U.S. With the program providing funds to states with up to a 50 percent match, its elimination will face strong opposition from both parties in Congress. The president’s budget cuts also target the popular Advanced Research Projects Agency for Energy (ARPA-E) for elimination. Disbanding the agency would end multiple streams of funding for innovations in energy production and storage.While it is the responsibility of the president to submit his budget for the funding of the federal government, the power of the purse resides with Congress. The process of federal funding has been drawn out more than usual this year, with a short-term government shutdown even playing a small role. With the budget agreement now in place, the rest of the funding for FY 2018 should come by the upcoming deadline, with hopes that Congress can then quickly pivot to FY 2019. With the midterm elections coming in November, however, political implications will play an outsized roll in the process for the remainder of the year. SEMI strongly advocates for the position that funding of basic research is closely linked with our nation’s economic prosperity in the modern global economy. Effective research funding as a national priority should be bipartisan and must be backed up by a strong and united community of stakeholders and advocates in the business, research, and education communities. In addition, this funding must not only be robust but consistent and not subjected to the uncertainty of short-term stop gap budget measures. If you’d like to learn more about SEMI’s public policy program, please contact Jamie Girard at [email protected].

FD-SOI has hit Q1 with terrific momentum, both in terms of visibility into products and in press coverage. In case you missed them, here are three articles you should definitely read: FD-SOI Adoption Expands – Technology shifts direction after years of competing directly with CMOS at advanced nodes (by Ed Sperling at Semiconductor Engineering) 22FDX Shows IoT Traction at MWC 2018 (by David Lammers for GF's Foundry Files) The Future of Silicon: An Exclusive Interview with Dr. Gary Patton, CTO of GlobalFoundries (by Ian Cutress at AnandTech) But, if you don't have time to read them all right away, here are some highlights to tide you over til you do. Expanding Adoption Ed Sperling at SemiEngineering sees FD-SOI adoption “... gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs.” After recounting the advantages (with which ASN readers are well familiar), he notes that two things have changed in our industry. First, fewer and fewer companies can afford to design in the most advanced FinFET nodes. And second: there are enough emerging markets where power is critical, but there won't necessarily be the billions of units per chip needed to amortize exorbitant design costs. In particular, for FD-SOI adoption he cites, “...the inferencing stage of machine learning [note: that happens in “edge” devices], base-stations, IoT and IIoT, bitcoin mining, 5G, radar, and a variety of automotive applications.” (GF's Jamie Schaeffer makes the technical case in the article for NB-IoT and automotive if you want more info.) ST's Giorgio Cesana makes an interesting point about body biasing (that I hadn't hear before) re: uni-direction vs. bi-directional. Currently, he explains, body biasing is uni-directional – although you can use it now in such a way that is effectively bi-directional. However, after the 22nm node, it will become truly bi-directional, which will enable wider swings for power savings. (For those concerned about pre-mature chip aging, see the full article for explanations by experts from Soitec who explain why that's not a problem after all.) Cesana also points out that the kind of chips leveraging FD-SOI are not the kind of chips that will need to move to a new node every year. They're looking for power savings, not shrink. Sperling goes on to make an interesting observation about Intel/MobileEye and power savings vs. shrink – by all means read what he has to say about that.... In conclusion, Sperling asserts that we are now witnessing a shift in the semi supply chain essentially dovetailing with the expansion of FD-SOI adoption and its ecosystem, wherein “...as new markets open up, chipmakers are finding themselves much closer to the application than in the past.” All in all a great read – don't miss it. Products! David Lammers (who you probably know from SST) wrote about products on FD-SOI for GF's Foundry Files in 22FDX Shows IoT Traction at MWC 2018. A number of start-ups will be showing products on GF's 22FDX (FD-SOI) technology at Mobile World Congress. For example, Nanotel Technology is using 22FDX to “...reduce power consumption for its mixed-signal NB-IoT modem.” Lammers interviewed the company's CTO, Anup Savla, who explained, “We have a digital engine, a processor, designed around IoT applications, where the emphasis is on low power and low leakage. With 22FDX there are knobs that are available to turn down the power and leakage. The opportunities to do that are unparalleled, and you just don’t get that kind of opportunity from bulk CMOS.” A significant part to this design is analog – which of course really benefits from FD-SOI. [caption id="attachment_11520" align="alignleft" width="300"] Riot Micro CEO Peter Wong cites savings in power, area and TTM with 22FDX. (Courtesy: GlobalFoundries)[/caption] Riot Micro on the other hand, has designed an all-digital cellular modem for LTE Cat-M and NB-IOT. There's no DSP, and big parts of the chip can be shut down as needed to save power for long-term battery operation in the field (get more details in the full GF blog). Several major cellular carriers are on track to certify it this year, and a Middle Eastern customer plans to incorporate it into an emergency-alert system. The company's CEO, Peter Wong told Lammers, “With 22FDX, the value proposition for us is potential power and area savings.” They also leveraged the growing 22FDX IP ecosystem to accelerate TTM. Dream Chip Technologies, which as Lammers reminds us, showed their multi-core vision processor at MWC last year, says that now “...the design is providing European auto makers and Tier 1 automotive component suppliers with a platform from which they can create custom derivatives.” Verisilicon, an SOI Consortium member and a major FD-SOI champion in China will be teaming up with GF show their dual-mode connectivity solutions (which we first heard about last year). GF and VeriSilicon have a suite of IP so that customers can create single-chip, low-power wide-area (LPWA) solutions that support either LTE-M (for the US) or NB-IoT (for Asia Europe). The IP covers integrated baseband, power management, RF radio and front-end components. Lammers also cited Anubhav Gupta, GF's director of strategic marketing and business development for IoT, AI Machine Learning. He said they've got customers taking older multi-chip designs and re-creating them as single-chip solutions in 22FDX for better performance and savings in area, power and cost. Gupta noted that with body biasing in digital designs, they can operate down to 0.4V with standby leakage currents of less than one picoamp per micron. And when embedded MRAM is used in tandem with on-chip SRAM, off-chip flash can be completely eliminated. Nice! Clear Winner In a wide-ranging interview (see part 7, which focuses on FD-SOI), GF CTO Gary Patton told Anandtech's Ian Cutress that, “FinFET is a great technology for [performance at any cost], but if you're looking for something that is more in the consumer space, you need to balance performance with power and cost, you know FD-SOI is a clear winner.” Patton told Cutress that they have working 12FDX devices in NY that are already close to reaching performance targets. They'll be in risk production in early 2019. Meanwhile in 22FDX, Patton talked about the different flavors, including RF, ULP, UL leakage and mmWave, and how well suited they are for target applications especially in automotive and IoT. Elsewhere in the interview he mentioned that potential customers in the cryptocurrency mining businesses are looking at 22FDX, and that ST will be using it to do some “incredible products”. All in all – products and press – it's a really fine Q1.

We fold our clothing. Our bath towels. Our sheets. And for the more artistically inspired among us, our origami. So why not our smartphones and tablets – those marvelously expansive if physically rigid windows to the world?Turns out we’re tantalizingly close to seeing flexible OLED displays, the only barrier to foldable smartphones, a full session on flexible displays at 2018FLEX, Feb. 12-15 in Monterey, California, revealed. With prototype flexible displays in play and the basic technology available, all that’s left before adoption are efficient processing and product development. Ross Young, founder and CEO of Display Supply Chain Consultants (DSCC) put it this way at the mid-February gathering of flexible hybrid electronics (FHE) industry players in Monterey, California: “If panel manufacturers can produce foldable OLEDs at sufficient yields to bring down costs and prices, and brands can develop products that unleash the form factor advantages of OLEDs and better communicate the performance and power benefits of OLEDs, the whole OLED supply chain will benefit.” Of course, prototype development is a key step in proving out designs of OLED displays and other FHE products. Now developers now have help with a process design kit from Hewlett Packard and NextFlex’s open-source Arduino kit for rapid prototype creation and testing, formally unveiled at 2018FLEX, the 17th annual event organized by SEMI-FlexTech, the Nano-Bio Manufacturing Consortium (NBMC) and NextFlex. The conference, which co-located with the 16th annual MEMS Sensors Technical Congress (MSTC), promotes FHE as one way to enable healthier, safer, simpler and smarter electronics products. Typical of a fledgling industry, a slew of flexible display innovators are working to identify viable markets as they develop prototypes. But some designs have vaulted to product development as they edge closer to commercialization or have already hit the market. The list includes FHE printed antennas, smart tags for asset monitoring, a host of consumer health monitors with wireless communication capabilities, and thrilling large-area display installations like E Ink’s Dazzle® -- wrapped around one side of a new car rental center at San Diego International Airport. Dazzle by E Ink Indeed, sensors for wireless medical applications drew some of the strongest interest at the event. Applications included deep brain stimulation to treat conditions including Parkinson’s, epilepsy, OCD and chronic pain (Cortera Neurotechnologies); human hydration monitoring (GE Research); patch-based wearable monitoring to enable better patient outcomes (Graftworx), and measuring blood oxygen levels using oximeters (University of California Berkeley). UMass Lowell presentation summary on printing textiles In the area of manufacturing – long a focus of FLEX – low-cost, low step-count roll-to-roll processes are advancing rapidly as industrial applications adopt these capabilities. At the same time, NextFlex continues to lead the charge in improving FHE manufacturability by providing public/private funds and leading collaboration initiatives. Manufacturing has been at the heart of many FlexTech technical projects and led to FlexTech’s formation of NextFlex, America’s Manufacturing Innovation Institute for flexible hybrid electronics. Paul Gagnon, IHS Markit, keynotes on the progress of flexible displays “2018FLEX splendidly met its objectives,” said conference chair, Bob Praino, CEO of Chasm Technology. “With the keynotes, we explored the breadth of applications enabled by FHE. With the sessions, we dove into the depths of materials, processing, and components demanded by the end-applications. And the exhibit provided the hands-on opportunity to explore new industry collaborations. FHE has clearly moved beyond conceptual and, best of all, many participants found answers to product needs here at the conference.” Beyond technology, the future brainpower for FHE was also on prominent display at 2018FLEX with college students participating in the Student Poster Session, judged by industry experts. The top three entries: First place: Jonathan Ting from UC Berkeley with a poster titled “Fully Screen-Printed NiO thermistor Arrays” Second place: Talha Agcayazi from North Carolina State University with a poster titled “Multi-Modal Array Sensing with Textiles” Third place: Levent E. Aygun from Princeton University with a poster titled “Sound Identification Using Physically-Expansive Sensing System” Outstanding industry achievements and contributions were also recognized at 2018FLEX with the FLEXI Awards. For a copy of the 2018FLEX proceedings, contact Amy Ly at [email protected]. Heidi Hoffman is senior director of FHE, MEMS and Sensors Marketing, SEMI.

RF-SOI is in every smart phone out there, and with 5G, there are lots more applications on the horizon. If you’d like to learn more about designing in RF-SOI, there’s a great short course coming up the day before and in conjunction with the EuroSOI-ULIS Conference in Granada, Spain.The title of this short course is RFSOI: from basics to practical use of wireless technology. Program and registration details can be found here. The course runs for the full day on Sunday, 18 March 2018.The talks, which are being given by a stellar line-up of experts, include: RF SOI, fabrication, materials and eco-system - Ionut Radu Director of Advanced R D, Soitec Fundamentals of RF SOI technology - Jean-Pierre Raskin, Professor, UCL 22nm FDSOI Technology optimized for RF/mmWave Applications - David L. Harame, RF CTO Development and Enablement, GlobalFoundries RF SOI technology and components for 5G connectivity - Christine Raynaud, Program Manager (Business Development – Technology to Design), CEA-Leti Analog and RF design on SOI - Barend van Liempd, Senior Researcher, imec Techniques and tricks for RF measurements on SOI - Andrej Rumiantsev, Director RF Technologies, MPI Corporation FOSS TCAD/EDA tools for advanced SOI-device modeling - Wladek Grabinski, R D CM Manager, MOS-AK RF design flow for SOI - Ian Dennison, Design Systems Senior Group Director, Cadence The course is being organized by SOI Consortium members Incize and Soitec. BTW, this year marks the 4th joint EUROSOI – ULIS Conference. The EuroSOI Conference, which has been ongoing for decades, is well paired with the ULtimate Integration on Silicon Conference. The joint conference provides an interactive forum for scientists and engineers working in the field of SOI technology and advanced nanoscale devices. One of the key objectives is to promote collaboration and partnership between different players from academia, research and industry. As such, it covers technical topics, industry trends and updates from pertinent European programs. EuroSOI-ULIS will take place 19–21 March 2018 at the University of Granada in Spain. For information on the program and how to register, see the website. Following the conference, the papers will be available at the IEEE Xplore® digital library, and the best papers will be published in a special issue of Solid-State Electronics.

GlobalFoundries' 45nm RF-SOI platform is qualified and ready for volume production on 300mm wafers (read the company's full press release here). It was just at the beginning of last year that GF announced the PDK availability for 45RFSOI (we covered it here). Now there are several customers engaged for this advanced RF SOI process, which is targeted for 5G mmWave front-end module (FEM) applications, including smartphones and next-generation mmWave beamforming systems in future base stations. In case you missed it, at the Consortium's Shanghai symposium GF's Mr. RF -- Peter Rabbeni -- gave a great talk on the company's RF-SOI capabilities, which are very impressive (they've shipped over 32 billion RF-SOI devices, after all). His slides from that day are available here on the SOI Consortium website. See his slide 12 for an indication of how 45RFSOI fits into the overall picture. [caption id="attachment_11482" align="alignnone" width="768"] Slide 12 from Peter Rabbeni's talk at the RF-SOI Symposium in Shanghai. (Courtesy: GlobalFoundries and the SOI Consortium).[/caption] As they explain it, next-generation systems are moving to frequencies above 24GHz, so higher performance RF silicon solutions are required to exploit the large available bandwidth in the mmWave spectrum. GF’s 45RFSOI platform is optimized for beam forming FEMs, with features that improve RF performance through combining high-frequency transistors, high-resistivity SOI substrates and ultra-thick copper wiring. Moreover, the SOI technology enables easy integration of power amplifiers, switches, LNAs, phase shifters, up/down converters and VCO/PLLs that lowers cost, size and power compared to competing technologies targeting tomorrow’s multi-gigabit-per-second communication systems, including internet broadband satellite, smartphones and 5G infrastructure. Psemi and Anokiwave are among those companies at the forefront of 45RFSOI use. Citing the drive to deliver faster, higher-quality video, and multimedia content and services Anokiwave CEO Bob Donahue said, “GF's RF SOI technology leadership and 45RFSOI platform enables Anokiwave to develop differentiated solutions designed to operate between the mmWave and sub-6GHz frequency band for high-speed wireless communications and networks.” The production line is in East Fishkill, N.Y.

ASN asked Carlos Mazure and Giorgio Cesana, the Executive Directors of the SOI Consortium, to take a moment to share their outlook for 2018. Here’s what they had to say. First of all, we’d like to wish everybody in the SOI ecosystem a safe, happy and prosperous 2018. We just finished up a great year, and now look forward to exciting prospects in the months to come. Taking a quick look back, 2017 was marked by significant growth for RF-SOI markets, and with key product announcements for FD-SOI (accompanied by a very positive change in how it is viewed). In both domains, the foundries announced their roadmaps, so now the current sweet spots and future directions are clearly established. Let’s take a moment to consider RF-SOI. As those following wireless markets know, RF-SOI has been the basis for antenna front-end modules in all the world’s smart phones for a few years now. With 2018, we see the industry turn its attention to 5G, with sub-6GHz in priority but also addressing the mmW space. Thanks to various flavors of RF-SOI, and RF integration in FD-SOI, we’ll move into a new phase where wireless will get faster and lower power than ever before. This will be a hot topic in both the SOI Consortium symposiums around the world this year, and in articles coming your way here in ASN. Another hot topic will be exciting new products coming out on FD-SOI. Chip design and manufacturing is of course always a fairly long process, and we’ve talked about the importance of building the ecosystem over the last few years. Now, a good ecosystem is in place. The design tools are ready and validated at the fabs, and key IP is ready. Of course with time there will be more and more IP, but lack of IP is no longer a barrier to design starts. Embedded memory – eMRAM – is another subject that designers want to learn more about, so that will be part of what we’ll be covering. [caption id="attachment_11476" align="alignleft" width="247"] Photo courtesy: SOI Consortium / Adele Hars[/caption] Last year we saw a growing list of successful FD-SOI tape-outs. In 2018, these chips will be ramping in volume. So this year, we look at products. We’ll be inviting those companies that are ramping in silicon to present their chips at the various symposia we organize around the world: Silicon Valley in the spring, Tokyo in the summer, China in the fall. Our symposia will again be accompanied by tutorial days, which have been very popular and successful. In this year’s tutorials there will be a particular focus on RF, analog and mixed-signal design, and they’ll dive deeper into how to use back biasing techniques for further boosting performance and lowering power. So we’re at the beginning of what should be a very exciting year. We’d like to take a moment to thank all the member companies in the SOI Consortium for their enthusiastic support. And we look forward to welcoming new members over the course of this year. With warm regards, Giorgio Cesana and Carlos Mazure Executive Directors of the SOI Consortium