Forecast SummariesCharts 1 and 2 are the recent world growth forecasts for this year and next for GDP (World Bank), Electronic Equipment and Printed Wiring Boards (Custer Consulting Group), Semiconductors (SIA/WSTSI and new Semiconductor Capital Equipment (SEMI). The semiconductor-related sectors are clearly outgrowing the rest of the supply chain. These forecasts require regular review considering the current global political uncertainty and potential industry output and trade disruptions.Updates to these forecasts are regularly available.Taiwan Wafer Fab SalesComposite sales of 14 Taiwan-listed wafer fabs including TSMC and UMC dipped sharply in June. This sales composite has been historically a useful leading indicator for global semiconductor shipments (Chart 3). If wafer fab sales remain weak, they may signal an imminent chip slowdown. These data are updated monthly.Wafer Fab, Semiconductor and SEMI Capital Equipment Business CyclesChart 4 compares the 3/12 growth of global semiconductor and semiconductor capital equipment to Taiwan-listed wafer fabs. Watch this information over the next few months to see if the wafer fab dip is temporary or leads semiconductor and SEMI equipment down to slower growth. Walt Custer of Custer Consulting Group is an analyst focused on the global electronics [email protected]

Standing-room only keynote speeches. A future awash in data amassed by transformative technologies and applications, with semiconductors at their core. Smart everything: Cars, medicine, manufacturing, workforce, you name it. The sheer numbers impressed as a record lineup of SEMICON West keynote speakers offered a glowing portrait of the future: The semiconductor industry stands on the cusp of a breakout expansion. Standing and seated shoulder-to-shoulder in the packed-to-gills opening keynote, the audience learned, indeed, that the best was yet to come: “This is the best SEMICON West, ever,” observed SEMI CEO Ajit Manocha. Here’s a glimpse of the keynotes by the numbers, starting with the luckiest of all. 7 – The number of keynotes – among the brightest lights in technology – sharing their visions of the future through the lens of breakthrough technologies that are nearly ready to make their indelible mark. Dozens of expert panelists also weighed in at SEMICON West, the annual U.S. flagship microelectronics gathering in San Francisco. 90 – The percentage of all data ever generated has been created in just the past two years as the cloud mushrooms with tweets, texts, emails, Facebook posts, YouTube videos, medical records and all manner of business information, noted Bill Bottoms, president and CEO of Third Millennium Test Solutions. In the years ahead, an almost unimaginable wealth of data will require analysis by artificial intelligence (AI) embedded in semiconductors to enable applications that go well beyond smart. 12-18 – That’s how many months it will take for data volume to double, predicted John Kelly III, IBM’s Senior VP, Cognitive Solutions. And it will double again and again, every 12-18 months. Kelly foresees a scale of growth “that will dwarf previous eras of computing … the number of opportunities is enormous.” Kelly’s four decades in computing gave considerable weight to his point that “in the industry, there has never been a more exciting point in time than today.” First – Technology is being re-born. Using baseball lingo, several speakers noted that we are just in “the first inning,” “the top half of the first inning” or “the beginning of the first inning” to make clear in the most emphatic terms the duration of prosperity that lies ahead for the industry. AI embedded in chips and demand for real-time analysis of AI data will be its fuel. As SEMI Americas president Dave Anderson observed with a smile, “We all know how long baseball games can go.” Third – That’s the current wave of machine learning the world is now experiencing, according to Sandia National Laboratories’ Principal Member Conrad James. Computers are now capable of solving many increasingly complex problems on their own, with no human intervention necessarily required, he said. 1000x – As spectacularly fast as computing power already is today, the industry will need to double that the rate of performance in the years ahead, predicted Applied Materials president and CEO Gary Dickerson. Demand for this herculean processing capacity will spur a “tremendous focus on innovation” among SEMI members, their customers and their customers’ customers. 5 to 15 – The remarkable amount of silicon that power today’s mobile devices will be overshadowed by the chips – equivalent in computing capacity to 5 to 15 cell phones – that will be the engine of self-driving and other features in future automobiles, predicted Pierre Ferragu, New Street Research Managing Partner, during the SEMI Bulls and Bears session. Automobiles with this souped-up computing capacity will sell in the millions worldwide in the years ahead, generating never-before-seen opportunities for the chip industry, he noted. 10,000 – It’s not just cars. Ten thousand is the number of sensors that will be built just into the wings of new Airbus A380-1000 aircraft, AMD CTO Mark Papermaster explained during his keynote. 10 terabits – The staggering amount of Facebook data uploaded daily in to the cloud, Papermaster noted. 1 Trillion – SEMI’s 2020 forecast that the industry will reach $500 billion in revenues by 2020 was eclipsed by one analyst, speaking at the SEMI Market Symposium on the first day of the event, predicted that the industry would top $1 trillion in the foreseeable future. SEMI’s Manocha later added that $1 trillion in industry revenue is possible by 2030, “maybe sooner.” 1 (sexy) coda – Coders are hip and software applications are the apple of the world’s eye. Even the most casual mobile device user knows that software apps makes it whirl. But “hardware is becoming sexy again,” said Applied Materials’ Dickerson, adding that equipment and other semiconductor hardware developed by SEMI members will enable the next great wave of global economic growth. Scott Stevens, SEMI

Driven by the adoption of evermore electronic components in end products, the semiconductor industry is facing a new era in which device scaling and cost reduction will no longer continue on the path followed for the past few decades. Advanced nodes no longer bring the desired cost benefit, and R D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to satisfy market demands, the industry is looking for technology solutions to bridge the gap and improve cost/performance while at the same time adding more functionality through integration.More than-Moore devices (including MEMS and sensors, CMOS Image Sensors, power electronic, along with RF devices) represent this new functional diversification of technologies, combining performance, integration and cost not limited to CMOS scaling, and their importance will become more and more preponderant.In 2017, wafer demand for More than Moore devices1 reached almost 45 million 8-inch eq. wafers. This figure is expected to reach more than 66 million 8-inch eq wafers by 2023, showing an almost 10 percent growth during this period.This increase is supported by the famous megatrends detailed in the new analysis, Wafer Starts for More Than Moore Applications2, performed by Yole Développement (Yole). This analysis is relevant to the following markets: 5G with wireless infrastructure and mobile segments, mobile including additional functionalities, voice processing, smart automotive and electrification, AR/VR3, and AI4.For the first time, the market research and strategy consulting company presents a dedicated technology and market analysis focused on the overall wafer demand for More than Moore devices. The aim of this report is to give an overview of wafer shipments for More than Moore devices, from wafer size to semiconductor material substrate type including silicon, glass, SOI5, SiC6, SiGe7, GaN8, InP9, GaAs10, sapphire and ceramic, and thus identify business opportunities in the More than Moore industry.For over 20 years, Yole has been analyzing the industry evolution, discussing with leading companies to understand market challenges, and identifying technical breakthroughs. The Wafer Starts for More Than Moore Applications report is the result of this 20-year research. Yole’s analysts combine technical and market expertise to describe the More than Moore world. Market size (volume and value), substrate sizes and formats, value chain, technology processes and market drivers, business opportunities and competitive landscape are all part of Yole’s analysis.The various research teams at Yole, encompassing power electronics, imaging and sensing, RF and semiconductor manufacturing, collaborate to present an in-depth understanding of the current market evolution, taking into account innovations and emerging businesses. This methodology allows Yole to cover the overall megatrends and illustrate the links between wafer substrate, device, module, sub-system, system and high-end product.Under this dynamic ecosystem, the deployment of renewable energy sources and industrial motor drives as well as the electrification of the automotive industry are good examples of the impact of megatrends on the semiconductor industry development. They are directly impacting the power devices’ wafer market, resulting in an expected 13 percent CAGR between 2017 and 2023. Already in 2017, this market represented more than 60 percent of the overall wafer market for More than Moore devices, and is currently still dominating the More than Moore industry.5G is one megatrend driving wafer demand. 5G is leading the More than Moore evolution, bringing any service to any user, anywhere. Antennas and filtering functionalities are two of the key innovations of this evolution.Without doubt, the stringent requirements of 5G are driving increasing demand for RF components like RF filters, power amplifiers (PAs), and low-noise amplifiers (LNAs) to ensure access to tomorrow’s radio network.This year, Corning and Menlo Micro announced a major agreement to develop a DMS[11] product platform. Both partners propose an innovative approach based on TGV12 packaging technology. According to both partners, this technical choice allows them to cover operation of frequencies beyond 50GHz. Amongst the numerous megatrends, mobility is not far behind 5G. Demand for advanced mobile applications integrating more and more functionality is growing. In order to compete companies are developing smart combinations of devices such as fingerprint sensors, ambient light sensors, 3D sensing, microphones, and inertial MEMS devices. As an example, impressive developments focused on SOI-based NIR sensors have been released by SOITEC for front-side imager applications including advanced 3D image sensors. This technical evolution will clearly contribute, in the near future, to strong growth of the wafer market for MEMS and sensors. Additionally, the automotive industry, with the development of smart cars, has reached a new level of complexity requiring the development and integration of new sensors. In this context, many companies are aiming to extend their capabilities in ADAS13 and autonomous driving. Recently the leading company On Semiconductor acquired SensL Technologies, the leader in SPAD and LiDAR sensing products for automotive. This acquisition is one sign among many highlighting the evolution of this historic industry, searching for new expertise and welcoming new players, more aware of consumer habits and needs.Yole’s analysts expect smart automobiles to drive consistent growth of CIS14 and sensor wafer production over the next five years. It is fueled by the increasing integration of high-value sensing modules like RADAR, imaging, LiDAR and more. Although automotive will be mainly supported by these growth areas, historic MEMS and sensors such as MEMS pressure sensors and inertial MEMS will continue growing at a reasonable rate, supporting the standard automotive world.Yole Group of Companies including Yole, System Plus Consulting, KnowMade, PISEO and Blumorpho follows and analyzes the industry continuously. The Group has developed in-depth expertise and knowledge focused on the semiconductor manufacturing process and markets. Companies of the Group work together to understand the technical issues, identify business opportunities and propose valuable analyses.Yole invites you to an overview of the Wafer Starts for More Than Moore Applications report during the exclusive online event, titled “Wafer Starts for More than Moore Applications – Webcast”. This hourlong webcast takes place on June 28 at 5:00 PM CEST. The market research company will present key results of this report including megatrends, wafer market evolution and technical trends. Moderated by David Jourdan, Sales Coordination Customer Service at Yole, it welcomes the two leading companies, SPTS (an Orbotech Company) and Corning Precision Glass Solutions: "Trends in Wafer Processing Technologies for RF MEMS" – Speaker David Butler, Executive Vice President and General Manager at SPTS Technologies "Benefits of Through Glass Vias for RF applications" – Speaker: Ravij Parmar, New Product Development Manager for Corning Precision Glass Solutions These results will be also presented by the Semiconductor Software team at SEMICON West (Booth #1320), SEMICON Taiwan and SEMICON Europa (Booth #A-4667). Make sure to meet Yole’s analysts and get a valuable overview of the More than Moore industry. Agenda and more information are available on i-micronew.com. Stay tuned!About the authors:Amandine Pizzagalli is a Technology Market Analyst, Equipment Materials - Semiconductor Manufacturing - at Yole Développement (Yole). Amandine is part of the development of the Semiconductor Software division of Yole with the production of reports and custom consulting projects. She is in charge of comprehensive analyses focused on semiconductor equipment, materials and manufacturing processes. Emilie Jolivet is Director of the Semiconductor Software Division at Yole Développement, part of Yole Group of Companies, where her specific interests cover package assembly, semiconductor manufacturing, memory and software computing fields. 1 Including: MEMS sensors, CIS, and power, photonics and RF devices2 Yole Développement, March 20183 AR/VR : Augmented Reality/Virtual Reality4 AI : Artificial Intelligence.5 SOI : Silicon On Insulator6 SiC : Silicon Carbid7 SiGe: Silicon Germanium8 GaN: Gallium Nitride9 InP: Indium Phosphide10 GaAs : Gallium Arsenide111 DMS : Digital-Micro-Switch12 TGV : Through Glass Via13 ADAS : Autonomous Driving Assistance Service14 CIS : CMOS Image Sensor

That FD-SOI can be a key to achieving near-threshold voltage design was an important point made during a #55 DAC expert panel. Entitled How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? the session was organized by Jan Willis of Calibre Consulting. Turnout was excellent. Btw, Jan (herself an EDA expert) was one of the original advisors in the formation of the SOI Consortium, and while this DAC panel was not meant to be about FD-SOI, it turned out be a focal point. Near-threshold voltage design* is an especially hot topic for IoT and edge-computing designers, for whom balancing performance, reliability and extremely low power is generally challenge #1. For them, the ability to get chips working at very low voltages translates into battery life savings. The original goal of the panel was “...to explore how far below nominal voltage we can design, in what applications it makes sense and in what ways it will cost us.” The description in the #55 DAC program noted that “Energy consumption is the driving design parameter for many systems that must meet 'always-on' market requirements and in IoT in general. For decades, the semiconductor industry has attempted to leverage the essential principle that lowering voltage is the quickest, biggest way to reduce energy for a SoC. Some today contend sub-threshold voltage design is viable while others argue for near-threshold voltage design as the minimum.” (Update 2 August 2018: a complete video of this panel is now available on YouTube -- click here to view it.) [caption id="attachment_12035" align="alignnone" width="958"] #55 DAC Expert Panel: How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? Left to right: Brian Fuller, Arm (moderator); Scott Hanson, Ambiq Micro; Lauri Koskinen, Minima Processor; Mahbub Rashed, GlobalFoundries; Paul Wells, sureCore. (Organized by Jan Willis of Calibre Consulting)[/caption] The panelists included: Scott Hanson - Ambiq Micro Mahbub Rashed - GLOBALFOUNDRIES Lauri Koskinen - Minima Processor Paul Wells - sureCore Ltd., Sheffield Brian Fuller of Arm served as moderator. [caption id="attachment_12033" align="alignright" width="200"] Panel organizer Jan Willis, Calibre Consulting[/caption] Following the panel Jan published the following excellent recap on LinkedIn. She graciously agreed for it to be reprinted here in ASN, for which we thank her. So without further ado, read on! #55DAC Expert Panel on Near-Threshold Voltage Sees Growing Opportunity Despite ChallengesFirst published on LinkedIn, June 27, 2018 by Jan Willis, Strategic Partnerships Marketing Executive Brian Fuller, Arm, skillfully guided a group of experts through the challenges of near-threshold design to conclude that the adoption is going to start gathering pace in a panel session at the 55th DAC in San Francisco on Monday, June 25. Scott Hanson, CTO of Ambiq Micro, led off by saying the list of what's not challenging is a much shorter list but that by taking an adaptive approach, they have been successful. It's required innovating throughout the design process including test where Scott said they had create their own "secret sauce" to make it work. Later on in the panel, Scott described designers in near-threshold as "picojoule fanatics" to overcome the limitations in design tools which are geared towards achieving performance goals. Lauri Koskinen, CTO of Minima Processor, agreed that adaptivity is key. Minima says it has to be done in situ in the design to make it robust for manufacturing while useful across more than one design. Later in the panel, Lauri indicated that FD-SOI is like having another knob available for optimizing energy in the Minima approach to near-threshold design. Mahbub Rashed, head of Design and Technology Co-Optimization at GlobalFoundries, highlighted the need for more collaboration between EDA, IP, and foundries to support near-threshold design but noted a lot of progress has been made on FD-SOI processes. Mahbub cited models down to 0.4V for FD-SOI processes are available now and GlobalFoundries is able to guarantee yield. Paul Wells, CEO of sureCore, validated that sureCore has bench marked their memories on GlobalFoundries FD-SOI with success. He reflected that FD-SOI has rapidly established itself as cost effective for a number of emerging markets. The panel all agreed that achieving quality on the memory at near-threshold voltage was much tougher than for digital IP. [Editor's note: sureCore's CTO wrote an excellent summary of their SRAM IP for FD-SOI in ASN back in 2016 – you can still read it here.] Paul went on to summarize at the end of the panel that near-threshold voltage is the way of the future and that it's gathering pace. Mahbub called upon the EDA community to step up to improve the tools for low energy design. Lauri and Scott both summarized that there were drivers emerging that will grow the addressable market for near-threshold voltage design. Lauri pointed to growth coming from the applications that require edge computing which he thinks will require near-threshold voltage design. Scott concluded the panel by pointing out that there's been a tremendous increase in performance of near-threshold voltage designs which will increase the addressable available market in the future. ~ ~ ~ This piece was first published by Jan Willis on LinkedIn, June 27, 2018. Here is the original. * As explained by Rich Collins of Synopsys in the TechDesign Forum: "Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity. [...] A transistor’s threshold voltage (Vth) is the voltage at which the transistor turns on. Most transistor circuits use a supply voltage substantially greater than the threshold voltage, so that the point at which the transistors turn on is not affected by supply variations or noise. [...] In sub-threshold operation, the supply voltage is well below the Vth of the transistors. In this region, the transistors are partially On, but are never fully turned. Near-threshold operation happens between the sub-threshold region and the transistor threshold voltage Vth, or around 400 – 700mV for today’s processes.

Powerful winds of change are re-shaping the semiconductor industry as it flexes and re-positions to power a new wave of growth on the back of emerging applications. Today, the industry is thriving, with growth expected to continue through 2019 even as Moore’s Law – the trusty doubling of transistors roughly every two years – begins to pump the brakes. Product mix and production technology are shifting as the dominant smartphone and PC markets, having seen their growth peaks, start to give way to large markets with relatively low semiconductor penetration, such as automotive.What’s more, new potentially ubiquitous technologies and platforms such as AI, blockchain and smart manufacturing are redefining market dynamics and the semiconductor ecosystem that underlies them.Troublingly, the most significant threats to the continued growth of the semiconductor industry are not of its own making. Macroeconomic trends and trade policy disputes loom.These were some of the key takeaways from the SEMI Market Symposium kicking off SEMICON West in San Francisco this week. Following is a deeper look.Semiconductor MarketThe consensus view, reflected in forecasts presented by Clark Tseng of SEMI and Bob Johnson of Gartner, is that the semiconductor industry could top $500 billion in 2019 after reaching $400 billion in 2017. According to Gartner, smartphones and PCs will continue to account for large parts of the market, but will be displaced as major drivers of market growth by the emergence of industrial, automotive and, to a lesser extent, storage, from 2017 to 2022. Johnson noted that while communications and data processing applications drive logic device demand, average sales prices (ASPs) are a bigger contributor to revenue growth than unit growth.Leading-edge processors are a big part of the ASP picture, with equipment costs increasing ~20 percent per node. One challenge is that as Moore’s Law loses steam, leading logic producers are increasingly going their own way with new production technology. The volatile DRAM market – now in a “super cycle,” according to Tseng, and expected to peak in 2019 – has been stoking memory market growth.Initially, supply shortages fueled memory price increases as three of the four leading memory makers invested in flash rather than DRAM capacity. However, memory prices have been more recently been lifted by technology complexity, particularly as DRAM has moved to 3D architectures. The good news is that pricing, at long last, appears to be driven by value.Automotive MarketWith automotive accounting for less than 10 percent of semiconductor demand, there is room for growth. Rudy Burger of Woodside Partners noted that while the end market for automobiles is growing slowly, at 3 percent CAGR, the market size is nearing 100 million units. In market segments such as electric vehicles, the semiconductor content exceeds $1,000 but can be much higher.For example, the BMW i3 sports over $4,000 in semiconductor content. Burger said connectivity, autonomous driving and shared mobility services are also key opportunities for semiconductors to deepen their penetration in automobiles. For instance, the auto market for cameras, is expected to grow from $2 billion in 2017 to $6 billion in 2022.On average, high-end vehicles feature over $1,000 in semiconductor content, whereas low-end vehicles hover in the $400 range, said Anand Srinivasan of Bloomberg. Because the automotive market is segmented by function or subsystem, with different suppliers focusing on different areas, there is little supply concentration. Srinivasan also pointed out that because of significant differences in their objectives, automotive safety and automation systems should be developed separately.BlockchainThe chief benefit of blockchain is the trust it begets among all parties to a digital transaction through four fundamental features, said David Treat of Accenture: The tracking of provenance (knowing who has touched data, and what has happened to it) Tamper evidence (knowing if someone has tried to change the data) Control (which data elements to share with which parties) Security at the data element level While most of the hype over blockchain focuses on tokenized assets and ledgers (bitcoin and other cryptocurrencies), the fundamental application in the semiconductor industry is sharing trusted access to reference data at the data element level. This ability to provide shared trust can reduce costs throughout the supply chain and across enterprises. For example, future blockchain implementations will offer a full ecosystem view to any supply chain participant. While blockchain has typically been deployed through centralized control or platforms, peer consortia, such as SEMI, could help weave the benefits of blockchain through various ecosystems by enabling equipment and material suppliers, device manufacturers, designers and system integrators to share business and technical information securely and, if desired, anonymously.Global and Macroeconomic TrendsThe biggest threats to the continued growth of the semiconductor industry are exogenous. After a decade of steady recovery since the financial crisis, the global economy appears to be heading for a slowdown. Duncan Meldrum of Hilltop Economics made the case that the global economy is at or just past the peak of the business cycle, and semiconductor equipment is past the peak.A key indicator of a looming recessionary is the movement toward an inverted yield curve, in which long-term interest rates fall below short-term rates – a phenomena that could materialize this year or next.The increasingly heated trade climate, marked by high-stakes confrontations between the U.S. and China, threatens complex supply chain arrangements, though mercurial policy statements could do even more harm than stiffer trade tariffs. Underscoring competing interests between the U.S. and China and the unpredictability of their relations, Robert Maire of Semiconductor Advisors pointed out that, in 2019, 60 percent of all semiconductors are expected to be used in China, deepening the dependency of several U.S. semiconductor companies on China.Paul Semenza, for SEMI Industry Research and Statistics

Leti and Soitec have announced a new collaboration and five-year partnership agreement to drive the R D of advanced engineered substrates, including SOI and beyond. This agreement brings the traditional Leti-Soitec partnership to a whole new dimension and includes the launch of a world-class prototyping hub associating equipment partners to pioneer with new materials, The Substrate Innovation Center will feature access to shared Leti-Soitec expertise around a focused pilot line. Key benefits for partners include access to early exploratory sampling and prototyping, collaborative analysis, and early learning at the substrate level, eventually leading to streamlined product viability and roadmap planning at the system level. [caption id="attachment_12066" align="aligncenter" width="644"] CEOs Emmanuel Sabonnadière (Leti) and Paul Boudre (Soitec) announcing the new Substrate Innovation Center during Semicon West '18. (Image courtesy: Leti)[/caption] Leading chip makers and foundries worldwide use Soitec products to manufacture chips for consumer applications targeting performance, connectivity, and efficiency with extremely low energy consumption. Applications include smart phones, data centers, automotive, imagers, and medical and industrial equipment, but this list is always growing, along with the need for flexibility to explore new applications starting at the substrate level. At the Substrate Innovation Center, located on Leti’s campus, Leti and Soitec engineers will explore and develop innovative substrate features, expanding to new fields and applications with a special focus on 4G/5G connectivity, artificial intelligence, sensors and display, automotive, photonics, and edge computing. “Material innovation and substrate engineering make entire new horizons possible. The Substrate Innovation Center will unleash the power of substrate R D collaboration beyond the typical product road maps, beyond the typical constraints,” said Paul Boudre, Soitec CEO. “The Substrate Innovation Center is a one-of-a-kind opportunity open to all industry partners within the semiconductor value chain.” Whereas a typical manufacturing facility has limited flexibility to try new solutions and cannot afford to take risks with prototyping, the mission of the Substrate Innovation Center is to become the world’s preferred hub for evaluating and designing engineered substrate solutions to address the future needs of the industry, inclusive of all the key players, from compound suppliers to product designers. Using state of the art, quality-controlled clean room facilities, and the latest industry-grade equipment and materials, Leti and Soitec engineers will conduct testing and evaluation at all levels of advanced substrate R D. “Leti and Soitec’s collaboration on SOI and differentiated materials, which extends back to Soitec’s launch in 1992, has produced innovative technologies that are vital to a wide range of consumer and industrial products and components,” said Emmanuel Sabonnadière, Leti CEO. “This new common hub at Leti’s campus marks the next step in this ongoing partnership. By jointly working with foundries, fabless, and system companies, we provide our partners with a strong edge for their future products."

White House-led panel to address U.S. goal to lead in development of next-generation microelectronicsSEMICON West next week will host a White House-led discussion of the anticipated national leadership strategy for semiconductors, a multi-agency initiative led by top U.S. government national security and economic organizations.Next Wednesday, July 11, a panel of U.S. officials representing agencies involved in leading the strategy will address federal research and development (R D), investment and acquisition priorities aimed at ensuring the U.S. remains the global leader in the semiconductor industry.As global economic trends and technologies such as artificial intelligence evolve, and foreign governments increasingly lure microelectronics manufacturing investments overseas, the U.S. strategy for manufacturing advanced semiconductors and driving research and development (R D) in technology innovation has become an economic priority.The White House selected SEMICON West, organized by SEMI, as the site for the discussion and this urgent call to action because of the event’s central role in bringing together critical industries across the global electronics supply chain. The multi-agency panel will outline activities and new policies under development to ensure U.S. strategic leadership in microelectronics, including focused investment in innovations key to the next generation of devices for commercial and government use. The initiative also includes public-private partnerships to accelerate the capabilities of advanced semiconductors for critical applications such as artificial intelligence (AI), cyber, secure communications, the internet of things (IoT) and big data analytics.MEDIA WHO WISH TO ATTEND MUST CONTACT IN ADVANCE SCOTT STEVENS AT +1.512.288.4050 TO OBTAIN ACCESS BADGES PANEL: National Strategy for Semiconductor and Microelectronic Innovation TIME AND DATE: 10:30 to 11:30 a.m., Wednesday, July 11 LOCATION: Yerba Buena Theater, 700 Howard St., San Francisco MODERATOR: Dr. Lloyd Whitman, Principal Assistant Director, Physical Sciences and Engineering, White House Office of Science and Technology Policy PANELISTS: Dr. Sankar Basu, Program Director, Computer and Information Science and Engineering, National Science Foundation Dr. Eric W. Forsythe, Flexible Electronics Team Leader, U.S. Army Research Laboratory Dr. Jeremy Muldavin, Deputy Director of Defense Software Microelectronics Activities, Office of the Deputy Assistant Secretary of Defense for Systems Engineering Dr. Robinson Pino, Acting Research Division Director, Advanced Scientific Computing Research, Office of Science, Department of Energy SEMICON West is organized by SEMI Americas to connect more than 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMICON West is celebrating its 47th year as the flagship event for the semiconductor industry. Find more at www.semiconwest.org.MEDIA CONTACTS:Mike Hall, SEMI Global, +1.408.943.7988Scott Stevens, for SEMI Americas, +1.512.288.4050

Strong global semiconductor industry growth is helping power rapid expansion of China’s IC manufacturers in 2018, and continuing technology innovation is inspiring the region’s optimism over the long term, said Du Shanshan, senior analyst of SEMI China, at the recent SEMI China Member Day. The chief driving force behind this year’s growth of China’s IC industry is its equipment and materials market, with the sector riding a wave of a strengthening industrial infrastructure, a rapid increase of wafer manufacturing capacity, global leadership in new fab projects and large memory investments, Shanshan added. NAURA, a leading domestic provider of high-end IC equipment, is seeing robust growth after its push to recruit highly skilled talent and bolster its technology infrastructure, customer service system and supply chain, said Zhou Yang, vice president of Procurement at NAURA, which hosted the event. Yang said the key to NAURA’s success has been its unblinking focus on technology, product quality, fast product delivery, responsiveness to customer needs, cost controls, and environmental and social responsibility. Before visiting a NAURA factory, attendees reflected on how China’s IC manufacturers, using equipment and materials sourced domestically, seized the opportunity of global semiconductor growth to drive rapid local expansion. Excited about the growth potential of China's chip industry, members expressed their commitment to contributing to its independence and self-reliance. SEMI China Membership Grows Opening SEMI China Member Day, SEMI China president Lung Chu highlighted another expansion – SEMI China’s membership growth to nearly 400 companies, behind only the U.S. and Japan. Chu credited the increase, in part, to the steady growth of the global semiconductor industry. Chu said the increase also stems from the recognition that SEMI China is the China semiconductor industry’s best partner for fulfilling its ambition of becoming a more prominent player on the world stage. SEMI China’s member services platform that includes exhibitions and conferences, industry technical standards, industry research and analysis, a publicity apparatus and a talent development initiative provides powerful ways for the industry to Connect, Collaborate and Innovate. The platform enabled SEMICON China 2018 to set a booth and visitor record for the event, with attendees numbering 91,252, a highly successful 32 percent year-over-year growth. More than 50 SEMI member companies attended the 2018 SEMI China Member Day on June 6th in Beijing to explore opportunities for the global and Chinese semiconductor industry. Cherry Sun is a marketing manager at SEMI China.

The Advanced Lithography TechXPOT at this year’s SEMICON West will explore progress in extreme ultraviolet lithography (EUVL), its economic viability for high-volume manufacturing (HVM) and other lithography solutions that will address the march to 5nm and onward to 3nm.As a prelude to the event, SEMI asked Neeraj Khanna, Global Head of the Patterning Customer Engagement Team at KLA-Tencor, a speaker at the TechXPOT, for insights about the readiness of inspection and metrology tools for EUVL applications at 5nm and 3nm. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Neeraj Khanna, Global Head of the Patterning Customer Engagement Team at KLA-TencorSEMI: In general, how would you characterize the readiness of inspection and metrology tools intended for EUVL applications at 5nm and 3nm? In particular, what are some of the remaining research and development challenges that need to be addressed for each of these nodes?Neeraj Khanna: KLA-Tencor is working closely with its customers to qualify and ramp EUV. Our suite of inspection, metrology and data analytic solutions are being implemented to enable EUV infrastructure readiness including, for example, new reticle and resist qualification, scanner qualification, and EUV ramp preparation. These EUV integration activities require process control systems that support a wide range of applications, including hotspot discovery, lithography modeling, focus/dose process window qualification, reticle print check, mask blank inspection, and process and tool monitoring.As with any major technology inflection, it is critical to understand sources of process variation to enable ramp at optimal yield. For example, stochastics result in random pattern variations, which have a major impact on EUV yield. To manage stochastics, IC manufacturers are deploying process control solutions that support fast modeling of stochastic variations coupled with high-sensitivity, high-coverage wafer defect inspection. Another example is a methodology called hybrid scanner utilization whereby, when EUV scanners are implemented in production, they will only be used for a few layers, while all other layers will be patterned with 193i scanners. This technique requires tighter control and monitoring of overlay budgets.SEMI: How are you able to achieve this tighter control and monitoring?NK: To understand why hybrid scanner utilization requires tighter control and monitoring of overlay budgets, it’s important to outline how this differs from current scanner implementation. For critical layers in current process flows using 193i lithography, pattern layers for a given wafer are printed using the same stage/chuck on the same scanner. The overlay performance achieved using this lithography strategy is called dedicated chuck overlay (DCO). Use of a dedicated scanner and chuck for lithography reduces inter-scanner and inter-chuck distortion effects, resulting in DCO overlay error of less than 1nm. When EUVL is first implemented in production, it will be used for a few layers – likely, cut masks and contacts with eventual migration to metal 1 layers. All other layers will be patterned with 193i scanners. This hybrid scanner operation eliminates any possibility of using a dedicated scanner and dedicated chuck to support tight overlay performance specifications. Instead, fabs will be forced to optimize mix-and-match overlay (MMO), with the overlay performance obtained using different scanners for printing different layers on a given wafer.With overlay specifications for advanced DRAM and logic at ~2.5nm, fabs will need to implement strict 193i-to-EUV scanner matching strategies or risk consuming 60 to100 percent of the overlay budget on just MMO. To achieve tighter overlay control and monitoring required for MMO, fabs need to implement dense, in-field overlay error measurements that feed into scanner fleet management systems. KLA-Tencor’s ATL™ overlay metrology system supports a high measurement speed and the use of small in-die targets, enabling dense in-field overlay measurements with high accuracy. Our 5D Analyzer® data analytic and management system includes scanner fleet management capability that enables automatic product-based corrections to minimize MMO error, helping fabs reduce the risk to yield loss associated with a 193i-EUV mixed scanner implementation. SEMI: What other challenges do you see coming to the fore at 5nm and 3nm?NK: Overall, the 5nm and beyond design nodes will face challenges associated with new lithography technology, potential new device structures and smaller pattern pitches. IC manufacturers will require process control solutions that not only identify process windows, but also monitor patterning parameters and defectivity at multiple points to identify process shifts. To monitor dynamic processes at these advanced nodes, inspection and metrology tools will need to have both sensitivity to critical parameters/defects and robustness to process variation in order to provide IC engineers with smart feedback for efficient control of their processes.SEMI: Could you elaborate on what will be required to monitor patterning parameters and defectivity at multiple points? How different will the techniques be at 5nm/3nm vs. at say, 7nm or 10nm?NK: As an example of monitoring at multiple points, consider the transition to EUV lithography. With EUV, the cost per scan goes up dramatically. Thus, IC manufacturers will monitor parameters at multiple points to maximize yield and minimize risk: EUV reticle qualification requires inspection and metrology throughout the entire flow from mask blank manufacturing, to the mask shop, to the IC fab. For the advanced design nodes associated with EUV, wafer qualification requires monitoring and control of wafer defectivity, shape and geometry throughout the wafer manufacturing process. It also requires control of fab incoming wafer qualification while ensuring that fab-wide processes are meeting defect and shape standards necessary for printing smaller feature sizes. EUV resist characterization and qualification requires comprehensive lithography simulation, wafer defect inspection, and film thickness and uniformity measurements to help reduce development time and prepare the litho stacks for production ramp. As EUV scanners are ramping, fabs are faced with finding any unknown particle sources within the new scanner chambers. This situation is driving the need for tighter and more frequent PWP (particles per wafer pass) chamber monitors to ensure scanner cleanliness. In addition, EUV scanner qualification requires reticle front and backside particle checks, and hotspot discovery and process window qualification using optical wafer defect inspection and e-beam review. EUV process monitoring encompasses overlay error monitoring, focus/dose monitoring, critical dimension (CD) and 3D device shape monitoring, and continuous process window monitoring. EUV inline defect monitoring and tool monitoring is important for reducing baseline defectivity in the litho cell for faster ramp, and for early identification of litho excursions in production. A critical part of this monitoring strategy is inline after develop inspection (ADI) monitoring, which is defect inspection on patterned wafers after printing and development of the resist ADI. Inline ADI innovations that find yield-critical defects allow fabs to reduce process issues, prevent at-risk wafers early in the process, and enable rework when excursions are found in production. As with past technology transitions, the implementation of multiple monitoring steps as part of a comprehensive process control strategy will be critical for a fab’s successful ramp of EUV.Debra Vogler, SEMI

New metrology and inspection technologies and new analysis approaches made possible by improving compute technology offer solutions to finding the increasingly subtle variations in materials and subsystems that meet specifications but still cause defects on the wafer. More collaboration across the supply chain is helping too. SEMICON West programs on materials and subsystems will address these issues. New metrology approaches needed to deal with process margin challenges As device process margins shrink and subtler materials variations cause unwanted deviations, the need for better monitoring of both surface and sub-surface material variations is driving a trend towards “metro-spection” – the convergence of metrology and inspection. “Device process margins have eroded to the point that traditional metrology strategies and techniques are no longer viable for controlling yield and parametric performance,” says Nanometrics Vice President Robert Fiordalice, who will speak in the materials program at SEMICON West. “Limited sampling capability, low throughput, insufficient sensitivity or the destructive nature of the techniques can often become problems. What’s more, deviations in material characteristics are not always determined by the initial quality of the material, but often arise from variations during the integration of the materials.” One new type of inline tool or line monitoring technology is Fourier Transform Infrared (FTIR) spectroscopy, traditionally used in quality control or tool characterization. Better sensitivity and higher throughput now enable rapid analysis and feedback for on-the-fly detection of subtle deviations in film properties that may compromise device performance or yield. More advanced analytics will help extract new information from old metrologyMore expensive metrology may not be required to identify subtle variations in in-spec materials that cause wafer defects. Today’s advanced compute capabilities now enable more sophisticated analysis of existing data and the identification of small but significant variations in raw materials and finished goods. The figure of merit (FoM) values presented in certificate of analysis (CoA) reports miss subtle variations in raw material properties. Of particular note is the reduction of molecular weight distributions to a mean, and standard deviation, whereas variations in the tails are associated with pattern defects. Advanced compute capabilities now allow the industry to step beyond the FoM in favor of more holistic measures, enabling predictive analysis of resist chemical variations associated with specific pattern defects. Source: JSR Micro“We often don’t need to find a new measure, but just a new way of looking at what we measure now,” says Jim Mulready, vice president of global quality assurance at JSR Micro. Mulready will speak in the SEMICON West program on materials defectivity issues. “The certificate of analysis reduces multiple measurements to a single figure of merit. But if we ignore all that raw data, we miss a chance to learn. One of our sayings in quality is ‘Customers don’t feel the average, they feel the variation.’ In many electronic materials, the quality of the raw material can have a big impact on the final performance, but the types of analysis needed to look at the tails of the distribution of these measures (such as molecular weight) in detail used to be really hard to do. Now it’s becoming increasingly straightforward and affordable.” Mulready says tools now available in the data processing sector enable the identification of subtle variations in materials that can cause defects on the wafer. These tools use methods like detailed subtractions of chromatography curves of polymer raw materials or analysis of tails of distributions of molecular weights. “Our job now is to drive these kinds of more sophisticated data analysis back into our chemical supply chain as well,” says Mulready. “We must work more closely with our suppliers to integrate their raw materials into our products. The reason the JSRs of the world exist is as a safety valve to reduce the variation from the chemical industry before it gets to the fab.”Continued collaboration with equipment suppliers required While the industry has been talking about the need for tighter collaboration between materials suppliers and equipment manufacturers for years, it still doesn’t always happen. “The material supplier and the equipment maker are tied together like kids in a three-legged race when we deliver an integrated system for consistent on-wafer performance,” says Cristina Chu, TEL/NEXX director of strategic business development, another speaker in the materials program. “When we introduce changes to the tool hardware, we need to make sure it doesn’t upset the system. Similarly, we need the material supplier to send a bottle over when a new chemistry formulation is under development. If a new chemistry runs into problems in the field, it will take much more time for both of us to fix it at the customer site. The toolmaker can provide a slightly different perspective on applications, while being more objective than a customer on how the formulation performs compared to earlier versions.”Regular and ongoing collaboration between chemistry suppliers and toolmakers enables the highest quality system solution to reach the customer. Chu notes that her team tries to maintain consistent collaborations with material suppliers across changes in organizations as the business environment changes. “For consistent on-wafer capabilities, we need a consistent collaboration process with chemistry suppliers. We need to meet with materials providers at a regular cadence throughout their development process. We need to check back with them as we scale up results from the coupon to the wafer level and to work out the kinks in the integrated solution together. The quality and consistency of our combined performance at the customer depends on ensuring the quality and consistency of our development and evaluation process as well.”Fabs and subsystems suppliers look to pilot data sharing program to improve process margins With ever tighter process margins, subtle variations in parameters that don’t appear in the specifications are also compromising results on the wafer, and neither the fab nor the supplier alone has the full information needed to improve performance. To help, a SEMI standards group is developing a protocol for a pilot program to standardize and automate some data sharing.The fab knows that performance is best with a particular parameter value, and knows when performance fluctuates, but often faces a black box problem with no way of knowing what exactly is wrong. In the rush to get the tool back up, the fab engineers may not get around to emailing the supplier about the issue for some time. The subsystems supplier, on the other hand, may know the cause of the variation, but likely has no way of knowing the critical parameters or ideal target values for the fab’s process. “In order for engineers to have constructive conversations about how to improve performance, we all need to exchange more information,” says Eric Bruce, Samsung Austin diffusion engineer, and co-chair of the SEMI Standards initiative addressing the issue, who will speak in the subsystems program at SEMICON West. A potential solution could be to create a standard and automated process to share particular data, agreed to in the purchasing contract, whereby the subsystems supplier shares more information about their parameters with the fab, and the fab in return gives feedback on what parameters work best to drive improved performance. The best place to start will likely be on parts that do not contain core yield-related IP, but where usage and lifetime information is useful.“We’re looking for people to participate in a pilot program to work together with suppliers to try sharing some information to improve performance,” says Bruce. “There’s a lot of this sharing in the backroom anyway, but this could make it fast and automated, and make everyone’s engineering job a lot easier.”Paula Doe, SEMI