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Laith Altimime, President, SEMI Europe


As President of SEMI Europe, Laith Altimime leads SEMI’s activities in Europe and Middle East and North Africa (MENA). He has overall responsibility for regional events, programs, membership, advocacy, and collaborative forums. Additionally, he manages and nurtures relationships with SEMI members in the region, as well as with local associations and constituents in industry, government, and academia. He provides support and services to SEMI members worldwide that have supply chain interests in Europe. Altimime has more than 25 years of experience in the industry, mostly in Europe. He has held leadership positions at Altis, Infineon, Qimonda, KLA-Tencor, Communicant Semiconductor AG, NEC Semiconductors, and imec. Altimime holds a BS from Heriot-Watt University, Scotland.



Kim Arnold, Executive Director - Wafer Level Packaging Materials, Brewer Science

Brewer Science Logo

Kim Arnold is the Executive Director of Wafer-Level Packaging Materials at Brewer Science, Inc., where she works with partners and customers globally to improve next generation advanced packaging materials. She has held various positions at Brewer Science in her 20 years of experience in the semiconductor industry, ranging from business analyst to customer relations director. In her time at Brewer Science, Kim has co-authored over 25 papers on topics from high-topography materials to fan-out device material build-up.  Prior to joining Brewer Science, she worked for a software development company and graduated from the University of Missouri-Rolla with her B.S. in Economics.



Mustafa Badaroglu, Technical Director, Huawei Technologies


We are living in a connected world with access to data in vast amounts. We now need to make this data connectivity more intelligent and accessible by making use of more sensors and by enabling more energy-efficient computation and networking. This could for instance include more intelligent sensors bringing people closer to the computation in a more natural and accessible way. This could also include new assembly and integration schemes, such as 3D integration for the energy-efficient machine learning computation, enabling more connectivity bandwidth and energy-efficient computation. In this talk we will present a landscape of technologies enabling this goal of intelligent connectivity and computation. 

Dr. Mustafa Badaroglu is the Technical Director working on chipset and technology planning of products in the domains of mobile processors, networking, automotive, and wearables. He had various assignments for the execution and management of chipset design from concept to volume production, process technology pathfinding, and design-technology co-optimization. He received his Ph.D. in Electrical Engineering and holds a Master of Industrial Management, both from the Catholic University of Leuven. He holds more than 50 published patents and he has (co)-authored over 100 publications in scientific journals/proceedings. He is the chair of More Moore section in International Roadmap for Devices and Systems (IRDS). He is a senior member of IEEE.



Richard BarnettSenior Product Manager for Etch Products, SPTS Technologies

spts logo

There are many emerging applications where die strength is critically important, most notably in harsh automotive environments, but also in other areas such as consumer wearables or remote sensing.  Plasma dicing uses a dry, low damage, chemically-driven etch as a viable alternative to traditional methods of wafer dicing, using mechanical saws or LASER based approaches, which is well-documented to improve die strength.

 This presentation will describe factors that have been investigated to enable successful integration of plasma dicing into existing process routes, such as dicing tape compatibility, optimized laser grooving to prepare dicing streets, and post-dicing surface treatments.  We will also present the latest die strength results from the implementation of plasma dicing already being used in commercial products where device reliability is critical.  Plasma dicing creates devices significantly less susceptible to failure, due to stress fatigue of the silicon, promoting longer service life and reliability, such as those controlling critical safety systems necessary for the broad adoption and consumer trust in vehicle autonomy.

Richard Barnett is Senior Product Manager for Etch Products at SPTS, with over 20 years’ experience in a number of fields in the semiconductor industry. In 2007, he joined what was then Aviza Technology, becoming a part of the etch product management team utilising his background in DRIE processing to help achieve a market leading install base for that technology. He is responsible for the management of SPTS’ Mosaic plasma dicing product line and has written and presented many papers about this disruptive new approach to die singulation. Mr. Barnett graduated from The University of Nottingham in the UK with a Bachelor’s degree in Materials Engineering and Electronics before entering the semiconductor industry.  His roles have bridged the various parts of the supply chain including fab process engineering, wafer supply, equipment vendor process engineer and product management. 



Eelco Bergman, Senior Director Business Development, ASE Group

ase group logo

The electronics industry is transforming our world, significantly driven by semiconductor innovation that is enabling life-changing applications from health to transportation, from virtual reality to AI. Advances in silicon integration technologies are proving truly revolutionary, where multiple die from multiple sources of varying functionality, are being combined to achieve unprecedented performance and operating characteristics. The packaging industry is at the forefront for the enablement of this integration. With a comprehensive tool box leveraging innovative technologies such as 2.5D & 3D die interconnection, high density fan-out, embedded devices, conformal and compartmental shielding, integrated antenna, and more, System-in-Package (SiP) portfolios are constantly being refined and enhanced to support growing demand for next generations of system integration.  During his keynote, Eelco Bergman will describe the expanding application landscape, discuss integration technology innovation, and explore how SiP technologies are delivering on their promise of miniaturization, power efficiency, and highest performance yet.

Eelco Bergman has 35 years of semiconductor packaging industry experience in roles spanning engineering, operations, sales and marketing.  He joined ASE Group early 2014 where he currently serves as Sr. Director of Business Development. Prior to joining ASE, Eelco was Director of Product Marketing for Advanced Interconnect with Global Foundries. He also spent 14 years with Amkor Technology, leading their global business development organization. He started his career with Micron, where he held both engineering and operations management positions.  Eelco has a BS degree in Aerospace Engineering from the University of Michigan (Go Blue!).



Eric Beyneimec fellow, VP R&D, Program Director 3D System Integration, imec

imec logo

Eric Beyne obtained a degree in electrical engineering in 1983 and the Ph.D. in Applied Sciences in 1990, both from the Katholieke Universiteit Leuven, Belgium.  Since 1986 he has been with IMEC in Leuven, Belgium where he has worked on advanced packaging and interconnect technologies.  Currently, he is imec fellow, VP R&D and program director of imec’s 3D System Integration program.  He received the European Semi Award 2016 and the 2019 IMAPS W.D.Ashman-J.A.Wagnon award for contributions to the development of 3D technologies.

Large scale heterogeneous system-on-chip monolithic integration becomes more challenging, technically and economically, with advanced CMOS scaling.  Some individual functions for memory storage or logic still benefit significantly from CMOS scaling, but implementation requirements are diverging. A more optimum solution can be realized using a heterogeneous multi-die integration.  Last year, several companies have adopted and introduced such approach for advanced systems products. The challenges and possibilities of realizing even more deeply partitioned 3D-SOC systems will be discussed.  In particular, the partitioning and 3D stacking of on chip cache as well as novel concepts for direct back-side power delivery at the standard-cell level.  This includes the EDA requirements and progress as well as the advances in wafer-to-wafer bonding down to the sub-µm pitch levels as well as high density ~100nm Ø TSV interconnects for backside power delivery and contact.   



Ruurd Boomsma, CTO, BESI



The drive towards faster response semiconductor devices requiring lower power consumption and yielding higher overall performance coupled with smaller features is continuing and even accelerating, enabling new applications like 5G, AI, Cloud Computing and autonomous driving besides many new applications, which may emerge due to improved semiconductor technology. New packaging technologies like 2.5D, 3D, SIP and Chiplets are becoming now as important as further device shrinking and will become a key enabler for improved overall device performance, new design ideas and new supply chain models. In these new packaging technologies, there is a clear trend towards larger die dimensions, more dense contact schemes as well as more variation in device structures. This has major impact on the required equipment capabilities in the fields of accuracy, die size handling, cleanliness, productivity and flexibility. This presentation will highlight some of the latest developments and limitations in Thermal Compression Bonding for small pitches and larger die sizes. For even smaller dimensions, Direct Cu-to-Cu bonding will be presented. The Wafer-to-Wafer direct Cu-to-Cu bonding process is already being established but may also have limitations. To address a wider range of applications direct Die-to-Wafer or Die-to-Die placement with direct Cu-to-Cu connections can be an attractive solution. New levels of accuracy, placement speeds and cleanliness are key factors for such a process. This presentation will highlight the key issues on how to reach accuracy and speed and cleanliness for this technology. With these new requirements, back-end equipment is moving to front-end specs.

Ruurd Boomsma received a Master Degree in Technical Physics from the State University of Groningen, the Netherlands, in Semiconductor Physics and High Vacuum Technology. He started working in the semiconductor industry in 1984 at ASM in Bilthoven, the Netherlands,  in front end equipment including Epi, Diffusion, PECVD Implant and Litho and was also involved in the sales of the first steppers from ASML (at that time part of ASM). Later on he moved on to MRC, a USA based company for PVD and Etch equipment. Later he became responsible for the Unaxis (Oerlikon) Materials and Display Divisions. He is now over 10 years active at Besi. Initially involved in technology assessment, supply chain optimization followed by holding the responsibility for the Plating Product group and later full responsibility for the Die Attach product group. He is now Besi’s Chief Technology Officer and also responsible for strategic supply chain management and overall quality.



David ButlerEVP and General Manager, SPTS Technologies


David Butler currently serves as Executive Vice President and General Manager at SPTS Technologies with overall responsibility of product management and marketing of SPTS’s portfolio of industry leading etch and deposition process solutions and executive relationships with SPTS’s customers. Previously, David served as VP of product and corporate marketing, overseeing all marketing efforts for SPTS’s full range of PVD, Etch, CVD, and thermal products. With more than two decades of experience in the semiconductor capital equipment and related industries, David first joined Electrotech in 1988 as a Senior Process Engineer, then moved to Product Marketing for Electrotech’s PVD products. In 2004, he assumed the role of Director of Marketing for the PVD/Etch/CVD products at Trikon, becoming Vice President of Marketing for the three product lines at Aviza Technology following the merger of Aviza and Trikon.



Séverine Chéramy3D Business Development and ITR 3D Director, CEA-Leti 

cea leti logo

Séverine Chéramy holds an engineering degree having specialized in material science. She has spent over eight years at GEMALTO, a leading smart-card company developing technologies for secure solutions such as contactless smart cards & electronic passports. In 2008, she joined CEA-Leti as 3D project leader, and then as 3D Integration laboratory manager. This group develops technology and integration for 3DIC, in strong relationship with 3D design, model and simulation teamsSince January 2017, she’s responsible for 3DIC integration strategy and Business development. She is also director of the ITR (Institute of Technological research) 3D program.



Dominique Drouin, Research Chair, University of Sheerbrooke

University of Sheerbrooke

Flip-chip technology is a well-established solution to increase the number of interconnections between a chip and a PCB in high performance computing and other high-end applications. Unfortunately, with large die and high bump density, flux residues cleaning is increasingly challenging. Fluxless soldering is becoming more attractive given that flux residues cleaning step can be avoided leading to an environment-friendly process by reducing water consumption and chemical use. To do so, a hydrogen-based plasma treatment can be used; In fact, hydrogen radicals are known as a reducing agent that can remove the oxide layer from a metal surface.

The plasma treatment used in this study is performed in a vacuum capacitively coupled plasma chamber with a gas mixture containing a percentage of hydrogen. We use large 20 x 20 mm2 chips and associated organic substrates, which bumps (80µm diameter and 185µm pitch) and pads are made of a tin-based lead-free solder. The plasma treatment is done on both the chip and the substrate prior to assembly. Then, soldering is conducted on an industrial-like environment.

Results of plasma treatment development will be presented. We have already successfully demonstrated the assembly of several modules using optimized mass reflow temperature profile. In the idea of process industrialization, re-oxidation kinetic will also be presented to establish potential process window.

Finally, reliability deep thermo-cycling (DTC) tests have been conducted to demonstrate the industrialization potential of this plasma treatment. DTC results tests are going to be presented to show the impact of adding a plasma treatment to a standard flip-chip soldering process on packaging reliability.


Maxime Godard1,2, Maxime Darnon1,2, Serge Martel3, Clément Fortin3, Dominique Drouin1,2

1Institut Interdisciplinaire d’Innovation Technologique (3IT), Université de Sherbrooke, Sherbrooke, Québec, Canada

2Laboratoire Nanotechnologies Nanosystèmes (LN2)—CNRS UMI-3463

3IBM Canada Ltd, 23 boul. de l’Aéroport, Bromont, J2L 1A3, QC, Canada


Prof.  Dominique Drouin is a holder of NSERC/IBM Industrial Research Chair on High-Performance Heterogeneous Integration and professor at the electrical and computer engineering department of the Universite de Sherbrooke since 1999. He received his electrical engineering degree in 1994 and his PhD in mechanical engineering in 1998. He has expertise in the fields of nanoelectronics devices and advanced packaging.



Romain Freux, CEO, System Plus Consulting

System Plus Consulting

In the last few years, computing, radio frequency, power management and sensor applications have driven the advanced electronics packaging market to encompass different sectors. With products such as high-end smartphones, wearables or others connected devices, the advanced packaging market is expected to grow in every sector. Wafer-level packaging (WLP), 3D stacking and SiP (System-in-Package) are key enablers for integration in segments where devices require small form factors, high speed operation and low consumption. Also, cost efficiency is critical. Based on images extracted from teardowns and physical analyses of several consumer mobile devices, we will demonstrate the present power of the latest advanced packaging solutions for manufacturers such as Apple, Qualcomm, Broadcom and others, from the manufacturing cost to the functional integration. We will extract some clues for fifth generation (5G) and millimeter wave (mmWave) applications. We will also present how these companies manage to provide cost-effectively several advanced packaging technologies.

Romain Fraux is the CEO of System Plus Consulting (part of Yole Group of companies), that focuses on Reverse Costing analysis of electronics, from semiconductor devices to electronic systems. Supporting industrial companies in their development, Romain and his team are offering a complete range of services, costing tools and reports. They deliver in-depth production cost studies and estimate objective selling price of a product, all based on a detailed physical analysis of each component in System Plus Consulting laboratory. Romain has been working for System Plus Consulting for more than 13 years and was previously the company’s CTO. He holds a bachelor’s degree in Electrical Engineering from Heriot-Watt University of Edinburgh, Scotland, a master's degree in Microelectronics from the University of Nantes, France and a Master of Business Administration.



Ayad Ghannam, CEO and Founder, 3DiS Technologies

3dis technologies

Nowadays, RF communication modules are integrated in an increasing number of electronic devices. With the tight requirements of 5G applications, these modules need to be compact, high performance, flexible and integrate advanced functions such as active and passive components and antennas. In this talk, we will discuss about how 3D-RDL and recently developed conformal high aspect ratio pre-formed TPVs (thru package vias) for RDL-First type FO-Packages, processed with 3DiS proprietary 3D-RDL within the standard RDL thin film process, answer these requirements thru enabling integration of advanced wafer-level 3D system packages. In particular, we will demonstrate how substrate-based and substrate-less package interconnects and TPVs can be formed cost-effectively using such 3D-RDL technology.

Ayad founded 3DiS Technologies in 2014. He acts as its chief executive officer and also as its chief technology officer. He oversees all products and services development based on 3DiS’s innovative 3D interconnections technologies. Ayad received a Ph.D. degree in electronics engineering, specialty Microwave, Electromagnetism and Optoelectronic, in 2010 from University of Toulouse III, France. During his Ph.D., he worked as a research engineer at Freescale Semiconductors, France branch, and LAAS-CNRS where he designed high-Q power inductors and developed a planar Above-IC process for their integration. After graduation, he continued working in LAAS-CNRS as a research engineer and developed the 3D interconnect process used by 3DiS Technologies.



Daniel Graf, Business Development Manager, 0eC


Daniel Graf is Head of Business Development at 0eC. 0eC presents a revolutionary new way of transporting data based on a physical discovery, discovered by Erez Halahmi and Prof. Ron Naaman from the Weizmann Institute of Science. Mr. Graf is mainly responsible for marketing and investor relations and organises the public presentation of 0eC. Prior to his work with 0eC, he was working in the telecommunication and automotive branch as a system engineer and a freelance IT consultant for more than 10 years, and he has worked in projects for process analysis and customisable system administration. In 2015, he founded a consulting company, Freimuth & Graf Consulting UG, which focuses on methods to build reliable, scalable companies. He has engaged in several startup projects, including AI and app development, where he has implemented agile methods and taken the lead in company building. Through his experience in these projects, Mr. Graf has become an advisor for an investment fund, where he mainly consults in tech investment cases.

In January 2019, he joined ZeroEC as Head of Business Development and started to convert the scientific physical breakthrough that Erez Halahmi’s team have achieved into a startup that will change the fundamental principles of data transfer.


Andreas Grassmann, Senior Director BE Technology, Infineon


More-than-Moore (MtM), System-in-Package (SiP), as well as 3D high-density integration technologies are a prerequisite for enabling the design of advanced compact microelectronic devices. We will present a systematic approach to develop such complex systems. This comprises a co-design methodology that allows a coherent design from chip to board, to optimize chip, package and board interfaces. We highlight the importance of virtual prototyping and reliability prediction, which require detailed understanding of material properties and their interfaces. For design and reliability verification, we show how failure analysis methods can be extended to analyze complex, high-density systems.

Andreas Grassmann is currently senior director for package innovation and as such providing new concepts and approaches for power and logic packages. Before he was in charge for the development of innovative automotive power modules for eMobility. Prior to that  he was had several management positions in development and production of semiconductors for Infineon in US, Europe and Asia for power electronics, advanced logic and DRAM. He holds a PhD in physics from the University of Erlangen.



François Guyader, Senior Member Technical Staff, STMicroelectronics


Image sensors need more and more Partitioning/Architectures/Data Processing capabilities for AI, VR/AR. Parallel Hybrid Bonding versus Sequential stacking 3D technologies are evaluated. Parallel 3D stacking thanks to Hybrid Bonding is a powerful wafer to wafer high-density interconnect technology but could be pitch limited. Sequential stacking should permit further scalable perspectives with sub-micrometer tier to tier connection and why not 3D Pixel Partitioning at Transistor level. These new key enablers could bring significant area reduction and path to innovative sensor architectures.

Graduated from french National Institute of Applied Sciences (INSA) in Physics, François has been working for STMicroelectronics since 1995. Pioneer for the first wafer-level packaged camera, François is now looking at innovative process integrations for the 3D-stacked Image Sensors and has filed numerous patents in this field.



Bernhard Hammerl, Group Leader of Process Engineering, Siconnex

Siconnex logo

What are the biggest challenges for process engineers in the wet area nowadays? I guess all of you have pretty similar things in mind now and yes, all of these points are correct. Shrinking of structure size, increasing wafer size, increasing number of wafers to produce, cleanness of equipment, process stability, wafer uniformity, processing of new material, temperature control and much more …. And these are exactly the problems for which Siconnex has a solution. As the leading provider of BATCHSPRAY® technology, Siconnex offers a wide range of wet process solutions for etching, stripping and cleaning. Due to nearly two decades of experience in wet processing and equipment manufacturing, we are proud to provide not just an equipment for wet process, but also the knowledge how to run it best. With a strong R&D department consisting of process, hardware and software engineers, we achieved bringing our technology to perfection. This presentation now will give you a brief introduction to Siconnex, our equipment and its applications.

Bernhard is Group Leader of Process Engineering at Siconnex in Austria. He is responsible for process research and development.  After four years working as a Process Engineer he took over the Process Engineering Department five years ago.  His focus is on etching, cleaning and stripping processes in batchspray equipment.



Jeroen Hoet, Product Marketing Manager, KLA



  • Executive MBA, Vlerick Business School, Belgium
  • MBA, University of Leuven, Belgium
  • MSc Engineering in Micro-electronics, Electronic systems and Circuits, Ghent University, Belgium


  • Product Marketing Manager, KLA
  • Product Manager, CommScope
  • ASIC Project Leader, ICsense
  • ASIC Design Engineer, ICsense
  • Research Engineer, Alcatel-Lucent



Emilie Jolivet, Semiconductor and Software Division Director, Yole Développement


Emilie Jolivet is Director of the Semiconductor & Software Division at Yole Développement (Yole), part of Yole Group of Companies. Emilie manages the expansion of the technical and market expertise of her team. In addition, Emilie’s mission focusses on the management of business relationships with semiconductor leaders and the development of market research and strategy consulting activities. With its previous collaborations at Freescale and EV Group, Emilie developed a core expertise dedicated to package & assembly, semiconductor manufacturing, memory and software & computing.Emilie Jolivet holds a Master’s degree in Applied Physics specializing in Microelectronics from INSA (Toulouse, France) and graduated with an MBA from IAE (Lyon, France).



Steffen Kroehnert, President and Founder, ESPAT Consulting

espat consulting

Steffen is President and Founder ESPAT Consulting. European Semiconductor Packaging, Assembly and Test (ESPAT) consultancy services: Packaging Technology decision for new applications; Package Design, Bill of Material (BOM) and Process of Record (POR) support; Setup of Supply Chain for prototypes, samples, small series and high volume manufacturing; Technology Trend analysis; Support to Market Researchers; Cooperation with research institutes; Support to relevant industry associations (SEMI, IMAPS, IEEE EPS, SMTA). In the past he covered management roles in AMKOr, NANIUM, Qimonda and Infineon,



Ivan Ndip, Head of RF & Smart Sensor Systems Department, Fraunhofer IZM

Fraunhofer IZM

The millimeter-wave (mmWave) band has been designated to be used for 5G because it offers significantly larger channel bandwidths than the sub-6GHz band. However, mobile communication at mmWave frequencies is challenging, mainly because of channel losses, which reduce the signal-to-noise ratio. To overcome this challenge, new mmWave massive MIMO-based system-architectures with integrated hybrid-beamforming functionalities have been studied by academia and industry. The hardware implementation of these innovative system-architectures requires efficient heterogeneous integration of multiple mmWave components such as antenna arrays, filters, power dividers/combiners, phase shifters, power amplifiers, low noise amplifiers, beamforming ICs and mixers. The packaging platforms used for such integration have significant impact on the performance, cost, reliability and scalability of 5G mmWave systems. In this work, we present new packaging platforms for efficient heterogeneous integration of 5G mmWave antenna arrays, passive and active components. We demonstrate the advantages of the proposed platforms by comparing them, in terms of performance, cost, reliability and scalability, to other 5G packaging platforms in published literature. Furthermore, we illustrate the application of these platforms for the development of 5G mmWave systems.

Ivan Ndip has been with Fraunhofer IZM Berlin since 2000, where he currently leads the Department of RF & Smart Sensor Systems. Since 2008, Ivan has been teaching graduate courses at the Faculty of Electrical Engineering and Computer Sciences, Technische Universität (TU) Berlin. He also teaches Professional Development Courses (PDCs) to practicing engineers and scientists worldwide. Ivan has authored and coauthored more than 200 publications in referred international journals and conference proceedings, and is a recipient of numerous Best Paper Awards. He is also a recipient of the Tiburtius-Prize (Preis der Berliner Hochschulen), awarded yearly for outstanding Ph.D. Dissertations in Berlin. In 2012 he received the Fraunhofer IZM Research Award for his work on the development, and successful application of novel methodologies, models, and design measures (M3-Approach) for optimization of high-frequency and high-speed systems. In 2016, he received the John A. Wagnon Technical Achievement Award from the International Microelectronics Assembly and Packaging Society (IMAPS) for his outstanding technical contributions to the microelectronics industry worldwide. Ivan currently drives research on 5G mobile communication at IZM. He leads numerous R&D projects on the development of 5G mmWave components and modules with European, US and Asian-based Firms. Ivan is a Fellow and Life Member of IMAPS, as well as a Senior Member of IEEE. Since 2016, he has been serving as Director in the IMAPS Executive Board/Council. He is a member of the Technical Program Committee of many IEEE and IMAPS international conferences/symposia. He also serves as a reviewer for many international journals (e.g., Nature Communications, IMAPS and IEEE Journals). Ivan studied Electrical Engineering at TU Berlin. He received the Dipl.-Ing. (M.Sc.) degree, and the Dr.-Ing. degree (Ph.D.) with the highest distinction (summa cum laude) from TU Berlin in 2002 and 2006, respectively. From 2007 to 2017, he pursued the Habilitation, and carried out extensive post-doctoral research on optimized design of miniaturized mmWave and terahertz (THz) systems for future wireless communication and radar sensing applications. His research focused primarily on mmWave and THz antenna configurations; new antenna modeling, measurement and analysis methods; novel high-frequency system-packaging architectures, system-integration structures and technologies as well as on design methodologies for improved signal integrity (SI), power integrity (PI) and intra-system electromagnetic compatibility (EMC). In 2017, he completed the Habilitation, and received the Dr.-Ing. habil. degree (a higher doctorate) in Electrical Engineering from the Brandenburg University of Technology, Cottbus-Senftenberg, Germany.



Markus Leitgeb, Programme Manager Mechanical Integration, AT&S AG


Heterogeneous Integration will need a more holistic “interconnection technology” in the future to form electronic modules at a minimum consumption of speed, space and energy. Large Panel based technologies (PCB, SLP and/or IC Substrate) can offer the integration of a larger number of components in a single module when combined with Chip first (embedding) and/ or Chip last (assembly using Cavities) technologies. Moreover, the existing high-volume manufacturing PCB and substrate infrastructure can be leveraged to a large extent which offers attractive potential for volume scaling.

Markus Leitgeb is an Austrian citizen and holds a Master degree in Polymer Engineering. He has joined AT&S in December 2000 and was responsible to develop an alternative concept for cavities and Rigid-flex solutions, which succeeded in the launch of the 2.5D® Technology. Markus is currently leading the Mechanical Integration Team within the R&D of AT&S, which is developing new concepts for miniaturization and integration of additional functions into PCBs and IC Substrates. Markus holds numerous patents, published several papers and is member of ECTC`s Advanced Packaging Committee.



Amy Lujan, VP of Business Development, SavanSys Solutions LLC


2.5D technology has been a solution on the marketplace for multiple years now, addressing technical challenges that older packaging technologies are unable to meet. However, an advanced packaging solution such as 2.5D generally comes at a price premium. It is generally accepted that, if a more mature packaging technology can meet the technical requirements, that established packaging solution will be more cost-effective. This presentation will focus on the identification and management of cost drivers in scenarios when technical requirements drive the use of advanced packaging. A few years ago, this analysis would have focused only on interposer-based solutions. As technologies have continued to advance, however, fan-out on substrate has been proposed as a solution that will sometimes meet the same requirements as a 2.5D solution. This presentation will take a detailed look at two advanced packaging processes: a solution in which chips are assembled onto an interposer, and that interposer is then assembled onto a substrate, and a solution in which a multi-die, high density fan-out package is assembled onto a substrate. The process flows for each technology will be reviewed, and a detailed cost breakdown will be presented. Key cost drivers will be highlighted, and the sensitivity of the total package cost to each cost driver will be evaluated. The impact of yield will also be analyzed.

Amy received her degree in Chemistry from The College of William and Mary; she is currently VP of Business Development at SavanSys. Prior to joining SavanSys, Amy held positions in business development at TOK America and in engineering at Nokia Japan. In 2006, she received a Fulbright grant to study the cost impact of shifting to lead-free manufacturing.



Moyra McManus, Director, Technology Development Center Europe, ASML


Dr. Moyra K. Mc Manus is the Director of ASML’s Technology Development Center, Europe, and is responsible for the company’s pathfinding exploration in patterning at imec where she leads a team of semiconductor industry experts. Her organization is tasked with understanding ASML’s customer’s long term roadmaps: devices, pitches and patterning options; all investigated in order to better understand future lithography and metrology requirements. Moyra obtained a Phd in Physics and joined IBM Research in 1998 where she worked for 15 years on developing diagnostics techniques for the debug and characterization of 6 generations of enterprise and high performance processors. She led several multi-functional and cross business teams during the development of the Blue Gene supercomputer, which was ranked #1 in the world in June of 2012. She joined ASML in 2015 and has held positions in strategy and marketing before assuming her role with imec for ASML. Moyra has 6 patents and 30 refereed research articles and continues to be interested in the development of HPC systems and their applications.



Laura Mirkarimi, VP 3D Portfolio and Technologies, Xperi Corporation

Xperi Invensas

The promise of high growth markets in the internet of things and artificial intelligence is driving semiconductor manufacturers to increase functionality and performance of devices and modules. With Moore’s law losing steam due to the technical challenges and increasing costs, the electronics industry looks toward 2.5D and 3D stacking to meet the market requirements for future products. A central theme for higher functionality is increased bandwidth and finer pitch interconnects. The challenge to deliver low cost modules with high yield remains difficult. The inability for the incumbent interconnect technologies to deliver a solution for the next generation packages lowers the barrier for new technology adoption. The new technology platform that the semiconductor industry is betting on is hybrid bonding.

Direct Bond Interconnect (DBI®) and DBI® Ultra are low-temperature wafer to wafer (W2W) and die to wafer (D2W)bonding technologies that reliably achieve interconnect pitches scaled to 2 µm. While DBI technology has been in high volume manufacturing for several years in W2W applications, a die to wafer process is currently in development across the semiconductor industry. The availability of the D2W technology will enable the fine pitch interconnect to become pervasive in electronics.

This paper explores the compelling value of DBI technology for a wide variety of applications including image sensors, displays, memory storage, and new heterogeneous applications. The salient features of this technology and the application advantages they offer will be outlined. Specifically, the technical advantages of hybrid bonding over conventional Cu-Cu and solder, thermal compression bonding will be discussed. Widespread disaggregation combined with chiplet architecture innovation offer enhanced performance with cost reduction through enhanced time to market and leverage of legacy designs where appropriate. The cost reduction advantages for adopting this DBI platform technology for system on chip (SoC) and memory applications include room temperature bonding at speeds comparable to a mass reflow flip chip assembly, followed by a low temperature final anneal temperature to form the all Cu-Cu interconnect.

The D2W and W2W test vehicles include either large DBI pads (10um to 15um) or small DBI pads (1.9um to 3.9 um) with a single daisy chain device ranging from 30k to 500k links. The bond quality of the device is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-sectional microscopy analysis. Electrical test yield, temperature cycling and highly accelerated stress test (HAST) data are reported and compared to examples from the literature.

Laura Mirkarimi obtained her PhD in Materials Science at Northwestern University. She joined Hewlett Packard Laboratories in 1993 in the Solid State Technology Laboratory and worked in ferroelectric memories, transparent optical conductors for displays and photonic crystals for all optical circuits building single molecule detectors. In 2005, she joined Tessera Technologies to begin her packaging career working on wafer level packaging, Cu pillar and PoP where she lead the Design, Simulation and Reliability groups. In 2015, she joined Zeiss Microscopy Division as their VP and Electronics Segment Marketing Manager. She returned to Tessera, now Xperi, in 2016 as VP of 3D Portfolio and Technology where she leads the engineering team to further develop hybrid bonding for both wafer to wafer and die to wafer applications.



Jawad Nasrullah, Co-founder, President and CTO, zGlue


Designing custom chips and systems with chiplets requires special architecture and design methods to achieve yield and reliability given the heterogeneous nature of components. Incoming chiplets or known good dies need to have characterization and testing in place by the supplier that guarantees quality and reliability at a level similar to packaged parts. One way to achieve such incoming component quality is to use chiplets produced in wafer-level chip-scale packages. System-level testing of the final assembly is generally broken into three buckets, a) tests for the assembly failures, b) tests for functionality and c) tests for reliability. zGlue Smart Fabric, an active silicon interposer, enables rapid development of systems-in-package and chips using chiplet stacking in a modular style and also incorporates a built-in self-test (BIST) scheme for debug and production. We will present the scheme for BIST and a repair mechanism to provide coverage for the assembly process followed by the reliability testing methodology used in the system production.

Dr. Jawad Nasrullah is the co-founder and CTO of zGlue Inc, a Silicon Valley technology startup commercially offering chiplet-based designs on active silicon interposers. As an expert in low-power designs for 3D-ICs, Dr. Nasrullah's career has spanned a number of roles at some of the top technology companies including Intel, Sun Microsystems and Transmeta Corporation among others. He earned his Ph.D. in electrical engineering from Stanford University, holds several US patents and is the recipient of a number of national and institutional awards.



Eoin OToole, Technology Development Manager, Amkor Technology Inc.

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FanOut wafer level packing has been shown to be extremely flexible with respect to single die, multiple die and heterogeneous integration of a variety of different die technologies and SMD types. With increasing competition between the different wafer level FanOut technologies this presentation aims to compare the applicability of different wafer level FanOut technologies to different application spaces focusing on advanced wafer level System in Package (SiP). Requirements of some of the different wafer level FanOut technologies, for example the necessity for copper pillar structuring in the incoming wafer for FaceUp FanOut wafer level technologies or RDL first with subsequent thermocompression / reflow assembly for high density technologies such as Swift or Info create restrictions on the application space where the technologies may be used. In terms of the different applications in which FanOut wafer level packaging is being employed different the different FanOut wafer level packaging technologies have been used in a wider variety of applications than others while other FanOut wafer level packages lay claim to improved reliability performance. For particularly demanding applications such as safety critical automotive AEC Q100 grade 1 or grade 0 applications the traditional choice has been and continues to be the Low Density FanOut technology developed by IFX as eWLB. Some examples will be shown of the reliability performance in automotive applications as well as optimizations possible through layer thickness adjustment and solderball alloy selection.

Eoin OToole is a the Technology Development Manager in the R&D department of Amkor Technology Portugal
Originally from Dublin Ireland where he obtained his primary and master degrees in material science from Trinity College Dublin.



Rafael Santos, Process Developer, LPKF


Currently, one of the most interesting materials for novel advanced packaging applications is glass. Its RF properties, tunable CTE, hermeticity and low cost, make glass a highly sought-after material with the potential to substitute various costly and often non-optimal materials in current semiconductor industry processes. The main hindrance in the widespread use of glass has been its processability: current processing technologies show limited capabilities and induce micro-cracks and internal stresses, while often being associated with high cost. Laser Induced Deep Etching (LIDE) is a high throughput glass processing technology capable of creating high quality and high aspect-ratio micro features, without impacting the properties of glass. In this talk, we will introduce the fundamental aspects of LIDE technology, show examples of its unique capabilities and a new application of glass in Fan-Out Packaging.

Rafael Santos studied Materials Engineering at NOVA in Portugal and graduated in 2011 as a MSc. After two years working as a research fellow in the field of thermoelectrics, he was offered the opportunity to do a doctoral thesis on the development of thermoelectric materials in Wollongong, Australia, which was he completed in September 2019. In the same month, Rafael joined LPKF Laser & Electronics AG, in Garbsen, Germany, as a Process Development Engineer for the Laser Induced Deep Etching (LIDE) technology.



Dan Smith, 3D Packaging Integration Engineer, GlobalFoundries


The advancements of wafer bonding technology are opening up new possibilities for 3D applications to complement traditional fab technology node scaling. With wafer bonding offering a z-axis direction of integration, new 3D SoC architectures achieve benefit from enhanced performance while helping to reduce overall product footprint. Thus is the need to develop world-class process and reliability controls to enable the multitude of wafer bonding offerings. This presentation will delve into the varied technological drivers for wafer bonding and cover the latest developments that GLOBALFOUNDRIES is currently achieving.

Daniel Smith received his B.S. degree in Computer & Electrical Engineering from Georgia Institute of Technology in 2004, and his M.S. degree in Microelectronic Engineering from Rochester Institute of Technology in 2012. From 2004 to 2010, he was an Electrical Engineer with Phillips-Gradick Engineer and Merrick & Company working on architectural and construction electrical design.  During graduate school from 2010 to 2012, he worked as Research Assistant on integrated multi-device MEMS fabrication and testing.  Since 2012, he is working as a Process Integration Engineer with GLOBALFOUNDRIES in the Malta, NY fab.  His focus is with TSV and the Hybrid Bond Module Terminal module integration and process development for both manufacturing readiness and scaling at the advanced nodes (28/22/14nm).  In addition, he works with 3D-CPI, bumping processing, and packaging reliability for overall 3D packaging applications for die stacking and wafer bonding assembly.



Franz Schrank,Senior Manager, AMS

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Franz Schrank ‘Senior Manager Process R&D’ at ams AG. He has 19 years of experience in 3D integration, CMOS post processing and MEMS. Franz received the Dipl.-Ing. degree in physics and the M.A.S. degree in Nanoelectronics and Nanoanalytics at the University of Technology in Graz, Styria, Austria. He currently holds 34 patents in the field of 3D technology, MEMS and opto technology. 



Jerome Serrand, Packaging Technical Manager, JSR Micro

Packaging Technical Manager, Jerome joined JSR in 2002. Located near Grenoble, the French Silicon Valley, from where he can give full technical support to many different key customers in Europe. Keeping close contact with the R&D department in Japan and Belgium, he manages and supports several on-going projects at different European customers.



Joerg Siegert, Manager 3DWLI, AMS AG

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ams AG is a leading provider of sensor solutions in a wide variety of fields, with optical sensing as one of the key competences. 3D processes, heterogeneous integration and combination with photonics are paving the way for the development of novel sensor solutions. We will present examples for sensor with optical readout based on silicon nitride photonic circuits monolithically integrated with CMOS. One of the applications is optical coherence tomography (OCT), a fast growing imaging technique in ophthalmology. Drawbacks of existing OCT systems are their high costs as well as their bulkiness, which prevents wider spread of OCT systems. To overcome both cost and size issues, optical and electrical components are integrated on a single chip. Moreover, we will also present an example of an opto-chemical gas sensor.

Joerg Siegert has worked on 3D and heterogeneous integration at ams AG, Austria, for over ten years and is currently managing the Process R&D team reponsible for 3D interconnect and wafer level integration development. He studied at Graz University of Technology, Austria, and KTH Royal Institute of Technology, Stockholm, Sweden, where he got his PhD degree in physics. Joerg is author and co-author of 17 publications and hold 15 patents in the fields of 3D integrated semiconductor devices and MEMS.



Steven Steen, Director DUV 3D Memory and Application Product Management, ASML


Steven Steen is director of Product Management at ASML. In this role he is responsible for the 3D Memory product portfolio at ASML. He studied at the Hogeschool Enschede and started his career at IBM’s T.J. Watson Research Center during the final stages of his education. Leading edge innovation is the consistent thread during his 20 years’ experience in semiconductor R&D (of which 15 in lithography). Steven joined IBM in 1997 to develop and commercialize full chip timing diagnostics through Picosecond Imaging Circuit Analysis. In 2001, Steven joined the microelectronics research line and started his career in lithography there. During a wide variety of roles he worked to realize numerous device technologies and business opportunities. He moved to the Netherlands and joined ASML in 2012 to lead the definition and development of lithography innovations and unique product offerings to ASML’s customers. As director of product management his focus is on unique offerings to enable the continued innovation for the semiconductor industry. Holder of over 23 US Patents and 39 published research papers, Steven continues to think of new applications and the challenges of the future. Outside of work he is often found near the water for sailing, swimming or other forms of water sports.



Dr. Valeriy Sukharev, Technical Lead, Mentor Graphics

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Potential challenges with managing mechanical stress and temperature and the consequent effects on device performance for advanced three-dimensional (3-D) IC technologies are outlined. The growing need in a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress and temperature-induced variations in MOSFET/FinFET electrical characteristics and interconnect crack initiation and propagation are addressed. A developed physics-based model and a multi-physics EDA tool-prototype analyze thermal, and thermo-mechanical problems during package assembly and chip operation. An implemented link between layout analysis tools and the multiphysics thermal mechanical tool enables to perform reliability check within the design flow for optimizing the floorplan for different circuits and packaging technologies, and/or for the final design signoff. A calibration technique based on fitting to measured electrical characterization data is presented, along with correlation of the electrical characteristics to direct physical strain measurements. The limited characterization or measurement capabilities for 3-D IC stacks and a strict “good die” requirement make this type of analysis critical in order to achieve an acceptable level of functional and parametric yield.

Valeriy Sukharev is a Technical Lead with the Design to Silicon Division (Calibre), Mentor, a Siemens Business, Fremont, CA, USA. He has received the Engineer-Physicist Diploma degree in microelectronics from the National Research University of Electronic Technology (MIET), Moscow, Russia and Ph.D. degree in Physical Chemistry from the Russian Academy of Sciences. Prior to Mentor Graphics, Dr. Sukharev was a Chief Scientist with Ponte Solutions, Inc., a Visiting Professor with Brown University, and a Guest Researcher with NIST, Gaithersburg, MD. He also held senior technical positions with LSI Logic Advanced Development Lab.  Dr. Sukharev was a recipient of the 2016 & 2019 Best Paper Award from the International Conference on Computer-Aided Design (ICCAD) and the 2016 & 2018 Mahboob Khan Outstanding Industry Liaison/Associate Awards (SRC). His current research interests include development of new full-chip modeling and simulation capabilities for the electronic design automation, semiconductor processing and reliability management. He serves on the editorial boards and technical/steering committees of a number of profiling journals and conferences.



Silke Traut, Technology Management, Dectris AG


In recent years 3D technologies have been implemented in process flows for many industrial applications, such as image sensors and high density memory devices. For X-ray and electron detectors, however, this is still in a development phase. Currently commercially available large area hybrid photon counting detectors exhibit a grid of pixel gaps throughout the detector`s active area. Providing fully active sensing areas by implementing 3D technologies will allow the hybrid photon counting technology to expand into new markets, such as electron microscopy or medical imaging. We will explore the differing requirements for the variety of applications along with their technological challenges.

Driven by technologies, Silke Traut has worked in research and development closely linked to production for the past 20 years. After 12 years in semiconductor industry, she joined Dectris in 2011 heading different engineering and production teams. Since 2018, she has been focusing on technology project management. Silke Traut received her BSc. degree in applied physics from the University of Applied Sciences in Lubeck, Germany and her MSc. in applied physics from the University of Massachusetts in Lowell, USA.



Jan Vardaman, President and Founder, TechSearch International, Inc.

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Driven by performance, 3D packaging has become a reality for memory and advanced logic.  Image sensors have been in production for many years with Sony’s high volume production of three-layer image sensor, DRAM, and logic in 2017 and Samsung’s three-layer stack in 2018.  In the last 10 years, High Bandwidth Memory (HBM) has transitioned from a handful of research programs to rapidly increasing volumes.  While logic and memory stacks have remained elusive, Intel and TSMC have introduced new packaging technology with active interposers that are considered 3D and Samsung has 3D SiP on its latest roadmap. Intel has introduced its Foveros 3D integration technology as a form of heterogeneous system integration.  The technology uses a 3D face-to-face stacking process. TSMC has introduced its SoIC with face-to-face stacking and wafer-on-wafer (WoW).  These technologies represent a new era in 3D packaging.  This presentation discusses the latest trends in these new 3D packages and the impact on the industry.    

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided market research and technology trend analysis in semiconductor packaging since 1987.  She is the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and is an IEEE EPS Distinguished Lecturer.  She is a member of SEMI and IMAPS.  She received the IMAPS GBC Partnership award in 2012 and the Daniel C. Hughes, Jr. Memorial Award in 2018.   She is an IMAPS Fellow.  Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.     



Thomas Uhrmann, Director of Business Development, EV Group

EV Group

Dr. Thomas Uhrmann is director of business development at EV Group (EVG) where he is responsible for overseeing all aspects of EVG’s worldwide business development. Specifically, he is focused on 3D integration, MEMS, LEDs and a number of emerging markets. Prior to this role, Uhrmann was business development manager for 3D and Advanced Packaging as well as Compound Semiconductors and Si-based Power Devices at EV Group. He holds an engineering degree in mechatronics from the University of Applied Sciences in Regensburg and a PhD in semiconductor physics from Vienna University of Technology.



Bernd Waidhas, Principal Engineer Package Architecture, Technology Enablement Group, Intel

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Bernd Waidhas is Principal Engineer for package architecture in Technology Enablement Group of Intel in Munich. He works on definition, development and characterization of advanced package types from external suppliers. He starts his business career at Siemens Semiconductors, later Infineon, in 1996, where he was working in several positions in package development such as package concept engineer and package project manager mainly for wireless products and package platform owner responsible for Fine Pitch BGA roadmap. He joints Intel with the acquisition of Infineon’s Wireless Solutions Business in 2011. Bernd holds a master’s degree in electrical engineering from the Technical University Dresden. He has been granted more than 15 patents and several additional patents pending.



Markus Wimplinger, Corporate Technology Development and IP Director, EV Group

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As Moore’s law is running out of steam, advanced packaging has taken leadership to drive performance. On the one hand, the die area is constantly reduced especially for small package sizes and heterogeneous integration with high interconnect density becomes crucial. This is for example the case in IoT or mobile applications. On the other side, for large packages sizes heterogeneous integration and die segmentation gets an increasing role of processing applications. Here, heterogeneous integration leads to an overall increased yield, mainly as smaller dies generally can be produced with higher yield. In the same time and most importantly, memory, processors, sensors and such from different sources can be combined using heterogeneous integration. Determined by the final application and device design, fusion and hybrid bonding by means of D2W or W2W needs to be implement. Understanding the differentiators of both processes and technologies is crucial. In this presentation we will give an update on current state of the art wafer to wafer fusion and hybrid bonding. Furthermore data on collective D2W bonding will be presented during the summit.

Markus Wimplinger is the Corporate Technology Development and IP Director at EVG. In this role, Markus oversees EV Group’s global Process Engineering team. His further responsibilities include the management of R&D partnerships and contracts with 3rd party organizations such as companies or government related entities, as well as Intellectual Property affairs associated with EVG’s process technology development efforts. Markus received his educational background in Electrical Engineering from HTL Braunau, Austria. He started with EV Group as a project manager at the company’s headquarters in Austria in 2001 with focus on customer projects. In 2002, Mr. Wimplinger transitioned to EV Group North America in Tempe, Arizona, USA, where he served as the Director Technology North America till August 2006. Mr. Wimplinger’s past work includes involvement in design, development, process technology and many other aspects of capital equipment production at both EV Group and at his former job with a capital equipment supplier for non-semiconductor related industries.



M. Jürgen Wolf, Head of Division Wafer Level System Integration - WLSI / Managing Director IZM-ASSID, Fraunhofer IZM

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M. Juergen Wolf received a M.S. degree in Electrical Engineering from the Technical University Chemnitz in 1979.  After gaining fundamental experience in the industry for several years, he joined the faculty Microperipheric Technologies at the Technical University Berlin in 1990. Here, he was mainly involved in the development of wafer level packaging processes, the development of flip chip multi-chip modules, RF modules and high density pixel detector modules.

In 1994 M. Juergen Wolf changed to Fraunhofer Institute for Reliability and Microintegration IZM Berlin and worked as a group & project manager in the department HDI&WLP in the field of wafer level packaging and system in package (SiP). He was especially responsible for the development, coordination and implementation of new technologies for wafer level packaging and system integration. From 2000 until 2010 he additionally took over the position of personal assistant for the director of Fraunhofer IZM - Prof. Dr.-Ing. Dr.-Ing. E.h. Herbert Reichl.

Starting in 2009, he was coordinating and planning and realization of the new center - All Silicon System Integration Dresden – ASSID of Fraunhofer IZM. Under his leadership a full industrial compatible process line for Wafer level Packaging and 3D integration was established. Since 2011, he is head of the department “Wafer Level System Integration” and also continued managing the center “ASSID” featuring a 200/300 mm 3D wafer level integration line. He is also actively involved in a number of research projects on national, European and international level.

M. Juergen Wolf is a member of IEEE and SMTA and among others, a longstanding member and European representative in different technical international packaging roadmap groups e.g. the Jisso International Council (JIC) and formally TWG of Assembly & Packaging of the International Roadmap of Semiconductors (ITRS) and now the Heterogeneous Integration Roadmap (HIR) where he is actively contributing to the definition of new roadmaps. Since 2016 Wolf is a member of the advisory board of 3D Incites (

Wolf is one of the initiators and co-chair of the Fraunhofer Cluster 3D Integration which was established in 2013 and comprises 5 Fraunhofer institutes. He has also initiated the annual 3D European Summit Conference where he is a member of the steering committee. He has authored and co-authored numerous scientific papers presentations and reports in the field of microelectronic packaging and holds a number of patents.



Jean-Marc Yannou, Senior Technical Director, ASE Europe

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Jean-Marc Yannou started his career as a Test & Product Engineer at Texas Instruments, first in France then in the USA. He then joined Philips Semiconductors (now NXP) as principal engineer where he managed the company’s initiatives in System-in-Package technologies. Next, he became a senior consultant and market analyst on advanced semiconductor packaging technology for Yole Développement, a market research consultancy. Jean-Marc joined ASE Group in 2012 where he serves as a Technical Director for Europe. Along with his professional activities, Jean-Marc served as chairman of the France chapter of IMAPS (International Microelectronics and Packaging Society) from 2010 to 2014.



Doug Yu, VP of Integrated Interconnect & Packaging, TSMC


Dr. Douglas Yu is TSMC’s Vice President of Integrated Interconnect &Packaging, responsible for research and development of advanced packaging and system integration solutions. Prior to his appointment to Vice President in 2016, Dr. Yu was Senior Director of the Integrated Interconnect & Packaging Division. Dr. Yu joined TSMC in 1994, serving in a variety of roles throughout his career including backend R&D, and developed technologies critical to the Company’s highly successful transition to copper process at the 0.13 micron generation. Dr. Yu also pioneered TSMC’s wafer-level system integration technologies, including Chip on Wafer on Substrate (CoWoS® ), Integrated Fan-Out (InFO), and System on Integrated Chips (SoICTM), as well as their derivatives. Dr. Yu became a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2013, and received the Presidential Science Prize of Taiwan in 2017 as well as the IEEE EPS Outstanding Manufacturing Technology Award in 2018. He has received more than 1,800 worldwide patents, including 950+ US patents, while serving at TSMC.




  • Jonathan Abdilla - Besi
  • Eric Beyne - IMEC
  • David Butler - SPTS Technologies
  • Severine Cheramy - CEA-LETI
  • Luke England -Marvell Technology Group 
  • Andreas Erhart  - Evatec
  • M. Juergen Wolf - Fraunhofer IZM
  • Steffen Kroehnert - ESPAT Consulting
  • Hugo Pristauz - Bluenetics
  • Thomas Schmidt - SUSS MicroTec
  • Franz Schrank -  ams AG
  • Thomas Uhrmann - EV Group
  • Bernd Waidhas - Intel Europe


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