Setting the Stage: Industry Drivers & SCC Initiative Context
• Semiconductor Industry Decarbonization Challenges
• The Need for Quantified Business Cases
• SCC Initiative Background & Development Journey
• Vision for Industry Adoption & Collaboration
• Tool Architecture & Methodology
• Key Inputs & Assumptions
• Understanding the Outputs & Metrics
• Live Demonstration & Example Scenario
• Current Limitations & Future Development Opportunities
9:36 am
-
9:50 am
Jeff Rudnik
Director of Environmental Sustainability & Net Zero
ASM
Industry Use Cases & Practical Applications
• Evaluating Decarbonization Projects
• Comparing Alternative Mitigation Strategies
• Supporting Internal Investment Decisions
• Lessons Learned from Early Applications
• Opportunities for Industry Collaboration
The semiconductor industry is under increasing pressure to decarbonize its operations, particularly with regard to Scope 1 emissions — direct greenhouse gas emissions (GHG) from owned or controlled sources. Yet many companies face a persistent challenge: how to make a clear, consistent, and financially credible case for emissions reduction investments. To help address this need, the Semiconductor Climate Consortium (SCC) has developed a Cost-Benefit Calculator — a simplified and flexible tool that offers a structured starting point for evaluating carbon emissions reduction projects. The calculator enables users to estimate the Net Present Cost (NPC) per ton of CO₂ equivalent emissions reduction, helping to translate environmental impact into business-relevant terms.
Join the SEMI's Semiconductor Climate Consortium (SCC) Scope 1 Working Group and document authors for a webinar discussing their journey creating the Cost-Benefit Calculator and outlining the use cases for this tool. The Cost-Benefit Calculator is a functional spreadsheet with built in report creation tools. For business managers who need to calculate emissions for Scrope 1.
Building the business case for emission reductions
9:00 am - 10:00 am
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Add to Calendar2026-06-16 09:00:002026-06-16 10:00:00SCC: Cost Benefit Calculator WebinarThe semiconductor industry is under increasing pressure to decarbonize its operations, particularly with regard to Scope 1 emissions — direct greenhouse gas emissions (GHG) from owned or controlled sources. Yet many companies face a persistent challenge: how to make a clear, consistent, and financially credible case for emissions reduction investments. To help address this need, the Semiconductor Climate Consortium (SCC) has developed a Cost-Benefit Calculator — a simplified and flexible tool that offers a structured starting point for evaluating carbon emissions reduction projects. The calculator enables users to estimate the Net Present Cost (NPC) per ton of CO₂ equivalent emissions reduction, helping to translate environmental impact into business-relevant terms.Join the SEMI's Semiconductor Climate Consortium (SCC) Scope 1 Working Group and document authors for a webinar discussing their journey creating the Cost-Benefit Calculator and outlining the use cases for this tool. The Cost-Benefit Calculator is a functional spreadsheet with built in report creation tools. For business managers who need to calculate emissions for Scrope 1.SCC members can download the Cost Benefit Calculator Report here.SEMI United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
Register Today!
Designing functionally correct, high-performance, and provably secure system-on-chips (SoCs) has become a strategic imperative for modern computing infrastructure. Yet traditional design and verification methodologies are increasingly strained by escalating complexity, massive design scales, heterogeneous integration, and rapidly evolving security threats. Ensuring correctness, scalability, comprehensiveness, and adaptability across the full SoC lifecycle now exceeds the practical limits of conventional toolchains and human-centric workflows.
The emergence of large language models (LLMs) introduces a transformative opportunity for SoC design automation. Beyond natural language understanding and code generation, advanced LLMs demonstrate capabilities in architectural reasoning, specification refinement, vulnerability analysis, and design-space exploration. However, monolithic models alone are insufficient for the multidisciplinary and iterative nature of chip design. An agentic paradigm—where specialized LLM-driven agents collaborate within a coordinated framework—enables modular reasoning, cross-layer verification, security validation, and adaptive decision-making throughout the design process.
This talk will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification. The framework integrates design synthesis, threat modeling, formal reasoning, runtime monitoring strategies, and hardware–software co-verification into a cohesive workflow. Looking ahead, such agentic systems point toward a future of self-optimizing, security-aware, and continuously verified silicon—where AI-driven design environments not only accelerate innovation but also fundamentally redefine how we conceive, build, and trust next-generation microelectronic systems.
United States
9:00 am
-
9:10 am
Warren Savage
Researcher
University of Maryland Applied Research Laboratory for Intelligence and Security
This webinar will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification.
ESD Alliance Webinar: Gen-AI for Chip Design and Security
A Look Into the Future
9:00 am - 10:00 am
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Add to Calendar2026-09-10 09:00:002026-09-10 10:00:00ESD Alliance Webinar: Gen-AI for Chip Design and SecurityThis webinar will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification.United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
Register Now
This workshop explores how advanced packaging is redefining the trajectory of Moore's Law. Participants will gain insight into cutting-edge approaches, such as heterogeneous integration and chiplet architectures, that enable continued performance growth beyond traditional scaling limits.
We will delve into key packaging, including wafer-level packaging, fan-out wafer and panel-level solutions, 3D integration, and embedded packaging- highlighting how each enhances transistor density and system performance, along with the associated technical challenges. The session will also cover next-generation interconnect and bonding techniques, including thermocompression and hybrid bonding used in advanced die-stacking solutions such as SoIC-X and SoIC-P.
In addition, the workshop will examine evolving interposer architectures (2.1D, 2.3D, 2.5D, and beyond), including platforms such as CoWoS-S, CoWoS-L, and CoWoS-R. It will also explore emerging interposer materials like glass substrates, covering their benefits, fabrication processes, technical challenges, and supply chain landscape in supporting the continued evolution of Moore's Law.
Who Should Attend
This course is intended for both manufacturing and R&D know-how in IC packaging professionals, including but not limited to:
Directors
Managers
Process Engineers
R&D Engineers
Sales and Application Engineers who supply packaging materials and tools
Learning Objectives
Understand the principles in the evolution of IC packaging and how the semiconductor industry has evolved with time.
Understand the principles of Interconnections ranging from TAB, and Wirebond to various Flip Chip bonding, such as thermocompression bonding with NCP, C4, ACF for manufacturing and R&D development.
Review the interposer of leadframe, ceramic, flex to BT substrates for Microelectronics packaging.
Explain the assembly flow and new assembly techniques from backgrinding to singulation.
Describe the material characterization from bulk to interfaces to reduce stress and enhance interfacial adhesion for reliability enhancement.
Course Topics
Advanced packaging and material characterization.
Packaging principles and how packaging evolves into heterogeneous packaging.
Packaging concepts such as Fan-in, Fan-out WLP, Embedded packaging technology, 3D packaging, TSV.
Wirebond and Flip chip interconnect technologies inclusive of interposer technologies, such as leadframe, ceramic, flex and substrate.
Assembly processes from backgrinding to singulation for QFP and FBGA packages.
Material characterization to select materials to reduce stress and strengthen the interface for reliability enhancement.
Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access course knowledge.
Can't find the training link day of? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders about 24 hours in an advance and an hour before with the same link. Please keep these emails on hand to access the trainings on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.
As transistor scaling slows under the physical limits of lithography, the semiconductor industry is entering a new era-one where innovation is driven not just by node shrink, but by how chips are integrated and packaged.
Pricing
Members: $599
Non-Members: $649
* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected].
Reshaping Moore's Law with Advanced Packaging
Virtual Training - Asia & EU
8:30 am - 5:00 pm
Off
Add to Calendar2026-08-03 08:30:002026-08-03 17:00:00Reshaping Moore's Law with Advanced Packaging (Asia)As transistor scaling slows under the physical limits of lithography, the semiconductor industry is entering a new era-one where innovation is driven not just by node shrink, but by how chips are integrated and packaged.PricingMembers: $599Non-Members: $649* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected]. SingaporeSEMI.org[email protected]Asia/Singaporepublic
Asia/Singapore
Register Now
This course will stress the impace of the IC and End product requirements, i.e., smaller, better, cheaper" and their influence on the manufacturing processes. Topics include area packaging - ball grid arrays, flip chip, fanout, attaching dies and chip scale packages, and the assembly technologies - chip & wire, tape automated bonding, and flip chip, as well as emerging technologies, namely, 3-D and stacked die, and packaging reliability issues.
Who Should Attend
This course is intended for both manufacturing and R&D know-how in IC packaging professionals, including but not limited to:
Engineers
Managers
Process Engineers
R&D Engineers
Sales and Application Engineers who supply packaging materials and tools
Learning Objectives
Identify the wide variety of package types and how they align with different application uses.
Understand chip interconnection technologies (such as wirebond, flip chip, or thin film) and chip encapsulation
Identify the materials and processes used in packaging.
Summarize the current state of the art packages, such as chiplets and heterogeneous packaging.
Gain a foundational understanding of what packaging is and its importance to the microelectronics industry.
Important Information
Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access the course knowledge.
Can't find the training link on the day of? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders about 24 hours in advance and an hour before with the same link. Please keep these emails on hand to access the training on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.
This comprehensive course will cover the underlying fundamentals, the interrelationship between materials and processes, and the hardware used in printed electronics. The masterclass will also explore how printed electronics can be applied currently in example applications including practical aspects of the technology, its highlights and challenges and scalability. We will also explore emerging new technologies at the cutting edge of FHE, semiconductor packaging, photonics and quantum materials. Throughout the course there will be opportunities for Q/A and discussions and case studies based on participant's interest.
ABOUT THE SPEAKER
J. Devin MacKenzie, PhD Dr. Devin MacKenzie is the Washington Research Foundation Professor and an Assoc. Prof. of Materials Science and Engineering and Mechanical Engineering at UW. He is also the Technical Director of the Washington Clean Energy Testbeds, a lab that provides open-access to world-class advanced manufacturing and characterization tools for printed optoelectronics, sensors and energy device research and scale-up. Devin also has 25 years of entrepreneurial experience in sustainable materials and manufacturing of semiconductors, optoelectronics and energy devices. Prior to UW he was CEO and co-founder of printed battery company, Imprint Energy (acquired CCL/Avery), Previously, as the CTO of Add-Vision, Inc. (acquired Sumitomo Chemical), Dr. MacKenzie led R&D for roll-to-roll printed flexible OLEDs at Add-Vision with licensing in Europe and Asia. Prior to Add-Vision, he led printed silicon RF device and product engineering at Kovio, Inc. a Si Valley MIT spin-out (acquired Thin Film Electronics). Dr. MacKenzie also co-founded, Plastic Logic, from Cambridge University as a postdoc and subsequently a visiting scientist in Physics at the Cavendish Laboratory. Prior to that he worked at Bell Labs and NASA. Dr. MacKenzie has authored over 240 publications and patents that have been licensed globally and has been cited over 12,900 times in fields ranging from rare earth-doped nitrides to quantum materials. He holds Ph.D, MS, and undergraduate degrees in Materials Science and Engineering from the University of Florida and the Massachusetts Institute of Technology.
United States
J. Devin MacKenzie, PhD
Washington Research Foundation Professor of Clean Energy, Associate Professor
Join us for a comprehensive Master Class with Dr. Devin MacKenzie, as he dives into the fundamentals and real-world applications of printed and flexible hybrid electronics (FHE). This session will explore the critical interrelationship between materials, processes, and hardware used in printed electronics, providing a strong foundation for understanding how these systems are designed and manufactured.
Participants will gain insight into current applications of printed electronics, along with practical considerations such as performance, scalability, and manufacturing challenges. The course will also highlight emerging technologies at the forefront of innovation, including advances in FHE, semiconductor packaging, photonics, and quantum materials
Advancing Printed Electronics Technology: From Macroelectronics to Quantum Devices
Flexible Electronics Master Class #31
10:00 am - 12:00 pm
Off
Add to Calendar2026-09-30 10:00:002026-09-30 12:00:00FEMC#31 Advancing Printed Electronics Technology: From Macroelectronics to Quantum DevicesJoin us for a comprehensive Master Class with Dr. Devin MacKenzie, as he dives into the fundamentals and real-world applications of printed and flexible hybrid electronics (FHE). This session will explore the critical interrelationship between materials, processes, and hardware used in printed electronics, providing a strong foundation for understanding how these systems are designed and manufactured.Participants will gain insight into current applications of printed electronics, along with practical considerations such as performance, scalability, and manufacturing challenges. The course will also highlight emerging technologies at the forefront of innovation, including advances in FHE, semiconductor packaging, photonics, and quantum materialsUnited StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
REGISTER NOW
This course provides a comprehensive introduction to semiconductor manufacturing, guiding participants through the complete journey from silicon fundamentals to chip fabrication and packaging. Designed for professionals new to the semiconductor industry, the course explains key concepts, terminology, devices, and manufacturing processes used in modern fabs.
Who Should Attend
Anyone interested in understanding semiconductor manufacturing, including new employees, professionals in related industries, and those seeking to broaden their knowledge of the field.
Learning Objectives
Upon completion of the course, participants should be able to:
Explain fundamental semiconductor concepts, including silicon materials, doping, PN junctions, and basic device behavior.
Identify and correctly use common semiconductor manufacturing terminology.
Outline the key steps involved in front-end wafer fabrication, from bare silicon to patterned wafers.
Summarize back-end manufacturing processes, including assembly, packaging, and testing.
Topics Included
Basic Electronics and Microelectronics
Process Nodes
Device Physics and Transistor Operation
Crystal Growth and Wafer Preparation
Advanced Transistor Technologies
Circuit Design and Layout
Wafer Processing
Important Information
Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access the course knowledge.
Can't find the training link on the day of the training? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders 24 hours in advance and 1 hour before, with the same link. Please keep these emails on hand to access the training on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.
Strengthen your knowledge and skills by learning about the journey from silicon fundamentals to chip fabrication and packaging.
Pricing
Members: $399
Non-Members: $449
* * Group pricing for 10+ attendees: $3,800 and 20+ attendees: $7,600 Any questions, please contact [email protected]
Inside the Fab: An Introduction to Semiconductor Manufacturing
Virtual Training - Asia
10:00 am - 2:00 pm
Off
Add to Calendar2026-08-10 10:00:002026-08-13 14:00:00Inside the Fab: An Introduction to Semiconductor Manufacturing (Asia)Strengthen your knowledge and skills by learning about the journey from silicon fundamentals to chip fabrication and packaging. Pricing Members: $399Non-Members: $449* * Group pricing for 10+ attendees: $3,800 and 20+ attendees: $7,600Any questions, please contact [email protected]SingaporeSEMI.org[email protected]Asia/Singaporepublic
Asia/Singapore
Register Now
This course provides a comprehensive introduction to semiconductor manufacturing, guiding participants through the complete journey from silicon fundamentals to chip fabrication and packaging. Designed for professionals new to the semiconductor industry, the course explains key concepts, terminology, devices, and manufacturing processes used in modern fabs.
This course is divided into four modules, enabling a progressive learning experience that builds from fundamentals to manufacturing execution. Participants will gain a clear understanding of how chips are made, the role of transistors, and the steps involved in front-end manufacturing, followed by back-end assembly and packaging processes. The course also introduces the broader semiconductor ecosystem, including supply chain players, helping learners connect technical fundamentals with real-world manufacturing practices.
Who Should Attend
This course is designed for sales and marketing professionals, as well as new employees, students, and anyone interested in gaining a knowledge about semiconductor manufacturing.
Learning Objectives
Upon completion of the course, participants should be able to:
Explain fundamental semiconductor concepts, including silicon materials, doping, PN junctions, and basic device behavior.
Identify and correctly use common semiconductor manufacturing terminology.
Outline the key steps involved in front-end wafer fabrication, from bare silicon to patterned wafers.
Summarize back-end manufacturing processes, including assembly, packaging, and testing.
Topics Included
Module 1: Semiconductor Fundamentals
Introduces semiconductor basics, silicon materials, doping PN junctions, and core device concepts, building a foundation for understanding how electronic devices function.
Module 2: Semiconductor Terminologies and Manufacturing Context
Covers essential semiconductor terminology, cleanroom concepts, supply chain players, process nodes, and packaging to help learners navigate manufacturing discussions with confidence.
Module 3: Front-end and Back-end Semiconductor Manufacturing
Provides an overview of the key steps involved in front-end wafer fabrication and back-end assembly, packaging, and testing processes.
Module 4: Transistors and Their Operation
Explains different types of transistors and their working principles, showing how transistors function as switches and amplifiers inside integrated circuits.
Important Information
Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access the course knowledge.
Can't find the training link on the day of the training? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders 24 hours in advance and 1 hour before, with the same link. Please keep these emails on hand to access the training on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.
Join the SEMI Water Management team and document authors for a webinar discussing their research and findings for the Water Management Strategy Reports. The reports are guides for water managers for understanding their water balance, baseline, potential savings and a general maturity scale for several solutions to be considered to move up the maturity scale to Zero Liquid Discharge (ZLD). The webinar will provide an overview on how the documents should be used to work with water solutions providers and provide strategies for both new and legacy facilities with end-of-pipe solutions as well as treatments for individual process stage water discharge.
The webinar will include a discussion of next steps for the continued development of the reports, including how they interact with SEMI Standards and the industry roadmaps.
9:00 am - 10:00 am
Off
Add to Calendar2026-05-21 09:00:002026-05-21 10:00:00Water Management Strategies WebinarJoin the SEMI Water Management team and document authors for a webinar discussing their research and findings for the Water Management Strategy Reports. The reports are guides for water managers for understanding their water balance, baseline, potential savings and a general maturity scale for several solutions to be considered to move up the maturity scale to Zero Liquid Discharge (ZLD). The webinar will provide an overview on how the documents should be used to work with water solutions providers and provide strategies for both new and legacy facilities with end-of-pipe solutions as well as treatments for individual process stage water discharge. The webinar will include a discussion of next steps for the continued development of the reports, including how they interact with SEMI Standards and the industry roadmaps.Reports can be downloaded HERE.United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
Register Here
This course introduces key cybersecurity principles, practices, and strategies tailored for semiconductor manufacturing environments. Participants will explore foundational concepts in cybersecurity, risk management, and best practices to secure semiconductor manufacturing systems and data.
Who Should Attend
This course is designed for:
Engineers and technicians in semiconductor manufacturing
IT professionals managing manufacturing systems
System administrators are responsible for securing semiconductor equipment and networks
Individuals tasked with implementing cybersecurity strategies in industrial settings
Prerequisites
Basic understanding of semiconductor manufacturing processes
Familiarity with IT infrastructure (networks, computers, and systems)
Learning Objectives
By the end of the course, participants will:
Understand the basic principles of cybersecurity and their importance in a manufacturing environment.
Be able to assess and manage cybersecurity risks within the semiconductor manufacturing systems.
Learn practical strategies for implementing cybersecurity measures to protect critical infrastructure, devices, and data.
Gain insights into responding to and recovering from cybersecurity incidents.
Be prepared to develop and promote a strong security culture within their organization.
Important Information
Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access course knowledge.
Can't find the training link day of? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders about 24 hours in an advance and an hour before with the same link. Please keep these emails on hand to access the trainings on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.
Unlock the secrets to safeguarding semiconductor manufacturing systems with this comprehensive cybersecurity course. Learn essential principles, risk management strategies, and best practices to protect critical infrastructure and data from cyber threats. Equip yourself with the knowledge to implement robust security measures and respond effectively to incidents in industrial environments.
Pricing
Members: $ 99
Non-Members: $129
* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected].
Implementing Basic Cybersecurity Principles in Semiconductor Manufacturing
Virtual Training - Americas & EU
8:00 am - 12:00 pm
Off
Add to Calendar2026-07-13 08:00:002026-07-13 12:00:00Implementing Basic Cybersecurity Principles in Semiconductor Manufacturing (Virtual Training (Americas & EU) Unlock the secrets to safeguarding semiconductor manufacturing systems with this comprehensive cybersecurity course. Learn essential principles, risk management strategies, and best practices to protect critical infrastructure and data from cyber threats. Equip yourself with the knowledge to implement robust security measures and respond effectively to incidents in industrial environments.PricingMembers: $ 99Non-Members: $129* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact [email protected]. United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
Register Now
This three-day virtual workshop (4 hours a day) provides a complete overview of the semiconductor manufacturing process. The class focuses on key process steps needed to form a functioning device. Some important science and engineering ideas needed to understand device manufacturing will be discussed. The workshop is designed for non-technical personnel needing an understanding of the fab process steps. Some technical background from attendees will improve the workshop learning.
The first day will overview the fab process steps with a brief summary of how a transistor functions. We will discuss how multiple transistors are connected to form a logic or memory device. We will also cover how a transistor works with respect to the physical layout of Bipolar and MOSFET transistors.
The second day will cover key fab process steps. Ion implantation, photolithography including DUV and EUV processes, plasma processes including deposition and etch, rapid thermal processing, and wet etch processing. Specific emphasis will be given to the different wet etch processes.
The third day of the workshop will focus on the new transistor designs, including FinFET and CFET designs. We will also cover reasons for changing the transistor design and newer materials, including tantalum, hafnium, silicon germanium, and low-k dielectrics. We will also review roadmaps of leading companies, including TSMC, Intel, and Samsung.
After completing the workshop, the student will be able to describe all the fabrication and assembly process steps and have an understanding of how the process steps work together to form the completed integrated circuit, in addition to an understanding of future structures.
Who Should Attend
This course is intended for both manufacturing and R&D know-how in IC packaging professionals, including but not limited to:
Process Technicians
Material Engineers
Process Engineers
Equipment Manufactures
Technical Marketing Engineers
Topics Included
Silicon wafer manufacturing
Basic operating principles of transistors and semiconductor devices
Planar, FinFET, and GAA transistor formation and design differences
Fab processes needed to form a semiconductor, including the following:
Note that only the person who registered will receive a certificate of completion. This virtual training will not be recorded. Attendees must be present to access the course knowledge.
Can't find the training link on the day of? After you register, you will receive the link to the live training via the email address you provided. In addition, you will receive email reminders about 24 hours in advance and an hour before with the same link. Please keep these emails on hand to access the training on time. If you do not see any confirmation emails, please check your junk/spam folders before contacting SEMI U for support.
