The chips powering today’s cell phones, cars, computers, and more can contain billions of transistors. Designing these chips requires a team of engineers with expertise in various aspects of the design flow, along with Electronic Design Automation (EDA) tools that are needed to implement and verify these complex designs.
This Master Class is intended for non-technical staff that wish to understand the basics of semiconductor chip design. It provides an appreciation of the complex design flows and an understanding of some of the terminology used by chip design teams.
For students, the course will introduce some of the rewarding challenges and career opportunities available in the design and EDA industries.
In this class we will cover basic information about digital chips, then introduce some of the key steps and tools used during the design flow. We will also discuss some of the tradeoffs of different implementation methodologies and some of the challenges presented by various critical applications such as devices used in medical and automotive systems.
Complex semiconductor chips power today’s cell phones, cars, computers, and more. This on-line Master Class will provide non-technical people who work in and around the chip design industry a high-level overview and understanding of how these complex chips are designed.
ESD Alliance Master Class: Introduction to Chip Design and EDA
Overview of the design of today's complex chips with Electronic Design Automation tools.
(On-line Event)
10:00 am - 11:30 am
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Add to Calendar2025-06-25 10:00:002025-06-25 11:30:00ESD Alliance Master Class: Introduction to Design and EDAComplex semiconductor chips power today’s cell phones, cars, computers, and more. This on-line Master Class will provide non-technical people who work in and around the chip design industry a high-level overview and understanding of how these complex chips are designed. SEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
Register Now to Watch the Recorded Event
“How Will Agentic AI Change Chip Design and Verification?” features EDA and emerging agentic AI company executives and entrepreneurs discussing changes within chip design and verification as agentic AI tools become more mainstream. Panelists will distill the excitement surrounding the innovation in chip design and verification, collaboration between traditional EDA and agentic AI startups and broader implications for technological advancements.
Cadence Design Systems 2655 Seely Avenue Building 10 San Jose, CA95134 United States
5:30 pm
-
6:45 pm
Registration and Networking with Dinner and Beverages
Hardware is at the heart of computing systems. However, recent years have seen increased attacks exploiting hardware vulnerabilities and exploits, which even traditional software-based protections cannot prevent. Hardware fuzzing has shown promise in detecting vulnerabilities in large-scale designs like modern processors. In this talk, we will describe the hardware vulnerabilities in hardware description languages, such as Verilog and VHDL. Then, we will explain a new and radical approach called hardware fuzzing to find these vulnerabilities and detail how fuzzing techniques can be combined with existing formal verification techniques to detect vulnerabilities efficiently. Finally, we will discuss a strategy for pinpointing vulnerabilities to accelerate the mitigation process and briefly talk about improving the efficiency of hardware fuzzing using ML/AI techniques, such as multi-armed bandit (MAB) and large language models (LLM).
Meet the Speakers
Guest Speaker
Jeyavijayan (JV) Rajendran Associate Professor Department of Electrical and Computer Engineering Texas A&M University Biography
Moderator
Warren Savage Researcher at University of Maryland Applied Research Laboratory for Intelligence and Security Biography
The ESD Alliance, a SEMI Technology Community, is hosting a webinar series, "Savage on Security," moderated by Warren Savage, Researcher at University of Maryland, Applied Research Laboratory for Intelligence and Security.
10:00 am - 11:00 am
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Add to Calendar2025-03-27 10:00:002025-03-27 11:00:00ESD Alliance Webinar: Savage on Security 2: Mar 27, 2025The ESD Alliance, a SEMI Technology Community, is hosting a webinar series, "Savage on Security," moderated by Warren Savage, Researcher at University of Maryland, Applied Research Laboratory for Intelligence and Security. United StatesSEMI.org[email protected]America/Los_AngelespublicRegister Now to Watch the Recorded Event
New horizons for semiconductors have been revealed by innovations in heterogeneous integration, especially due to the availability of an abundance of inter-chiplet wires. All this has implications on security leading to new challenges as well as opportunities. This talk presents an overview on how prior work on 2D SoCs may or may not be helpful in addressing this challenge.
Meet the Speakers
Guest Speaker
Ankur Srivastava Director of the Institute for Systems Research University of Maryland Biography
Moderator
Warren Savage Researcher at University of Maryland Applied Research Laboratory for Intelligence and Security Biography
The ESD Alliance, a SEMI Technology Community, is hosting a webinar series, "Savage on Security," moderated by Warren Savage, Researcher at University of Maryland, Applied Research Laboratory for Intelligence and Security.
ESD Alliance Webinar: Security Constructs for Heterogenous Integration
Savage on Security Webinar Series #1
Recording
Recorded January 23, 2025
Heterogeneous Integration (HI) has come a long way in 50 years. The world of multi-chip modules (MCMs) has given way to a vast ecosystem of chiplets, 3D stacked die, and co-packaging of antenna, high-bandwidth memory (HBM), and optics. HI is at the center of “More than Moore” development activities, as innovative engineers look for creative ways to overcome the slower scaling of silicon technology. The promise of HI is new devices with superior power, performance, area, and cost (PPAC). All these promises come with new challenges. Managing different process nodes, physical characteristics, mechanical stresses, and other system-level challenges not found in monolithic system-on-chip (SoC) devices, creates a great opportunity for design and manufacturing companies to reshape our industry.
In this webinar, we’ll explore this enabling technology from both the device maker and material supplier perspectives. We will learn about demands placed on devices by new applications and what new tools are needed to meet these demands. We will also hear about the challenges placed on materials and equipment suppliers to develop processes capable of manufacturing the individual components and integrating them into final products. Join us as our panel of experts address the issues and opportunities involved with heterogeneous integration.
United States
Arsalan Alam, PhD
Member of Technical Staff (MTS), 3D Stacking Technology Group
AMD Packaging
2nd Generation 3D V-Cache™ Enablement
Andrea Chacko, PhD
Director of Packaging Solutions
Brewer Science
Dongshun Bai, PhD
Business Development Director and Senior Technologist of Packaging Solutions
Brewer Science
Enabling Heterogeneous Integration through Material Design
The realization of Heterogeneous Integration (HI) has been key in driving advancements in semiconductor technology. The complexities of integrating dissimilar materials continue to be a challenge for HI. All advanced packaging technologies rely on advanced materials to address the many challenges in achieving continued shrinking and improved performance of devices. Novel materials capable of managing mechanical stresses and increased thermal budgets with strict cleanliness requirements are required for processes such as wafer thinning, fan-out wafer-level packaging, and hybrid bonding. This presentation will highlight how advanced materials can address the growing challenges in the industry.
Dive into the dynamic world of semiconductor materials and discover the future landscape as the industry experts provide a glimpse into the future of the semiconductor ecosystem in the era of heterogenous integration.
Heterogenous Integration finds its place
Webinar
10:00 am - 11:00 am PT
Zoom
10:00 am - 11:00 am
Off
Add to Calendar2024-10-16 10:00:002024-10-16 11:00:00Heterogeneous Integration finds its placeDive into the dynamic world of semiconductor materials and discover the future landscape as the industry experts provide a glimpse into the future of the semiconductor ecosystem in the era of heterogenous integration.United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
REGISTER NOW
INAUGURAL EVENT FOCUSED ON SMART MANUFACTURING & SMART MOBILITY
Join us for a groundbreaking Midwest conference and tradeshow on April 1-2, 2025, focused on Smart Manufacturing and Smart Mobility with an emphasis on the semiconductor industry! Automotive electronics and smart manufacturing are two of the key end markets on the path to $1T in semiconductor revenue.
A significant amount of both markets is concentrated in the Midwestern United States. SEMIEXPO in the Heartland will bring these two key markets together and provide an opportunity for collaboration and growth.
Smart Manufacturing
The program will focus on the deployment of Industry 4.0 or Smart Manufacturing tools, technologies, and methods for the semiconductors required for this growing market.
Smart Mobility
The program will unite stakeholders in the semiconductors/sensors and mobility ecosystems to identify and address technical issues and supply chain dynamics that are best addressed collectively.
Ways to Participate
Exhibit
Sponsor
Speak
Attend
MAKE YOUR MARK AT THE INAUGURAL SEMIEXPO HEARTLAND
Plan Now to Exhibit or Sponsor. Contact— Shane Poblete | +1 202-847-5983 | [email protected]
NEW EVENT!
April 1–2, 2025
Indiana Convention Center, Indianapolis, IN
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Add to Calendar2026-04-29 00:00:002026-04-30 00:00:00SEMIEXPO Heartland 2026Indiana Convention Center 100 S Capitol Ave Detroit, MI United StatesSEMI.org[email protected]America/Detroitpublic
America/Detroit
Your company has built a strong patent portfolio — now what? This webinar will discuss strategies for managing existing patents, including how to use IP to strengthen your business and maximize return on investment. Topics will include best practices for patent marking, controlling rising maintenance fees, and licensing, as well as insights into emerging trends in patent enforcement and litigation in the semiconductor sector.
ABOUT THE SPEAKER
Michael Jones, Partner, Rothwell Figg Michael H. Jones’s practice includes patent litigation, patent prosecution, and IP counseling. Michael advises clients who have developed a broad range of technologies, including semiconductor devices and manufacturing, integrated circuits and systems, green energy, terahertz electronics, hardware and protocols for wireless communications, and various online technologies. Although much of his work is with large multinational clients with complex patent portfolios, Michael also has a significant, and growing, practice with smaller high-technology clients, ranging from startups to growth companies dealing with patent issues for the first time in their evolution. Michael has a B.S. in Electrical and Computer Engineering from University of Virginia, a M.S. in Electrical and Computer Engineering from University of California, Santa Barbara, and a J.D. from The George Washington University Law School.
Best Practices for Semiconductor Patent Portfolio Management
Flexible Electronics Master Class #23
10:00 am - 12:00 pm
Off
Add to Calendar2024-11-06 10:00:002024-11-06 12:00:00FEMC #23 Best Practices for Semiconductor Patent Portfolio ManagementUnited StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
A high quality patent can turn an innovation into a valuable business asset. Strategic drafting of patent applications and the management of the prosecution of the application around the world is essential to obtaining maximum value. Learn how to ensure your valuable innovation remains protected while avoiding common pitfalls, including losing rights through errors like public disclosure or incomplete protection.
ABOUT THE SPEAKER
Brian Rosenbloom, Partner, Rothwell Figg With over two decades of experience in the intellectual property (IP) field and a strong technical background in the electrical and software arts, Rothwell Figg partner Brian Rosenbloom is an expert in patent prosecution, IP counseling, and patent litigation proceedings before the U.S. Patent and Trademark Office and in district courts across the country. Brian represents clients ranging from Fortune 100 companies to independent inventors, entrepreneurs, and emerging enterprises, and works with a broad range of technologies. Brian received a Bachelor’s degree in Electrical Engineering from Columbia University (Tau Beta Pi Engineering Honor Society, Eta Kappa Nu Electrical Engineering Honor Society), and worked as a software engineer at General Electric Information Services for several years. After working at GE, he pursued a law degree and received a J.D. from Georgetown University Law Center (cum laude).
How to Protect Your Valuable IP in the Microelectronics Industry
Flexible Electronics Master Class #22
10:00 am - 12:00 pm
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Add to Calendar2024-10-30 10:00:002024-10-30 12:00:00FEMC #22 How to Protect Your Valuable IP in the Microelectronics IndustryUnited StatesSEMI.org[email protected]America/Los_Angelespublic
The SEMI Server Certification Protocol was developed to minimize the unauthorized use (piracy) of licensed software. Developed by a partnership of companies in the Electronic Design Automation (EDA) industry and managed by the Electronic System Design Alliance, a SEMI Technology Community, the protocol is applicable to many high-value software solutions. The protocol achieves this by being able to uniquely identify license servers – closing a loophole that is often exploited to enable unauthorized software use.
Later this year, SEMI will begin offering licenses to the protocol to companies wishing to strengthen their software license management systems against unauthorized usage.
On Wednesday, September 27th, the ESD Alliance will be presenting a webinar on the protocol including:
How software piracy impacts both software vendors and their customers
An overview of how the protocol is used to prevent license server duplication
A description of the protocol and its scope
How the protocol can be integrated into a software license management system
Additional background on use cases and how the protocol can be applied in different environments
The webinar will be presented by the chair of the joint development team that developed the protocol and will include a Q&A session.
United States
Wednesday, September 27, 2023 | 10:00-11:30am Pacific Time
10:00 am
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10:15 am
Bob Smith
Executive Director, ESDA,
SEMI
Welcome and Impact of Software Piracy
10:15 am
-
11:00 am
Chair, SEMI/ESDA License Management and Anti-Piracy Committee
Sashi Subramanian
Senior Group Director, Licensing, Downloads and Release Operations,
Cadence
Introduction to the SEMI Server Certification Protocol
Are you involved in managing your company’s software licensing practices and infrastructure? If so, this free webinar is for you!
Register today for this informative webinar presented by the Electronic System Design (ESD) Alliance.
SEMI License Server Certification Protocol
[VIRTUAL WEBINAR]
September 27, 2023
10:00–11:30am Pacific Time
10:00 am - 11:30 am
Off
Add to Calendar2023-09-27 10:00:002023-09-27 11:30:00SEMI License Server Certification Protocol WebinarAre you involved in managing your company’s software licensing practices and infrastructure? If so, this free webinar is for you!
Register today for this informative webinar presented by the Electronic System Design (ESD) Alliance.United StatesSEMI.org[email protected]America/Los_Angelespublic
America/Los_Angeles
REGISTER NOW
