Day 1 | Power Electronics and Devices Day | Tuesday, March 23, 2021
Stefan Eisenbrandt, Principal Engineer Process Development, X-FAB
Abstract
Voltage-scalable device architectures are a widely used approach during technology development to enrich the device portfolio with a common process1,2,3. While the targeted breakdown voltage and on-resistance are compromised straightforwardly, the scalability of reliability parameters across a certain voltage range remains a challenge. Most publications investigate on failure mechanisms faced in scalable device design4,5,6 whereas only few focus on reliability scalability. In this presentation a 40V to 125V n-channel LDMOS device demonstrates reliability scaling through layout and process co-optimization in 0.18 μm SOI technology.
Biography
Stefan Eisenbrandt received the Master of Science degree in electrical engineering and information technology from Ilmenau University of Technology, Germany in 2015. He joined X-FAB in 2016 as a process development engineer for high-voltage devices. His interests include Technology CAD, fabrication, characterization and modeling of Silicon and GaN based high-voltage devices.
Dr.-Ing. Tobias Erlbacher, Head of Department Devices, IISB Fraunhofer
Abstract
Silicon carbide has turned into an established material for high voltage power semiconductor devices. This talk will start with a brief recap of the SiC device and processing history to date – summarizing the benefits of SiC devices in power converters, the progress in development of such power devices and the tremendous efforts of governments and industry to make SiC economically feasible.On the basis of this success, the presentation will then focus on chances to further exploit the availability of SiC manufacturing technology in combination with 150mm and 200mm processing lines and recent developments towards new horizons. Present trends in power device fabrication are summarized and discussed. This also includes the utilization of SiC CMOS technology towards integrated circuits for harsh environments. High temperature analog signal amplification will serve as an example. Additionally, some of the challenges involved with doping Silicon carbide and the corresponding modelling will be addressed.Also, the presentation will provide an outlook towards the application of SiC electronics towards quantum computing and sensing. Challenges and chances towards the implementation of quantum dots, magnetic field sensing and quantum logic will be discussed.Finally, the presentation will include a summary towards SiC fabrication technology and a call to action for tool manufacturers, designers and application engineers to exploit the new capabilities that Silicon carbide device technology offers.
Biography
Tobias Erlbacher received the Diploma in Electrical Engineering (Microelectronics) from the University of Erlangen-Nuremberg in 2004, and his Ph.D. degree in 2008. Since 2009 he is with the Fraunhofer Institute of Integrated Systems and Device Technology IISB in Erlangen, where he is heading the “Devices” Group. His research activities focus on device modelling, design and integration as well as technology development for power electronics. This includes the monolithic integration of passive networks and the optimization of power semiconductor devices in silicon integrated circuits. He has authored a book on lateral power transistors in integrated circuits. Moreover, Dr. Erlbacher is working on design and development of silicon carbide devices for power applications, high-temperature integrated circuits and sensors. He also has expertise with non-volatile memories and device characterization at the nano-scale. He has authored and coauthored over 100 papers in scientific journals and contributed to 10 patents.
Luca Fanelli, U.S. Sales & Business Development Manager, SPEA
Luca Fanelli receives his M.S. degree in Electrical Engineering from the Polytechnic of Turin (Italy) in January of 2006. He joins SPEA the same month and immediately becomes part of the Product and Test Engineering Group involved with Wafer and Final test of Silicon discrete high power MOSFETs. In November 2007 he is appointed Test Engineering Manager of the same group. In this position, he joins the company’s engineering efforts to develop the next generation of High Volume ATEs for the test of GaN products (for Static and Dynamic tests). In 2009 he relocates to United States, where he manages the entire Semiconductor Engineering Team. While maintaining his Engineering Management role, in December 2012 he is appointed Technical Sales Manager for the North America Sales Team. During this period, he works closely with the Sales team to affirm and expand the presence of SPEA’s products in North America. In March 2017 he is appointed as Manager of the entire Semiconductor Division in North America, including Sales, Engineering and Service. In the last three years, his group has worked directly with SPEA's customers to develop state-of-the-art technology for testing high volume discrete SiC high power devices, SiC KGD devices, and SiC Power Modules.
Torsten Loch, Director Technical Sales, ExaGaN
Abstract
GaN-on-Silicon power devices are recognized as a key technology to sustain future power converter systems roadmaps in the a multitude of fields including IT electronics, renewable solar and emission free automotive applications, amongst others. Exagan is implementing a proprietary 200-mm GaN-on -Silicon technology in high volume production which will enable higher integration and improved efficiency. Currently, silicon based solutions are the benchmark used to evaluate any new technology. Similar "easy to use", "predictive FIT in use" and "cost in use" are critical attributes for any new product. The Exagan product portfolio provides GaN-on-Silicon solutions and leverages extremely fast GaN on Silicon switching properties. Meeting user expectations, required reliability and cost targets, Exagan solutions help innovators create smaller, more efficient and higher-performing power converter applications. This was not achievable with traditional silicon-based technology.
Exagan’s paper covers the latest developments and the pending product releases using cost effective G-FET™ 200-mm GaN-on-Silicon technology.
Biography
Mr Loch, joined Exagan in June 2019 as Director of Technical Sales. In this role, his focus is on customer application development leveraging GAN technology, a key future component in our industry. Previously, he served as Sales Manager for major automotive accounts at Diodes Inc. a supplier of analog and discrete power components and as Sr RSM at Power Integrations, a supplier of analog and mixed signal PSU's. The primary markets Mr. Loch served are Industrial, Consumer, Lighting and Automotive.
He has 20 years of technical Sales and Marketing experience in the power semiconductor industry. Mr. Loch holds a graduate degree in both Electrical and Industrial Engineering. He is based in Munich, Germany.
Ionut Radu, Director R&D, Soitec
Biography
Ionut Radu is Director of Research and External Collaborations being responsible for path finding and technology scouting at Soitec. Ionut is currently involved with industrial and academic innovation platforms supporting strategic developments of advanced substrate materials for semiconductor industry.
Dr. Radu obtained his B.S. in physics from University of Bucharest in 1999 and Ph.D (Dr. rer. nat.) in physics from Martin-Luther University Halle-Wittenberg in 2003. He has co-authored more than 70 papers in peer-reviewed journals, conference proceedings and reference handbooks and holds more than 60 patents in the field of semiconductor technologies. Dr. Radu is senior member of IEEE society and involved in Technical Program Committees of international conferences (ESSDERC, VLSI-TSA) and industrial forums (Semicon Europa).
Walter Schwarzenbach, Technology Leader, Soitec
Abstract
Silicon Carbide (SiC) Power Devices is a very fast growing business, serving a wide range of market and application and especially supporting new electrical mobility solutions.Current technology is based on bulk SiC materials, being limited by the material crystalline quality leading to poor device yield performance.Soitec's Smart Cut technology, enables high quality SiC layer transfer on top of low resistivity materials, opening path for both higher device fabrication yield and electrical performance. This talk will present early demonstration of Smart Cut Engineering SiC substrate including material characteristics, test device results and recent update on the newly created pilot line to accelerate Smart Cut SiC substrate development.
Biography
Walter Schwarzenbach (m) has received an Engineer Degree in Physics from the Swiss Federal Institute of Technology in Lausanne in 1994, and a PhD Degree in Physics from the University of Grenoble in 1999. He joined Soitec in 2000 as process development engineer then becomes project leader in charge of SmartCutTM process industrialization for several 300mm Partially-Depleted SOI substrate generations. From 2009 to 2018, he was in charge as Product Leader of Fully-Depleted SOI, Imager SOI and 3D materials definition and introduction. Since 2019, as part of Innovation team, he is Technology Leader for SmartCut SiC engineered substrates. He is author or co-author of more than 45 articles in international refereed journals and conferences and more than 30 patents.
Véronique Sousa, Head of Power device laboratory, CEA
Abstract
Wide band gap in power electronics has today demonstrated its ability to intercept next challenges for power conversion systems. Silicon carbide is now available and well-established for high power density needs. Gallium nitride power switches has emerged in the industry during the last two years and it is clear that they will provide solutions for a wide range of power applications. In terms of device technology, E-Mode functionality seems to be the most popular for lateral HEMT GaN switches. pGaN FET architecture of devices is now available on the market for several “end-users” applications. CEA/LETI has develop another approach to meet the requirements of power electronics with an isolated MIS GATE HEMT GaN solution. This option is on its way to reach an industrial level of maturity. We will review the main technological challenges that have been overcome to reach this level of maturity. Then, the next challenges will be described with a perspective to provide competitive GaN HEMT devices compared to the state of the art.
Biography
Véronique Sousa graduated in 1994 from the Université Grenoble Alpes in the field of Materials Science and Engineering. She joined the CEA-Leti-MINATEC-Campus in 1998. For about 20 years, she led R&D projects dedicated to the optimization of different resistive memory technologies, among which the phase change memories. Since 2018, the focus of her work shifted toward GaN power devices. Since 2020, she is the head of the Laboratory for Power Semiconductor Devices in CEA-Leti.
Day 2 | Materials Day | Wednesday, March 24, 2021
Rolf Aschenbrenner, Director's Deputy, Fraunhofer IZM
Abstract
Heterogenous integration through SiP (System-in-Package) can leverage the advanced capabilities of packaging technology to create systems close to the SoC form factor but with better yield, lower overall cost, higher flexibility, and faster time to market; the latter has especially shifted the paradigm from SoC-centric to SiP-centric in the recent past even for volume products. This presentation highlights the market needs, technology paths, difficult challenges and potential solutions when addressing high-density system integration with advanced packaging materials, tools and techniques, with projections on required developments over the next 10 to 15 years.
Biography
Rolf Aschenbrenner received the B.S. degree in mechanical engineering from the University for Applied Science, Gießen, Germany, in 1986 and the M.S. degree in physics from the University of Gießen, Germany, in 1991. From 1991 to 1992 he has worked at the University of Gießen and in 1993, he joined the Research Center for Microperipheric Technologies at the Technical University of Berlin. Since March 1994 he has been employed at the Fraunhofer Institute for Reliability and Microintegration Berlin (IZM) where he is presently the Deputy Director and Head of the Department System Integration and Interconnection Technologies.He received the iNEMI International Recognition Award in 2005, the CPMT David Feldman Outstanding Contribution Award 2013 and the European Semi Award 2016.As a member of the IEEE EPS Society Board of Governors Rolf Aschenbrenner has worked as a European representative on the Conference Advisory Board Committee, and has played an active role in the globalization of IEEE EPS in terms of membership and chapter development. He served as IEEE CPMT Vice President, Technical and IEEE EPS Vice President, Conferences. From January 2010 until December 2011 he was IEEE EPS President and in 2012 he became IEEE Fellow.
Prof. Dr. Jonathan Finley, Chair for Semiconductor Nanostructures and Quantum Systems, Technical University of Munich
Biography
Prof. dr. Jonathan Finley has more than twenty years of research experience working in the field of nanostructured semiconductor materials and their use for exploring emergent nano-photonic and quantum phenomena. He is the director of the Walter Schottky Institut and is full professor at the Physics Department of Technical University of Munich, holding the chair for Semiconductor Nanostructures and Quantum Systems (SNQS). The principle research topics are the growth and optical properties of semiconductor nanomaterials, quantum optics using condensed matter systems and the physics of atomically thin 2D-nanomaterials. This includes III-V, 2D and group IV semiconductors and their development for emergent nano and quantum photonic devices. Prof. Finley is recipient of several awards including the Walter Schottky Prize of the German Physical Society DFG (2007), the ISCS Young Scientist prize (2010) and the Bavarian Government Prize for University Teaching (2011). Prof. J. Finley is author of >400 papers, articles, book chapters and patents resulting in an h-index of 52 (44) according to Google Scholar (Web of Science) and >10000 (>7500) citations.
Prof. Amelie Hagelauer, University of Bayreuth
Abstract
Nowadays, primarily acoustic wave devices are used for filtering in front ends of modern mobile transceivers. The two subgroups of those devices, that have made it into volume production, are surface acoustic wave (SAW) and bulk acoustic wave (BAW) devices. A lot of effort has been spent to reduce the number of SAW/BAW devices, or ideally, completely remove them. However, no competitive technology providing the same performance at the same size and cost exists today. Thus, the trend is going in the opposite direction, driven by the demand for ever higher data rates and the desire to use the same phone in all parts of the world. The number of acoustic wave devices in a mobile phone is increasing with each new generation of communication standards. An end of this trend is not foreseeable yet.No competitive technology providing the same performance at the same size and cost exists at the moment. Key developments in the past years to enhance the performance are new materials. In this talk, materials for SAW/BAW devices and high k2 materials for BAW devices, of which both give great impact to the device performance, are presented.
Biography
Amelie Hagelauer received the Dipl.Ing. degree in mechatronics and the Dr.Ing. degree in electrical engineering from Friedrich–Alexander University Erlangen–Nuremberg, Germany, in 2007 and 2013, respectively, and the Ph.D. degree in thin film BAW filters from the Institute for Electronics Engineering. She joined the Institute for Electronics Engineering in November 2007. Since 2013, she has been focusing on SAW/BAW and RF MEMS components, as well as integrated circuits for frontends up to 180 GHz. She was the Chair of MTT-2 Microwave Acoustics from 2015 to 2017. She has also been a Professor with Universitat Bayreuth, since August 2019. She is currently continuously contributing to the development of RF Acoustics community by organizing workshops and student design competitions. She has been acting as an Associate Editor of the IEEE Transactions on Microwave Theory and Techniques and as a Guest Editor of a special issue of the IEEE Transactions on Microwave Theory and Techniques on the topic RF Frontends for Mobile Radio as well as for a Special Issue in the Sensors Journal (MDPI) on the topic Surface Acoustic Wave and Bulk Acoustic Wave Sensors.
Prof. Dr. Fred Roozeboom, Professor, TU Eindhoven & TNO-Holst Centre
Prof. dr. Fred Roozeboom received his MSc (cum laude) at Utrecht University in 1976 and his PhD degree in 1980 from the Twente University, The Netherlands on topics in catalysis. From 1980-1983 he worked on zeolite catalysis with Exxon R&D Labs in Baton Rouge, USA. In 1983 he joined Philips Research (since 2006: NXP Research) in Eindhoven, where he worked on thin-films processing of III-V semiconductors (1983-1988), IC metallization (1988-1990) and soft-magnetics (1990-1996). From 1997 to 2009 he led a team working on technology transfers of 3D Si-integrated System-in-Package products for wireless communication and power management, manufactured at Philips/ NXP Semiconductor plants in Caen, France (now Murata) and Shanghai. For this work he received the Bronze Award of the ‘NXP Invention of the Year 2007’ and became an NXP Research Fellow in 2007.
In 2007 he became also part-time professor at TU Eindhoven (Netherlands) in the group Plasma and Materials Processing. He has been teaching MSc classes in this field from 2009-2015, and advised 7 PhD and 2 PD Eng. graduates. Since Sept. 2018 he is emeritus-professor, still advising students.
In 2009 he left NXP, to join TNO-Holst Centre in Eindhoven, as a senior technical advisor working in a team specializing in the industrialization of spatial Atomic Layer Deposition and related Atomic Layer Etching and Cleaning. In 2011, the spatial processing team at TNO received the 2nd EARTO Innovation Award.
In 2014 he was elected Fellow of the Electrochemical Society ‘for pioneering work in semiconductor processing and thin film technology’. Since Sept. 2018 (eligible for Dutch retirement) Fred had his contract extended at TNO for a few more years, where he aims at new applications in area-selective ALD, Li-ion micro-batteries, EUV optical lifetime.
Fred is co-/author of 200+ publications (h-index: 38) covering chemistry and physics, 5 book chapters, 36 granted US patents and several pending WO patent applications, and co-/editor of 49 conference proceedings on semiconductor processing.
He was or is active in organizing committees of many conferences (MRS, ECS, AVS) and is a member
of the SEMI Europe Semiconductor Technology Programs Committee. He was a member of the ENIAC advisory committee to the European Commission (subcommittee “Beyond CMOS”), the scientific advisory board of several EU-projects. He also served as Meeting Chair of the Materials Research Society (MRS) Fall 2003 Meeting.
Website: https://research.tue.nl/en/persons/fred-roozeboom
Hessel Sprey, Manager External R&D and Cooperative Programs, ASM
Biography
Hessel Sprey received his M.Sc. in experimental Physics from the University of Leiden (The Netherlands) in 1989, and joined ASM in 1990. He has been active in equipment and process R&D at various ASM locations for almost all of ASM product lines and technologies, since 1996 mainly in project and team leader positions. He has been project and workpackage leader for several European funded projects, is (co-)author of more than 60 scientific papers and conference contributions on deposition processes, equipment and applications, and holds 13 patents. He is currently based in Leuven, Belgium, and coordinating the External R&D activities at universities and institutes for ASM’s Corporate Research Development Department.
Vincent Vandalon, Post-Doctoral Researcher, TU/e
Abstract
Two-dimensional layered transition metal dichalcogenides (TMD) such as MoS2 and WS2 are of interest for nanoelectronics because of their promising electronic characteristics and their predictable properties even in the few- and monolayer regime. The merits of TMDs for transistor applications have already been demonstrated by fabrication of field-effect transistors (FET) mainly using intrinsic TMDs (i.e. without intentional doping). However, doped variants of these TMDs are essential for the fabrication of high-performance devices and the realization of advanced transistors concepts. The fabrication method of these doped TMDs has to be compatible with large area deposition and scalable to allow adoption in device fabrication workflows.
In this presentation, the most promising approaches towards doped TMDs will be briefly reviewed with an emphasis on semiconductor fabrication compatibility. In particular, the synthesis of Al-doped MoS2 by plasma-enhanced atomic-layer deposition (ALD) will be discussed as this process demonstrated the highly sought after p-type behavior, widely tunable electronic properties, and excellent control over the carrier density. Going beyond control over carrier density, the control over the doping profile on the nanometer scale - made possible by this ALD based approach - was highlighted by cross-section transmission electron microscopy (TEM) imaging and energy-dispersive X-ray spectroscopy (EDX). Compatibility with semiconductor fabrication is ensured by the conformallity, uniformity, low deposition temperature (< 350 oC), and the sub-nm thickness control inherent to ALD. To conclude, the scalable synthesis of doped TMDs with good control over the electronic properties is key for future TMD based nanoelectronics but these materials are also desirable in other fields including photovoltaics, catalysis, and energy storage.
Biography
Vincent Vandalon is a post-doctoral researcher in the Applied Physics department of the TU/e. He obtained his MSc and PhD in Applied Physics from the Eindhoven University of Technology focusing on nonlinear optics to study the growth of metal and metal-oxide atomic-layer deposition (ALD). For this work he received the American Vacuum Society (AVS) ALD-conference best paper award in 2015. After obtaining his PhD in 2017, his area of research shifted towards the growth and characterization of 2D transition-metal dichalcogenides (TDMs) with a special interest in alloys and doped TMDs for nanoelectronic applications.
Day 3 | Future Fab Day - The World of Smart Manufacturing | Thursday, March 25, 2021
Michael Arnold, Managing Director, Peer Group
Biography
Michael has been responsible for overseeing PEER Group´s European operations since 2003 and helped establish a strong services position in the global semiconductor manufacturing market. Michael is the account manager for several of PEER Group’s top customers in Europe. He served as a member of the SEMICON Europa technical program committee since 2009 and currently chairs the European chapter of the SEMI SMART Manufacturing Technology Community. In 2017, Silicon Saxony appointed Michael as a Board Member. He holds a Diploma degree in Physics and a Ph.D. from the Friedrich-Schiller University Jena.
John Behnke, General Manager, Final Phase Systems, INFICON
Abstract
The semiconductor industry has been on the forefront of developing advanced technologies used tofuel innovation and accelerate technology development since its inception. Its understanding andaccess to advanced technologies coupled with its need to continuously improve manufacturingefficiency and customer satisfaction has pushed the industry to develop and adopt Semi specificSmart Manufacturing/Industry 4.0 methodologies. Ironically the Semi Industry’s development ofpowerful compute capabilities and low cost memory is the leading enabler of these Smart/I4.0solutions.These Smart/I4.0 methodologies are heavily integrated solutions which enhance existing systemsand capabilities. Data from these multiple systems, such as MES, yield, metrology, fault detection,process control, maintenance, and demand integrate to create a learning real time digitalrepresentation of the factory. This Digital Twin or Cyber Physical System is an intelligent learninginformation hub that when properly designed and deployed supports a broad range of sophisticatednew Smart/I4.0 applications. The most common first deployed Smart/I4.0 application is advancedWIP scheduling as it generates the largest ROI and most immediate impact upon a fabsperformance. There are many other Smart/I4.0 applications available or under development whichwhen integrated with a fab’s Digital Twin address other needs or improve the fidelity of theexisting Smart/I4.0 applications. Some of these are evolutionary like automation/robot additions,improved labor allocation, better starts planning, improved PM planning, etc. but others arerevolutionary like AI analysis of Big Data to find subtle causalities, comprehensive in-line productrisk management, integrated AI/ML enabled FDC solutions, augmented reality based PMprocedures, integration of process support tools (think pumps, abatement and more) into the fabDigital Twin to optimize their use and performance as an integrated part of the fab which is criticalto the realization of greener factories.An overview of this evolution of Smart Manufacturing solutions and how they are integrated toprovide their capabilities will be presented in this talk.
Biography
Mr. Behnke has 35 years of semiconductor industry experience including: logic and memory manufacturing, technology/product development and fab operational excellence. As the GM of Final Phase Systems an INFICON Product Line, John leads a team that develop and deploy SMART software solutions that enable fabs to improve their manufacturing efficiency. FPS’s suite of software solutions are built upon a common Datawarehouse which enables advanced Fab Scheduling and optimized WIP movement as well as other related capabilities. He is also a Co-Chair of the Semi North America Smart Manufacturing Special Interest Group. Prior to FPS John served as the CEO and President of Novati Technologies, the SVP and GM of the Semiconductor Group of Intermolecular, the CVP for Front End Manufacturing, Process R&D and Technology Transfers at Spansion and the Director of AMD’s Fab 25’s Engineering and Operations groups where he was a founding member of AMD’s Automated Precision Manufacturing (APM) initiative which led the Semiconductor industry’s development and use of APC and other advanced factory systems. He also led the successful conversion of Fab 25 from Logic to Flash memory which was enabled through the virtual automation of the fab.Mr. Behnke earned a B.S. degree in Mechanical Engineering with an Industrial Engineering Minor from Marquette University. Mr. Behnke holds five U.S. patents.
Bernie D. Capraro, Research Manager, Silicon Technology, Intel Ireland
Biography
Bernie received a Masters Degree in Engineering (MEng) from Newcastle upon Tyne Polytechnic (with Distinction) and has been working at Intel for the past 24 years holding various Engineering and Management roles across the wafer fabrication facilities. Bernie is currently responsible for all silicon nanotechnology research involving Intel in Ireland, helping to identify potential future technology options to Intel in collaboration with Research Centres and Academia across Ireland.
In addition, Bernie owns the relationship development within Ireland’s Third Level Education Institutions, helping to produce a highly educated talent pool in the region, progress Intel’s research agenda, and help set policy direction for the good of both Academia and Industry. In February 2019, Bernie was announced as an Adjunct Professor within Ireland’s first Technological University, TU Dublin.
Bernie’s semiconductor career spans 34 years, with other Process and Equipment Engineering positions held at Telefunken GmbH (Ge), Nortel/Bell Northern Research (UK/Canada), Applied Materials (UK) and Newport Wafer Fab (UK).
Tom Hoogenboom, System Engineer, ASML
Abstract
Holistic Lithography is data hungry. Chips are ‘made with data’. The position and shape of every pattern element must be set with sub-nm precision. We have >billion such elements per wafer. We must do this for every wafer, >million passing a machine in 1 year. Year in, year out.
Chip buyer, chip maker and equipment vendor have a shared interest here: to spot any deviation, however small. We must spot each deviation quickly, before it hurts. Then we must group them so we can tackle as many as possible making process and equipment work together in the right (sub-nm) direction.
A bad marker on the wafer or a temperature drift in a process chamber are isolated deviations which are easily spotted. But to quickly pinpoint a complex interaction between pattern shape, wafer shape, equipment condition and environmental conditions requires advanced algorithms. These in turn require a year or more worth of detailed high-quality data to rule out know issues and/or identify new sources of variation.
This paper describes a central platform for data storage and computing, available to all involved in the patterning process.
Biography
Tom Hoogenboom started his career at Philips in e-beam lithography in the 1980's, working on system aspects and machine software definition.
After a sidestep into Philips Medical Systems (Magnetic Resonance Imaging Software) he joined ASML in 1998 as a system engineer.
Specializing in Software Technology, Tom guided developments related to the machine control of the PAS and TwinScan lithography machines and the development of the second generation YieldStar metrology tools. Today Tom's focus is on the SW infrastructure needed to control nm feature placement at the sub-nm level. Tom's special interests are the social aspects of software engineering and specifically SW as enabler for cross-enterprise team collaboration.
Thomas Schulz, Channel Manager Central and Eastern Europe, GE Digital
Abstract
With the introduction and integration of Industry 4.0 devices, platforms and frameworks to existing systems comes the issue of interoperability. In industrial environments, securing interconnectivity between diverse devices is often challenging. Difficulties in ensuring security in Industry 4.0 result also from lack of technical capabilities of connected industrial devices and systems, especially considering integration with legacy infrastructures. Constraints in embedded systems brings about a major challenge, especially when referring to low end ICSs and PLCs, as they face many issues with a direct impact on their security.
Securing an operational technology (OT) environment is significantly different than securing a traditional information technology (IT) environment. IT focuses on digital information protection. OT focuses on people and physical asset protection. Tools for network monitoring, automatic asset discovery, and configuration and change management at the OT environment have increased the security level of such systems and have raised their availability. The future of the cyber security strongly depends on considering threat landscapes and emerging trends in technology related to big data, cognitive computing, and artificial intelligence.
Biography
Thomas Schulz studied mechanical engineering at the Budapest University of Technology. During his various roles in different companies he has acquired in-depth knowledge and extensive experience in digital transformation and cyber security projects in manufacturing and process industry. Since January 2010 he is responsible for the ecosystem in the German speaking region (D-A-CH) as well as Central and Eastern Europe in the GE Digital division at General Electric (GE).
As a long-standing, active member of the German platform Industry 4.0, he is author and co-author of numerous publications. In recent years he has presented, in Germany and abroad, at over 80 German and English spoken lectures on Industry 4.0 and participated in numerous podium discussions. As Editor of the technical book “Cyber security for connected applications in Industry 4.0”, Thomas Schulz informs with 32 other top-class authors about the expertise, concepts and knowledge base of cyber security in the industrial sector. As a result, change becomes faster, and targeted skills are utilized to make evidence-based decisions.
Brian Vaughan, Director Virtual Interactive Research Lab (VIRaL), TU Dublin
Abstract
Virtual and Augmented reality (VR and AR) technologies provide great opportunity to enhance learning and training in safety and process critical environments across a number of industries. While the technology is developing at a rapid pace, enhancing, augmenting and creating new work practices, our understanding of what these technologies are good for, and not good for, is also developing at a rapid pace. Existing pedagogical theories can provide insight and understanding on how and why these technologies are beneficial for training and simulation. Moreover, combined with contemporary insights and research on game design and game mechanics, these theories can be leveraged to create engaging, immersive, and beneficial training environments. By examining what we know today, rapidly developing VR and AR technologies can be more effectively utilised in the future. Using learnings from other domains, this presentation examines why VR and AR technologies are beneficial and focuses on tangible outcomes of the use of AR and VR technology in cleanroom environments and beyond.
Biography
Brian Vaughan received his BA in Philosophy and Sociology from Trinity College Dublin in 2001; his MA in Audio Technology from Technological University Dublin in 2003, and his PhD in Emotional Speech Analysis from Technological University Dublin in 2011. He worked as a post-doctoral researcher in the Speech Communication Lab in Trinity College for a number of years where he developed, patented, and licensed novel speech analysis technology for the aviation industry. He returned to Technological University Dublin in 2013 where he was programme chair of the MSc in Creative Digital Media and User Experience for five years. As a newly appointed senior lecturer, he went on to found the Virtual Interaction Research Lab (VIRaL) in 2018. The lab is a Mixed Reality (MR) research and development lab that works closely with industry to research, develop, and explore the potential of mixed reality technologies across a number of domains. The lab places great emphasis on User Centred Design (UCD), and utilises a mix of game design and pedagogical methodologies in order to deliver immersive, engaging, and meaningful experiences.
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