semiconductors

In the rapidly-evolving semiconductor industry, maintaining a competitive edge is crucial. To position Europe at the forefront of global semiconductor innovation, imec is leading the NanoIC pilot line initiative. Aligned with the European Chips Act, this initiative is a strategic move to bolster Europe's leadership in key markets like high performance computing, automotive, and healthcare.SEMI spoke with Srikanth Samavedam and Jo De Boeck from imec, Belgium, to learn more about the NanoIC pilot line and to better understand its goals, challenges, and prospects. From transitioning to gate-all-around (GAA) nanosheet devices, to developing advanced memory technologies and interconnects, this conversation highlights the cutting-edge advancements made possible through collaboration across the industry’s value chain.SEMI: How is the NanoIC pilot line working to revolutionize the semiconductor industry, and what are its main objectives?Samavedam: The NanoIC pilot line is a European initiative aimed at bridging the gap between R D and industrial innovation. The project is creating a beyond-2nm system-on-chip (SoC) pilot line, developing advanced logic, memory, and interconnect technologies. This effort supports the European Chips Act's vision for leadership and competitiveness in global semiconductor innovation, particularly in critical markets like high performance computing, communication, automotive, energy, and healthcare. However, advanced technologies come with more complexity, and addressing these complexity challenges requires more mature module baseline flows. By improving baseline flow repeatability and variability while reducing defectivity, we can accelerate the development of future technologies. The NanoIC pilot line is working to provide access to these advanced technologies and baselines to develop future compute systems. This will help ensure European competitiveness across the industry – from semiconductor materials, equipment and design to systems and applications.SEMI: Who are the core partners involved in this initiative?De Boeck: Key partners of the pilot line include CEA-Leti, Fraunhofer-Gesellschaft, VTT Technical Research Centre of Finland, Tyndall National Institute, and the Center for Surface Science and Nanotechnology of the University POLITEHNICA of Bucharest. This project is also supported by the Flemish government, other participating states, and the Chips Joint Undertaking of the EU Chips Act.These institutions and organizations bring a wealth of knowledge and resources, and imec compliments their efforts by providing access to its global partnerships with key industry leaders. The NanoIC pilot line is helping strengthen Europe’s global semiconductor industry leadership while aligning efforts with other regional Chips Acts. SEMI: Can you elaborate on the significance of transitioning from field-effect transistors (FinFETs) transistors to GAA nanosheet devices in CMOS technology?Samavedam: The transition from FinFETs to GAA nanosheet devices is a significant advancement in CMOS device technology. FinFETs have been the backbone of CMOS technology from the 22nm to the 3nm node. But starting at the 2nm node, nanosheet devices will need to be introduced. Nanosheet devices, including variants like Forksheet devices, are expected to drive scaling and performance through three generations – 2nm, A14, and A10. Complementary FET (CFET) architectures are also expected to be introduced around 2031 at the A7 node, which will represent another major inflection point in CMOS device design. This progression requires extensive research into new materials, process modules, equipment, and advanced patterning capabilities using high numerical aperture extreme ultraviolet (high NA EUV) lithography – all of which will be implemented on the NanoIC pilot line. FIGURE PROVIDED BY IMEC │ SCHEMATIC ILLUSTRATION OF A FUTURE COMPUTE SYSTEM. THE SYSTEM IS MADE OF LARGE MULTI-DIE ELECTRICAL-OPTICAL INTERPOSER PROVIDING ELECTRICAL AND OPTICAL INTERCONNECTS BETWEEN THE VARIOUS CHIPLETS (CPUS, GPUS, HBM). ALSO SHOWN ARE CONNECTIONS TO PACKAGE SUBSTRATE, AS WELL AS FIBER CONNECTORS AND AN INTEGRATED LASER SOURCE. CENTRAL PROCESSING UNIT (CPU); GRAPHICS PROCESSING UNIT (GPU); HIGH BANDWITH MEMORY (HBM); PROCESSING UNIT THAT CAN INCLUDE CPUS, GPUS, AND OTHER SPECIALIZED PROCESSORS (XPU); APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC); ELECTRONIC INTEGRATED CIRCUIT (EIC); FF-LEVEL: FEMTOFARAD-LEVEL; FIELD-PROGRAMMABLE GATE ARRAY (FGPA); GAAS QD: GALLIUM ARSENIDE QUANTUM DOT; INTEGRATED SILICON PHOTONICS PLATFORM 300MM (ISIPP300); REDISTRIBUTION LAYER (RDL); SILICON PHOTONICS (SIPHO); THROUGH PACKAGE VIA (TPV). SEMI: What are the key innovations necessary for advancing memory technology?Samavedam: As SRAM scaling slows, the exploration of novel, dense embedded memory concepts will become imperative. Technologies like spin orbit torque magnetic RAM (SOT-MRAM) and 2-transistor 0-capacitor (2T0C) embedded DRAM using deposited semiconductors like indium gallium zinc oxide (IGZO) are promising. These innovations address memory capacity and bandwidth challenges from new workloads in compute systems. Additionally, developing a 3D memory platform to explore future memory options will be essential for improving SRAM and DRAM. These advancements will help meet the demands of new applications like machine learning, augmented and virtual reality, and autonomous vehicles.SEMI: How do advanced interconnect technologies contribute to the future of semiconductor design?Samavedam: Advanced interconnect technologies, like chip-to-chip lateral (2.5D or interposer technologies) and vertical interconnects (3D technologies), play a crucial role in addressing memory capacity and bandwidth challenges. These technologies enable the partitioning of SoC functions into separate dies, allowing for more efficient and scalable designs. Advances like pitch scaling of micro-bumps and copper (Cu) hybrid bonding are facilitating this fine-grained partitioning of SoC functions. Additionally, optical interconnects and 3D interconnect-enabled co-packaging provide high-bandwidth and low-power connectivity at wafer scale. The rise of chiplet architectures and standardization will also increase the demand for low-cost, tight-pitch interconnect technologies like Cu/polymer redistribution layers.SEMI: How do your collaborators benefit from the NanoIC pilot line? De Boeck: One of the biggest collaborator benefits is the pilot line’s commitment to knowledge sharing through R D access and training. We invite foundries, IDMs, materials suppliers, equipment suppliers, and system companies/OEMs to jointly develop the materials, process modules, and integration flows to accelerate the development of beyond-2nm SoC technology pillars.Design pathfinding and system exploration process design kits (PDKs) will be available for start-ups, small- and medium enterprises, universities, and design and system companies to aid in prototyping and testing their designs. The NanoIC pilot line will also offer comprehensive training programs, including virtual PDK training, bootcamps for faculty, and internships and expert courses for students. To learn more, experts and key partners of the NanoIC pilot line will be presenting from 14 -16:40 at SEMICON Europa on November 12. imec’s program, ITF Chip into the Future, will highlight advancements in digital technology, capacity building through the European Chips Act, and the role of the NanoIC pilot line in accelerating beyond-2nm innovation. The conversation will also address industry requirements for pilot lines, emerging initiatives boosting Europe’s innovation and competitiveness, and perspectives on advanced materials and semiconductor equipment. Srikanth Samavedam, Senior Vice President of Semiconductor Technologies at imec, oversees programs in logic, memory, photonics, and 3D integration. Previously, he was a senior director at GlobalFoundries, leading 14nm FinFET technology into production and developing 7nm CMOS. Starting his career at Motorola, he worked on strained silicon and other advanced materials. He holds a Ph.D. in materials science and engineering from MIT and a master's degree from Purdue University. Jo De Boeck, Executive Vice President and Chief Strategy Officer at imec, oversees the company’s strategic direction and serves on its executive board. He joined imec in 1991 after earning his Ph.D. from KU Leuven and has since held various leadership roles, including head of imec’s Smart Systems and Energy Technology business unit and CTO. De Boeck is also a part-time professor at KU Leuven. Maria Daniela Perez / Communications Manager, SEMI EuropePhone: +49 160 2562977Email: [email protected]

Silicon carbide (SiC), with its wide band gap and high thermal conductivity, is increasingly favored for semiconductor power applications across several fast-growing industries. Its ability to operate at higher voltages and frequencies enables significant efficiency gains, particularly in e-mobility, where SiC offers key advantages in size, weight, and speed compared to traditional silicon-based power devices.However, as promising as SiC is, the industry still faces critical challenges in scaling to meet growing demand. Key barriers include cost, reliability, and manufacturing capacity, all of which must be addressed for SiC to fully mature.SEMI spoke with Entegris Senior Director - Advanced Technology Engagements, Office of the CTO Mark Puttock, Ph.D., to discuss the challenges of scaling SiC power chip manufacturing from a material supplier’s perspective. Puttock shared insights ahead of his presentation at the Entegris session, Cultivating a Thriving SiC Market: Tackling Key Challenges Across the Value Chain, taking place on November 14, 2024, at SEMICON Europa in Munich, Germany. Don’t miss the opportunity to engage with experts from Entegris and other industry leaders. Registration is now open. SEMI: Global megatrends like environmental crises and AI drive the necessity for SiC power semiconductors. What is the current status? Puttock: The increasing demand for efficient power electronics — fueled by global megatrends such as vehicle electrification, environmental de-carbonization, and the rise of power-hungry AI chips — drives the necessity of wide bandgap semiconductors. SiC offers advantages of weight, size, and speed over traditional silicon (Si) solutions, which are particularly vital in automotive applications 600V and above. However, SiC chip manufacturing has not reached the maturity of silicon-based processing. Greater maturity will help reduce costs, which will accelerate adoption in the market.SEMI: What are the main challenges in scaling SiC?Puttock: Challenges in scaling SiC power chip manufacturing to high volumes are not surprising. That’s because high volume producers have not been operating long enough to resolve early-stage issues. From a material perspective, SiC is more challenging to manage compared to Si. The challenges we identify include:Chemical Mechanical Planarization (CMP): SiC is nearly as hard as diamond and significantly harder than Si, making it challenging to achieve a high removal rate while maintaining both planarity and low defectivity. This step is crucial toward the end of the wafering process and before the epitaxial growth of device layers.Handling: SiC is more brittle than Si, making it more susceptible to damage or breakage.Implantation: SiC is more difficult to implant than Si, requiring higher temperatures and the use of aluminum instead of boron as a P-type implant species. Additionally, it is a significant challenge to achieve a reliable aluminum source with a long and stable lifetime.Thermal Processing for Wafer Growth and Epitaxy Processes: SiC processes run hotter than Si ( 2000° C for wafering, 1500° C for epitaxial growth), demanding resilient chamber parts to achieve good lifetimes.Sustainability: Because SiC is extremely hard, the CMP process requires significant amounts of slurry. Improving slurry recycling and wastewater management continues to be a challenge.On October 29, we will address these issues in our webinar, “Challenges in Scaling SiC Power Chip Manufacturing: A Material Supplier's Perspective” This session will provide valuable insights and considerations for advancing maturity in high-volume SiC power chip manufacturing. SEMI: Can you elaborate on the challenges associated with CMP for SiC wafers? Puttock: SiC wafers are challenging to process, requiring specialized materials and methods compared to traditional silicon. Defects in the SiC wafer crystal during non-optimized CMP processing can propagate into the device epitaxial layers. This leads to yield loss, increased electrical resistance, reduced performance, and wasted power.SiC wafers must be cut, ground, lapped, and polished to create the necessary surface properties before depositing active layers. As the demand for these devices grows, optimizing the CMP process is essential to ensure the desired surface quality and planarity required for device fabrication. For a deeper understanding of these challenges, we recommend downloading our latest white paper, “Solving CMP Challenges in High-Volume SiC Production,” which covers:Achieving maximum smoothness with high removal ratesReducing the total cost of ownership Optimizing CMP slurry and pads for the unique wafer chemistry and topology of SiC wafersSEMI: What do you mean by optimizing slurry for SiC CMP?Puttock: CMP slurry typically consists of abrasive nanoparticle powder dispersed in a chemically reactive solution. The objective is to achieve a smooth, defect-free surface (less than 1 A Ra) with a high removal rate (greater than 7 µm/m).Traditionally, achieving high removal rates and smooth surfaces required two separate slurries. This approach sometimes forced SiC wafer manufacturers to choose a defect-free surface over a faster, more efficient CMP process, depending on their fab capabilities. Today, optimization allows SiC wafer manufacturers to achieve both high polishing capacity and good final surface quality using a single slurry.Additionally, while the slurry is the most critical part of the CMP process, the pad must be compatible with the application. This ensures the desired planarity while also preventing scratches or contamination of the SiC wafer surface. Research shows that optimized thermoplastic polyurethane CMP pads outperform traditional thermoset polyurethane pads. The optimized pads minimize surface damage and enhance removal rates due to their bulk hardness.SEMI: What are the future challenges for SiC devices? Puttock: SiC devices are increasingly favored for their superior energy efficiency and reduced environmental impact. However, the SiC manufacturing process presents challenges due to its high-temperature operations, which consumes significant amounts of energy and shortens the lifespan of chamber components. To address this, improving efficiency in these processes will be crucial in the coming years.Recycling is another important challenge. For example, CMP slurries present an opportunity for water recycling and conservation. At Entegris, we are committed to this issue and are actively collaborating with key industry players to enhance material circularity and prioritize sustainability in our new product development.SEMI: How is Entegris contributing to advancements in SiC technology, and what initiatives or partnerships do you have planned for the near future? Puttock: Entegris is an active member of the SEMI Global Automotive Advisory Council (GAAC) and participates in a working group focused on SiC with key industry leaders such as Volkswagen, BMW, Porsche Consulting, onsemi, Infineon, STMicroelectronics, and others. Our engagement spans the entire semiconductor supply chain, collaborating with integrated device manufacturers and original equipment manufacturers in fabs worldwide. Additionally, we recently announced our latest long-term agreement with onsemi, which underscores our commitment to advancing SiC technology.SEMI: What are your expectations regarding your participation at SEMICON Europa? Puttock: SEMICON Europa is a unique platform to connect with the semiconductor and automotive ecosystems. Last year, we organized a highly successful SiC session in collaboration with SEMI at both SEMICON West and SEMICON Europa, focusing on “Connecting the Automotive Ecosystem Towards More Mature SiC Manufacturing.”This year, we will continue the discussion with industry leaders during our session, “Cultivating a Thriving SiC Market: Tackling Key Challenges Across the Value Chain.” Our goal is to provide insights and propose solutions that will enable SiC power chips to achieve their anticipated role in future technology ecosystems.We will present alongside Porsche Consulting, and the talks will be followed by a panel discussion that will explore the current state and future prospects of SiC technology in power electronics. We invite visitors to join us at the Executive Forum on Thursday, November 14, from 1:40 – 3:00 p.m. and to visit us at Silicon Saxony booth 219 in Hall C1.About Mark PuttockMark Puttock, Ph.D., is the senior director of advanced technology engagements in the office of the CTO at Entegris. He has worked in the semiconductor industry for over 30 years with a background in physics and plasma processing. As a team member of the Entegris CTO office since 2014, Mark has followed technology trends and collaborated with Entegris’ global product development teams to develop timely and differentiated new materials, chemistries, and components for all the world’s semiconductor manufacturers. Maria Daniela Perez is Communications Manager at SEMI Europe.

Electronics industry experts and researchers will offer insights into ALD trends and adoption at Beneq ALD TechDay at SEMICON Europa 2023, Nov. 14-17 in Munich, Germany.

SEMI spoke with Rebecca Dobson, Corporate Vice President EMEA at Cadence Design Systems, about semiconductor industry growth drivers and why semiconductor design is crucial to meeting device scaling challenges today and beyond.

ISS Europe 2023 speakers focused on the influence of the EU Chips Act on the strategic direction of Europe’s semiconductor industry through 2030 and the legislation’s potential as a powerful instrument to strengthen Europe’s semiconductor industry.

ISS Europe 2023 speakers focused on the influence of the EU Chips Act on the strategic direction of Europe’s semiconductor industry through 2030 and the legislation’s potential as a powerful instrument to strengthen Europe’s semiconductor industry.

Comet Yxlon provides X-ray and  computed tomography (CT) inspection solutions for R&D labs and production environments, including semiconductor manufacturing facilities, to enhance their productivity.

Coming in the wake of the COP27, the Smart and Green Manufacturing Summit at SEMICON Europa 2022 (Munich, 15-17 November) had a timely focus on the semiconductor industry’s contribution to meeting the United Nations’ target of limiting global warming to 1.5°C above pre-industrial levels.

SEMI spoke with Christian Driller, Vice President of Research and Development at Comet Yxlon, about opportunities to accelerate time-to-market and increase yield for advanced packaging manufacturers through x-ray inspection.

Electronics industry experts will offer insights into key aspects of the radio frequency (RF) challenge – from materials and devices to ICs and modules – at ITF Beyond 5G at SEMICON Europa 2022, Nov. 15-18 in Munich, Germany.