SEMICON Europa

Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain.At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth trajectory of this critical sector and Europe’s potential to lead in next-generation packaging solutions.Market Momentum Fueled by AI and HPCRomain Fraux, Chief Research Officer at Yole Group, forecasted that global revenues for advanced packaging will grow from $46.1 billion in 2024 to $79.4 billion by 2030. “Everything is linked to AI and high-performance computing (HPC),” said Fraux, while also emphasizing the growing relevance of automotive applications in driving demand.Romain Fraux, Chief Research Officer, Yole GroupThis demand is accelerating innovation across the supply chain. One emerging area is panel-level packaging, which breaks away from traditional round wafers. As Andreas Wocko, Sales Manager at Lam Research, observed, “Since the 1970s, the semiconductor industry has built on wafers. Now we are not just scaling, we are reshaping, building in a square format for the first time” – an innovation which substantially increases area efficiency and reduces device cost. Andreas Wocko, Sales Manager Europe, Lam ResearchTechnology Transformation from Lab to FabEurope is already investing in the foundational technologies that will power tomorrow’s packaging systems. Rolf Aschenbrenner, Deputy Director of Fraunhofer IZM, the home of the European Union’s APECS advanced packaging pilot line, discussed ongoing research into functional interposers, routing density, and organic interposers. “Our goal is to show how a new design philosophy incorporating chiplets can be brought to the industrial systems level,” said Aschenbrenner.Rolf Aschenbrenner, Director Deputy, Fraunhofer IZMThese breakthroughs are essential, as pitch sizes shrink and new materials emerge. Dr. Jessica Stubbe, Global Application Manager at MKS Atotech, described how interconnect densities have doubled in the past two years, with the industry moving to pitch sizes of less than 10µm. Stubbe said this new technology “will be enabled by a move from traditional solder-based interconnects to copper-to-copper hybrid bonding to provide higher density I/Os and lower resistance.” Jessica Stubbe, Global Application Manager, MKS AtotechInnovation Meets Real-World IntegrationThis increased density carries thermal risks with it. As Ram Trichur, Global Head of Semiconductor Packaging at Henkel Corporation, said, “New architectures enabled by advanced packaging are putting power devices on the backside, interposer or substrate, and this addition of more power delivery components in the package creates more local hotspots.”The reduced feature sizes inside the latest packages make it more difficult than ever to apply thermal interface materials. “At Henkel, we are now making 1µm-level fillers which enable the effective filling of gaps as small as 7µm,” said Trichur.Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationOne of the applications which stands to gain the most from the development of advanced packaging technology is silicon photonics. Dr. Himani Kamineni, Director for Advanced Packaging at GlobalFoundries, described how co-packaged optics (CPO) brings photonics directly inside the package, reducing connection lengths from centimeters down to millimeters, and providing higher bandwidth and lower latency at lower power. “Advanced packaging and CPO are foundational elements for AI and data centers to enable scalability to the next generation of compute,” said Kamineni. “But it will need a lot of packaging innovation: silicon interposers, copper-to-copper interconnects, and fiber-attach units for precise alignment.” Himani Kamineni, Director, Advanced Packaging, GlobalFoundriesReliability and Test Under PressureIn the transition to new packaging technology, it is crucial that the industry does not lose sight of the reliability standards which have made semiconductors so valuable in sectors such as automotive and aerospace. Amar Mavinkurve, Director of Materials and Labs Package Innovation at NXP Semiconductors, warned the finer spacing and smaller feature sizes in the latest packages posed a problem for reliability and long-term performance. He said, “We are dealing now not just with one failure mechanism, but with multiple. So, the way that we are used to describing behavior in models will not necessarily hold in future. Even industry standards might not hold.”Discussing new technologies such as copper-to-copper interconnects, Mavinkurve pointed out that failure would not be due to a single event, but to processes such as electromigration, corrosion, and thermomechanical effects. To model reliability properly in future, he said, “we need to move from a physics of failure to a physics of degradation.” Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP SemiconductorsFabio Pizza, Business Segment Manager at Advantest Europe focused on quality and failure. With geometry scaling toward 1nm, early identification of known-good dies is essential to optimize cost and test coverage. Pizza said that, while device manufacturers need to keep time-to-market and the cost of test under tight control, they are also trying to figure out how to increase test coverage. “In a modern GPU, even a 100 DPPM quality process leaves 20 million transistors untested,” he said. Fabio Pizza, Business Segment Manager, Advantest EuropeEurope’s Position in the Global EcosystemThe conference concluded with a panel discussion about the prospects for Europe in the global advanced packaging market. According to Yole’s Romain Fraux, there is a strong ecosystem in Europe: “Europe’s strengths include specialized packaging service providers in the photonics and power market segments, as well as many packaging equipment manufacturers,” said Fraux. This resonated with the instincts of NXP’s Amar Mavinkurve and Advantest’s Fabio Pizza. Mavinkurve said: “We should focus on what we are already good at doing. It will be challenging to compete with advanced packaging providers elsewhere for AI and HPC business.”Ram Trichur of Henkel, however, urged the industry in Europe, “Do not take your foot off the gas on advanced packaging. You cannot do the full stack here, but in a technology such as CPO, there is a lot of innovation in Europe, and there is scope to add the manufacturing of these devices on top of the research capabilities.”Chris Scanlan, Senior Vice President of Technology at Besi, raised the idea of shifting production toward Eastern Europe. But Trichur cautioned that talent and infrastructure remain limiting factors in that strategy. From left to right: Chris Scanlan, Senior Vice President Technology, Besi;Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP Semiconductors; Fabio Pizza, Business Segment Manager, Advantest Europe; Rolf Aschenbrenner, Director Deputy, Fraunhofer IZM; Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationCollaboration is the Path ForwardSpeakers throughout the conference echoed a common message: advanced packaging is reshaping the semiconductor landscape, and global collaboration will be essential to success. “It is impossible for one country or one region to do the entire stack,” Trichur concluded. “Innovation must be matched with strategic partnerships to bring advanced packaging from research to real-world impact.”On behalf of SEMI, the SEMI Europe team would like to thank the industry leaders whose expertise and enthusiasm made this conference a resounding success. SEMI ContactCassandra Melvin, Senior Director of Business Development and OperationsEmail: [email protected]

The sensor revolution is shaping the future of connectivity, with innovation in MEMS and imaging technologies paving the way for a smarter and more integrated world.As the world becomes increasingly interconnected, MEMS and imaging sensor technologies are driving transformative changes across industries, shaping the future of connectivity, intelligence, and sustainability. Powered by advances in miniaturization, AI integration, and sustainable design, MEMS and imaging technologies are enabling groundbreaking applications—from autonomous vehicles to wearable health devices—while addressing urgent global challenges like climate change and energy efficiency. At the MEMS Imaging Sensors Summit 2024, Laith Altimime, President of SEMI Europe, emphasized the pivotal role of MEMS and imaging technologies. Setting the stage for discussions on technological breakthroughs and market trends, Altimime remarked, “Sensors are at the heart of the next wave of innovation, enabling unprecedented levels of intelligence that are transforming industries and fostering a smarter, more sustainable, and seamlessly connected future.”Laith Altimime, President, SEMI EuropeStefan Finkbeiner, CEO of Bosch Sensortec, underscored in his opening keynote how advanced sensor technologies are enabling life-changing use cases. “Sensors are all around us, though we don’t always notice them,” emphasizing sensors’ ubiquitous role in smartphones, wearables, and hearables. Finkbeiner highlighted miniaturization as a key challenge, noting that even as sensors continue to shrink, they are increasingly integrated with edge AI to enable efficient, local decision-making.Stefan Finkbeiner, CEO, Bosch SensortecSimone Ferri, APMS Group Vice-President and MEMS Sub-Group General Manager at STMicroelectronics, highlighted the pivotal role of sensors as a bridge between the physical and digital world, noting “the most sophisticated machine is the human – so it is best to emulate human capabilities to enable the next generation of devices to accurately measure the parameters of your body.” Ferri stressed the importance of sustainability, advocating for smart, transformative, and precise sensors that provide meaningful data with optimal efficiency. By aligning technological innovation with environmental responsibility, Simone Ferri demonstrated how sensorization can enhance lives while enabling a net-zero transition across industries.Simone Ferri, APMS Group Vice-President and MEMS Sub-Group General Manager, STMicroelectronicsMEMS Growth Fueled by Piezo Materials and ElectrificationJean-Christophe Eloy, CEO and President of Yole Group, grounded the discussion in market data, forecasting a 5% CAGR for the MEMS market, which is set to exceed $20 billion by 2029. He highlighted key trends such as the increasing sophistication of automotive sensors—more cameras, higher resolution—and the impact of electrification. On the technology front, Eloy noted a “strong shift towards piezoelectric (piezo) MEMS,” driven by advancement in new materials like Lead Zirconate Titanate (PZT), Aluminum Nitride (AIN), and Scandium-doped Aluminum Nitride (ScAIN).Jean-Christophe Eloy, CEO and President, Yole GroupAlissa Fitzgerald, CEO of A.M. Fitzgerald Associates explored the expanding roles of MEMS technology in new domains, such as fiber optics for data centers. “Photonics is in the news,” she remarked, highlighting its potential to deliver 40% power savings compared to copper technologies. “MEMS manufacturing is set to evolve by 2030 and beyond,” said Fitzgerald, emphasizing the continued innovation in traditional wafer-based processes through the adoption of advanced thin-film materials like piezoelectrics and GaN. Furthermore, Fitzgerald discussed emerging manufacturing techniques such as 3D-printed MEMS and biodegradable materials to enable low-cost, sustainable sensors.Alissa Fitzgerald, CEO of A.M. Fitzgerald AssociatesAdding to the conversation on manufacturing, Jessica Gomez, CEO of Rogue Valley Microdevices, shared her perspective on how 300mm-capable MEMS foundries could “change the game,” improving production efficiency and lowering costs. Gomez also outlined the unique challenges of MEMS manufacturing, including the need for custom processes and the high-mix, low-volume nature of production.Advancing Smart Mobility Through Interoperable NetworksSmart mobility gained significant traction as Patrice Ancel, In-Vehicle Technologies Leader at BMW, tackled the intricacies of in-vehicle networking. Ancel shed light on the complexities of today’s vehicles, which contain 20,000 components and over 100 electronic control units (ECUs) from multiple suppliers. His message was clear: “Interoperability is key for us; without interoperability, none of this will happen.” Ancel’s call for collaboration resonated throughout the summit, highlighting the critical role of teamwork in driving innovation and progress within the automotive industry.Patrice Ancel, In-Vehicle Technologies Leader, BMWA Vision for the Future: Sustainability, Collaboration, and InnovationThe MEMS Imaging Sensors Summit demonstrated how collaboration, sustainability, and innovation are driving the sensor industry forward. From addressing market trends to tackling manufacturing challenges, the discussions revealed a shared commitment to creating a smarter, more connected world.On behalf of SEMI, the SEMI Europe team would like to thank the industry leaders whose expertise and enthusiasm made this summit a resounding success. SEMI ContactAna Bernardo, Manager of Technology ProgramsEmail: [email protected] Mobile: +49 175 4129 764Sitong He, Communications Manager Email: [email protected]: +49 151 5546 2638

Integrated photonics offers the semiconductor industry a new way to increase the speed and capability of classical compute functions, as well as enabling quantum computing. The III-V Summit, hosted by SEMI Europe in partnership with Photon Delta at SEMICON Europa, opened with a compelling question: why is a photonics summit taking place in the middle of a semiconductor event? Ajit Manocha, President and CEO of SEMI, highlighted the growing convergence of the semiconductor and photonics industries, stating, “It is my firm belief that a boost to Moore’s Law will come from the III-V world.” Declaring that the rate of growth in integrated photonics is set to pick up substantially, Manocha assured, “I will be your ambassador to make sure that the III-V technologies gain far greater visibility than they have today.”Ajit Manocha, President and CEO, SEMIThe promise of new III-V technologies is generating significant excitement within the semiconductor industry. Abdul Rahim, Ecosystem Manager at PhotonWorld, acknowledged the reality that today’s III-V device industry operates in a limited sphere, stating, “The III-V world is still at the interface of industry and academia. There is one main application for III-V devices – transceivers for data centers.” Abdul Rahim, Ecosystem Manager, PhotonWorld Carlos Lee, Director General of the European Photonics Industry Consortium (EPIC), echoed this message, “Photonics is not so much an industry today; it’s an ecosystem. It lacks the standards, roadmaps, and market data that a full-fledged industry needs – but we are getting there.” Carlos Lee, Director General, European Photonics Industry Consortium (EPIC)However, Rahim pointed to a number of trends that are driving the growth of III-V technology for integrated photonics. One key development is large-scale integration, “over the years, the number of devices in one photonics integrated chip (PIC) has been growing fast, reaching tens of thousands of components on-chip,” Rahim explained. Additionally, the widening frequency range supported by III-V devices is unlocking new applications beyond the telecom sector. Broad Scope of Research into III-V Technology for Integrated PhotonicsResearch into III-V technology spans an impressive range of materials, processes and applications. Nick Singh, CTO at Compound Semiconductor Applications (CSA) Catapult, a government-backed technology incubator, described in detail the most important fields of research that are driving innovation in integrated photonics. “III-V materials are special because they can be engineered,” Singh explained. Highlighting their potential role in advancing quantum computing, Singh added, “The ability to use new materials is crucial to reducing the reliance on algorithmic compensation for errors and non-linearity in hardware.” Nick Singh, CTO, Compound Semiconductor Applications Catapult However, Singh emphasized the need for the photonics industry to address structural challenges that could hinder progress. “Collaboration is crucial to standardize process development kits (PDKs) for photonics device fabrication processes—it’s like the Wild West in PDKs right now,” Singh remarked. “Additionally, the availability of raw materials presents a significant challenge.”The truth of this warning was confirmed by Diane Scott, Vice President of TECHCET, stating, "The US has deemed gallium to be the number one supply chain risk among a list of 50 raw materials, and the European Union (EU) has identified gallium as a critical raw material."Diane Scott, Vice President, TECHCETSuch geopolitical concerns have done little to dampen the intensity of research in III-V technology. One of the powerhouses of integrated photonics research is IBM, and Heike Riel, a Fellow at IBM Research with a special interest in quantum computing, revealed promising avenues that IBM is exploring. “IBM has developed local III-V-on-silicon heteroepitaxy, “Riel explained. “Using a direct growth method, we can grow vertical, lateral, and even 3D structures in III-V, such as stacked GaAs structures.” Riel highlighted the potential applications of this technology in emerging processor designs, including the Artificial Intelligence Unit (AIU) and analog computing devices with in-memory logic. “Here, we can deploy GaAs as a photorefractive material, used as a grating, to perform the same function as conventional electronic non-volatile memory in an analog computer chip,” Riel noted. Heike Riel, IBM Fellow, IBM ResearchAlso at the forefront of photonics integration is Black Semiconductor, a start-up company based in Aachen, Germany, which is developing devices using graphene. Cedric Huyghebaert, CTO of Black Semiconductor, shared the company’s vision, “We want to use electronics to compute, and photonics to transfer data, and bring both functions together on the same chip.” Black Semiconductor’s mission is to become the first foundry to offer integrated graphene technology. “Our ambition is to integrate graphene in line with semiconductor standards using semiconductor tools – avoiding the need for exotic processing technologies,” Huyghebaert explained. “We also aim to demonstrate co-integrated photonics on a 300mm wafer system, regardless of the process node. In doing so, we want to prove that deep technological innovation of this kind is possible in Europe.”Cedric Huyghebaert, CTO, Black Semiconductor GmbH Bringing Integrated Photonics to the MassesAs III-V technology develops to enable a broader range of integrated photonics applications beyond the telecom market, experts are recognizing the need for it to become more accessible if it is to be adopted by a wider range of manufacturers. Joni Mellin, manager of the photonics business line at the X-Fab Group, emphasized, “As an industry, we need to bring electronics design automation (EDA) tools up to a level of capability that matches that of the silicon world, so that you do not need a PhD to do product design – we need to make it accessible to ordinary electronics engineers.” Joni Mellin, BL Manager Photonics, X-FAB GroupAdoption of the technology also requires access to production capacity. Peter Maat, Senior Product Manager at SMART Photonics, an open foundry for indium phosphide (InP) programmable interface controllers (PICs), highlighted the challenges in this area. Maat explained that the availability of the foundry as “not a trivial capability,” because many InP fabs are run by integrated device manufacturers, and are closed to other users. The SMART Photonics business model aims to provide a comprehensive enablement service for fabless manufacturing of PICs. “Our responsibility is to produce stable, manufacturable building blocks that we make available to designers and to provide a platform which enables our circuit building blocks to be combined into an integrated photonics circuit,” Maat said.Peter Maat, Senior Product Manager, SMART Photonics Jayakrishnan Chandrappan, Head of Advanced Packaging Technology at CSA Catapult, also emphasized the importance of access to production capability. “The CSA Catapult has one of the world’s only sub-10micron hybridization facilities for advanced packaging that is open to third-party users,” Chandrappan noted.Jayakrishnan Chandrappan, Head of Technology, Head of Technology - Advanced Packaging, Compound Semiconductor Applications CatapultPromising Future for Integrated PhotonicsAs the summit concluded, the atmosphere was charged with optimism about the future of integrated photonics. The discussions highlighted how III-V materials, combined with advanced packaging, are set to play a pivotal role in shaping next generation technologies. A recurring theme throughout the event was the profound impact III-V materials will have, as they poised to become a corner stone of virtually every emerging technological advancement. SEMI ContactLaith Altimime, President of SEMI EuropeEmail: [email protected]

In the rapidly-evolving semiconductor industry, maintaining a competitive edge is crucial. To position Europe at the forefront of global semiconductor innovation, imec is leading the NanoIC pilot line initiative. Aligned with the European Chips Act, this initiative is a strategic move to bolster Europe's leadership in key markets like high performance computing, automotive, and healthcare.SEMI spoke with Srikanth Samavedam and Jo De Boeck from imec, Belgium, to learn more about the NanoIC pilot line and to better understand its goals, challenges, and prospects. From transitioning to gate-all-around (GAA) nanosheet devices, to developing advanced memory technologies and interconnects, this conversation highlights the cutting-edge advancements made possible through collaboration across the industry’s value chain.SEMI: How is the NanoIC pilot line working to revolutionize the semiconductor industry, and what are its main objectives?Samavedam: The NanoIC pilot line is a European initiative aimed at bridging the gap between R D and industrial innovation. The project is creating a beyond-2nm system-on-chip (SoC) pilot line, developing advanced logic, memory, and interconnect technologies. This effort supports the European Chips Act's vision for leadership and competitiveness in global semiconductor innovation, particularly in critical markets like high performance computing, communication, automotive, energy, and healthcare. However, advanced technologies come with more complexity, and addressing these complexity challenges requires more mature module baseline flows. By improving baseline flow repeatability and variability while reducing defectivity, we can accelerate the development of future technologies. The NanoIC pilot line is working to provide access to these advanced technologies and baselines to develop future compute systems. This will help ensure European competitiveness across the industry – from semiconductor materials, equipment and design to systems and applications.SEMI: Who are the core partners involved in this initiative?De Boeck: Key partners of the pilot line include CEA-Leti, Fraunhofer-Gesellschaft, VTT Technical Research Centre of Finland, Tyndall National Institute, and the Center for Surface Science and Nanotechnology of the University POLITEHNICA of Bucharest. This project is also supported by the Flemish government, other participating states, and the Chips Joint Undertaking of the EU Chips Act.These institutions and organizations bring a wealth of knowledge and resources, and imec compliments their efforts by providing access to its global partnerships with key industry leaders. The NanoIC pilot line is helping strengthen Europe’s global semiconductor industry leadership while aligning efforts with other regional Chips Acts. SEMI: Can you elaborate on the significance of transitioning from field-effect transistors (FinFETs) transistors to GAA nanosheet devices in CMOS technology?Samavedam: The transition from FinFETs to GAA nanosheet devices is a significant advancement in CMOS device technology. FinFETs have been the backbone of CMOS technology from the 22nm to the 3nm node. But starting at the 2nm node, nanosheet devices will need to be introduced. Nanosheet devices, including variants like Forksheet devices, are expected to drive scaling and performance through three generations – 2nm, A14, and A10. Complementary FET (CFET) architectures are also expected to be introduced around 2031 at the A7 node, which will represent another major inflection point in CMOS device design. This progression requires extensive research into new materials, process modules, equipment, and advanced patterning capabilities using high numerical aperture extreme ultraviolet (high NA EUV) lithography – all of which will be implemented on the NanoIC pilot line. FIGURE PROVIDED BY IMEC │ SCHEMATIC ILLUSTRATION OF A FUTURE COMPUTE SYSTEM. THE SYSTEM IS MADE OF LARGE MULTI-DIE ELECTRICAL-OPTICAL INTERPOSER PROVIDING ELECTRICAL AND OPTICAL INTERCONNECTS BETWEEN THE VARIOUS CHIPLETS (CPUS, GPUS, HBM). ALSO SHOWN ARE CONNECTIONS TO PACKAGE SUBSTRATE, AS WELL AS FIBER CONNECTORS AND AN INTEGRATED LASER SOURCE. CENTRAL PROCESSING UNIT (CPU); GRAPHICS PROCESSING UNIT (GPU); HIGH BANDWITH MEMORY (HBM); PROCESSING UNIT THAT CAN INCLUDE CPUS, GPUS, AND OTHER SPECIALIZED PROCESSORS (XPU); APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC); ELECTRONIC INTEGRATED CIRCUIT (EIC); FF-LEVEL: FEMTOFARAD-LEVEL; FIELD-PROGRAMMABLE GATE ARRAY (FGPA); GAAS QD: GALLIUM ARSENIDE QUANTUM DOT; INTEGRATED SILICON PHOTONICS PLATFORM 300MM (ISIPP300); REDISTRIBUTION LAYER (RDL); SILICON PHOTONICS (SIPHO); THROUGH PACKAGE VIA (TPV). SEMI: What are the key innovations necessary for advancing memory technology?Samavedam: As SRAM scaling slows, the exploration of novel, dense embedded memory concepts will become imperative. Technologies like spin orbit torque magnetic RAM (SOT-MRAM) and 2-transistor 0-capacitor (2T0C) embedded DRAM using deposited semiconductors like indium gallium zinc oxide (IGZO) are promising. These innovations address memory capacity and bandwidth challenges from new workloads in compute systems. Additionally, developing a 3D memory platform to explore future memory options will be essential for improving SRAM and DRAM. These advancements will help meet the demands of new applications like machine learning, augmented and virtual reality, and autonomous vehicles.SEMI: How do advanced interconnect technologies contribute to the future of semiconductor design?Samavedam: Advanced interconnect technologies, like chip-to-chip lateral (2.5D or interposer technologies) and vertical interconnects (3D technologies), play a crucial role in addressing memory capacity and bandwidth challenges. These technologies enable the partitioning of SoC functions into separate dies, allowing for more efficient and scalable designs. Advances like pitch scaling of micro-bumps and copper (Cu) hybrid bonding are facilitating this fine-grained partitioning of SoC functions. Additionally, optical interconnects and 3D interconnect-enabled co-packaging provide high-bandwidth and low-power connectivity at wafer scale. The rise of chiplet architectures and standardization will also increase the demand for low-cost, tight-pitch interconnect technologies like Cu/polymer redistribution layers.SEMI: How do your collaborators benefit from the NanoIC pilot line? De Boeck: One of the biggest collaborator benefits is the pilot line’s commitment to knowledge sharing through R D access and training. We invite foundries, IDMs, materials suppliers, equipment suppliers, and system companies/OEMs to jointly develop the materials, process modules, and integration flows to accelerate the development of beyond-2nm SoC technology pillars.Design pathfinding and system exploration process design kits (PDKs) will be available for start-ups, small- and medium enterprises, universities, and design and system companies to aid in prototyping and testing their designs. The NanoIC pilot line will also offer comprehensive training programs, including virtual PDK training, bootcamps for faculty, and internships and expert courses for students. To learn more, experts and key partners of the NanoIC pilot line will be presenting from 14 -16:40 at SEMICON Europa on November 12. imec’s program, ITF Chip into the Future, will highlight advancements in digital technology, capacity building through the European Chips Act, and the role of the NanoIC pilot line in accelerating beyond-2nm innovation. The conversation will also address industry requirements for pilot lines, emerging initiatives boosting Europe’s innovation and competitiveness, and perspectives on advanced materials and semiconductor equipment. Srikanth Samavedam, Senior Vice President of Semiconductor Technologies at imec, oversees programs in logic, memory, photonics, and 3D integration. Previously, he was a senior director at GlobalFoundries, leading 14nm FinFET technology into production and developing 7nm CMOS. Starting his career at Motorola, he worked on strained silicon and other advanced materials. He holds a Ph.D. in materials science and engineering from MIT and a master's degree from Purdue University. Jo De Boeck, Executive Vice President and Chief Strategy Officer at imec, oversees the company’s strategic direction and serves on its executive board. He joined imec in 1991 after earning his Ph.D. from KU Leuven and has since held various leadership roles, including head of imec’s Smart Systems and Energy Technology business unit and CTO. De Boeck is also a part-time professor at KU Leuven. Maria Daniela Perez / Communications Manager, SEMI EuropePhone: +49 160 2562977Email: [email protected]

Silicon carbide (SiC), with its wide band gap and high thermal conductivity, is increasingly favored for semiconductor power applications across several fast-growing industries. Its ability to operate at higher voltages and frequencies enables significant efficiency gains, particularly in e-mobility, where SiC offers key advantages in size, weight, and speed compared to traditional silicon-based power devices.However, as promising as SiC is, the industry still faces critical challenges in scaling to meet growing demand. Key barriers include cost, reliability, and manufacturing capacity, all of which must be addressed for SiC to fully mature.SEMI spoke with Entegris Senior Director - Advanced Technology Engagements, Office of the CTO Mark Puttock, Ph.D., to discuss the challenges of scaling SiC power chip manufacturing from a material supplier’s perspective. Puttock shared insights ahead of his presentation at the Entegris session, Cultivating a Thriving SiC Market: Tackling Key Challenges Across the Value Chain, taking place on November 14, 2024, at SEMICON Europa in Munich, Germany. Don’t miss the opportunity to engage with experts from Entegris and other industry leaders. Registration is now open. SEMI: Global megatrends like environmental crises and AI drive the necessity for SiC power semiconductors. What is the current status? Puttock: The increasing demand for efficient power electronics — fueled by global megatrends such as vehicle electrification, environmental de-carbonization, and the rise of power-hungry AI chips — drives the necessity of wide bandgap semiconductors. SiC offers advantages of weight, size, and speed over traditional silicon (Si) solutions, which are particularly vital in automotive applications 600V and above. However, SiC chip manufacturing has not reached the maturity of silicon-based processing. Greater maturity will help reduce costs, which will accelerate adoption in the market.SEMI: What are the main challenges in scaling SiC?Puttock: Challenges in scaling SiC power chip manufacturing to high volumes are not surprising. That’s because high volume producers have not been operating long enough to resolve early-stage issues. From a material perspective, SiC is more challenging to manage compared to Si. The challenges we identify include:Chemical Mechanical Planarization (CMP): SiC is nearly as hard as diamond and significantly harder than Si, making it challenging to achieve a high removal rate while maintaining both planarity and low defectivity. This step is crucial toward the end of the wafering process and before the epitaxial growth of device layers.Handling: SiC is more brittle than Si, making it more susceptible to damage or breakage.Implantation: SiC is more difficult to implant than Si, requiring higher temperatures and the use of aluminum instead of boron as a P-type implant species. Additionally, it is a significant challenge to achieve a reliable aluminum source with a long and stable lifetime.Thermal Processing for Wafer Growth and Epitaxy Processes: SiC processes run hotter than Si ( 2000° C for wafering, 1500° C for epitaxial growth), demanding resilient chamber parts to achieve good lifetimes.Sustainability: Because SiC is extremely hard, the CMP process requires significant amounts of slurry. Improving slurry recycling and wastewater management continues to be a challenge.On October 29, we will address these issues in our webinar, “Challenges in Scaling SiC Power Chip Manufacturing: A Material Supplier's Perspective” This session will provide valuable insights and considerations for advancing maturity in high-volume SiC power chip manufacturing. SEMI: Can you elaborate on the challenges associated with CMP for SiC wafers? Puttock: SiC wafers are challenging to process, requiring specialized materials and methods compared to traditional silicon. Defects in the SiC wafer crystal during non-optimized CMP processing can propagate into the device epitaxial layers. This leads to yield loss, increased electrical resistance, reduced performance, and wasted power.SiC wafers must be cut, ground, lapped, and polished to create the necessary surface properties before depositing active layers. As the demand for these devices grows, optimizing the CMP process is essential to ensure the desired surface quality and planarity required for device fabrication. For a deeper understanding of these challenges, we recommend downloading our latest white paper, “Solving CMP Challenges in High-Volume SiC Production,” which covers:Achieving maximum smoothness with high removal ratesReducing the total cost of ownership Optimizing CMP slurry and pads for the unique wafer chemistry and topology of SiC wafersSEMI: What do you mean by optimizing slurry for SiC CMP?Puttock: CMP slurry typically consists of abrasive nanoparticle powder dispersed in a chemically reactive solution. The objective is to achieve a smooth, defect-free surface (less than 1 A Ra) with a high removal rate (greater than 7 µm/m).Traditionally, achieving high removal rates and smooth surfaces required two separate slurries. This approach sometimes forced SiC wafer manufacturers to choose a defect-free surface over a faster, more efficient CMP process, depending on their fab capabilities. Today, optimization allows SiC wafer manufacturers to achieve both high polishing capacity and good final surface quality using a single slurry.Additionally, while the slurry is the most critical part of the CMP process, the pad must be compatible with the application. This ensures the desired planarity while also preventing scratches or contamination of the SiC wafer surface. Research shows that optimized thermoplastic polyurethane CMP pads outperform traditional thermoset polyurethane pads. The optimized pads minimize surface damage and enhance removal rates due to their bulk hardness.SEMI: What are the future challenges for SiC devices? Puttock: SiC devices are increasingly favored for their superior energy efficiency and reduced environmental impact. However, the SiC manufacturing process presents challenges due to its high-temperature operations, which consumes significant amounts of energy and shortens the lifespan of chamber components. To address this, improving efficiency in these processes will be crucial in the coming years.Recycling is another important challenge. For example, CMP slurries present an opportunity for water recycling and conservation. At Entegris, we are committed to this issue and are actively collaborating with key industry players to enhance material circularity and prioritize sustainability in our new product development.SEMI: How is Entegris contributing to advancements in SiC technology, and what initiatives or partnerships do you have planned for the near future? Puttock: Entegris is an active member of the SEMI Global Automotive Advisory Council (GAAC) and participates in a working group focused on SiC with key industry leaders such as Volkswagen, BMW, Porsche Consulting, onsemi, Infineon, STMicroelectronics, and others. Our engagement spans the entire semiconductor supply chain, collaborating with integrated device manufacturers and original equipment manufacturers in fabs worldwide. Additionally, we recently announced our latest long-term agreement with onsemi, which underscores our commitment to advancing SiC technology.SEMI: What are your expectations regarding your participation at SEMICON Europa? Puttock: SEMICON Europa is a unique platform to connect with the semiconductor and automotive ecosystems. Last year, we organized a highly successful SiC session in collaboration with SEMI at both SEMICON West and SEMICON Europa, focusing on “Connecting the Automotive Ecosystem Towards More Mature SiC Manufacturing.”This year, we will continue the discussion with industry leaders during our session, “Cultivating a Thriving SiC Market: Tackling Key Challenges Across the Value Chain.” Our goal is to provide insights and propose solutions that will enable SiC power chips to achieve their anticipated role in future technology ecosystems.We will present alongside Porsche Consulting, and the talks will be followed by a panel discussion that will explore the current state and future prospects of SiC technology in power electronics. We invite visitors to join us at the Executive Forum on Thursday, November 14, from 1:40 – 3:00 p.m. and to visit us at Silicon Saxony booth 219 in Hall C1.About Mark PuttockMark Puttock, Ph.D., is the senior director of advanced technology engagements in the office of the CTO at Entegris. He has worked in the semiconductor industry for over 30 years with a background in physics and plasma processing. As a team member of the Entegris CTO office since 2014, Mark has followed technology trends and collaborated with Entegris’ global product development teams to develop timely and differentiated new materials, chemistries, and components for all the world’s semiconductor manufacturers. Maria Daniela Perez is Communications Manager at SEMI Europe.

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