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The semiconductor industry is undergoing a rapid transformation. Artificial intelligence (AI) applications, such as agentic and physical AI, push compute demands to unprecedented heights, prompting the semiconductor industry to push the boundaries of 2nm technology and beyond. Yet, as we move to these advanced semiconductor technology nodes, it has become increasingly challenging for academic research to remain closely connected with the fast-evolving industrial developments, limiting academic researchers in driving innovation. Europe’s NanoIC pilot line, a pioneering European initiative, hosted by imec, is addressing this challenge by offering pathfinding process design kits (P-PDKs). To cover the potential of these P-PDKs and their impact on Europe’s semiconductor ecosystem, we sat together with Professor Mehdi Tahoori (professor at Karlsruhe Institute of Technology) and Anita Farokhnejad (DTCO Program Manager at imec).SEMI: What exactly is a P-PDK, and how does it differ from traditional PDKs?Farokhnejad: At its core, a process design kit (PDK) is a software environment that enables circuit designers to simulate, validate, and optimize chip designs using realistic models of chip technology. Consider it a blueprint or a simulation toolkit allowing chip designers to explore performance, power, and manufacturability of a new chip architecture in a virtual sandbox. What sets P-PDKs apart is that they anticipate future technologies. Unlike traditional PDKs, which are based on existing technologies, P-PDKs are built on predictive models of future nodes and architectures. This allows researchers to explore system-level trade-offs, assess architectural implications, and prepare design flows before a technology reaches maturity. SEMI: Why are they so crucial for academia?Tahoori: For decades, academic researchers could contribute to semiconductor innovation using abstraction layers that allowed them to design and test new architectures without direct access to the latest technologies. This approach worked well until the industry reached the 20-nanometer node. At that point, the complexity of semiconductor design increased, with the introduction of advanced device architectures like FinFETs, nanosheets, Forksheets, CFETs, and novel integration solutions such as 3D stacking and chiplet integration.Transistor scaling in the AI eraTraditional abstraction models could no longer keep up with these advances, and the gap between academic research and industrial practice began to widen. This growing gap started to limit academia’s ability to participate in semiconductor paradigm shifts, such as CMOS 2.0 and new computing architectures. P-PDKs, enabled by the NanoIC pilot line, aim to bridge this gap, restoring the connection between academic thinking and industrial progress.SEMI: How does this support semiconductor innovation in Europe?Tahoori: Universities are ideally positioned to drive out-of-the-box innovation and invent new paradigms for computing. This is where universities truly excel. But to do that, they need access to the latest technologies and tools. We see for example a strong focus on the AI revolution and how the microelectronics industry is enabling that transformation. To meet the demands of AI applications and the computing power they require, we need to design new computing architectures based on advanced technology nodes. This is precisely the academic area of expertise. To design these new AI computing architectures, however, we need the most advanced technologies available. The P-PDKs for advanced nodes provided by the NanoIC pilot line now make this kind of research possible at universities. Something that was not feasible before.Additionally, the P-PDKs also provide an important reference technology and platform to benchmark and validate these innovations within a next-generation design roadmap. This means researchers can test their novel architectures against realistic process and performance metrics.SEMI: Are they only available for academia?Farokhnejad: The NanoIC P-PDKs are meant to be accessible to foster innovation across Europe’s semiconductor ecosystem. These advanced PDKs are therefore also available to European research organizations, startups, and industry partners. Access is facilitated through Europractice, where eligible users can apply by signing a Design Kit License Agreement (DKLA). Once approved, they gain access to the PDKs.SEMI: What other technology nodes are NanoIC’s PDKs addressing?Farokhnejad: The first P-PDK was released in June (first version of the N2) and supports frontside and backside routing with TSVM, standard cell libraries, and multiple VT flavors for early-stage design exploration. Upcoming releases include new versions of the N2 P-PDK, as well as A14 and A7 PDKs, eDRAM and SOT memory PDKs, and advanced interconnect solutions such as redistribution layers (RDL), hybrid bonding, and interposers.Those interested in learning more about the NanoIC ecosystem and the research enabled by the P-PDKs can meet representatives and partners of the NanoIC pilot line during SEMICON Europa, November 18-21 at booth C2417 in Messe Munchen. More information about the initiative is also available on the NanoIC website.BiosMehdi Tahoori, Professor Chair of Dependable Nano-Computing - Karlsruhe Institute of Technology Mehdi B. Tahoori is Professor and Chair of Dependable Nano-Computing at the Karlsruhe Institute of Technology (KIT), Germany, and guest professor at imec, focusing on CMOS 2.0 and future chip technologies. He previously worked at Xilinx (USA), Fujitsu Labs (USA), and served as a junior professor at Boston Northeastern University (USA) and as a visiting professor at the University of Tokyo (Japan). He earned his B.S. from Sharif University (Iran) and M.S./Ph.D. from Stanford (USA). Prof. Tahoori is Deputy Editor-in-Chief of IEEE Design and Test Magazine, is a former Editor-in-Chief of Elsevier Microelectronic Reliability and has chaired major IEEE symposia. His honors include multiple best paper nominations and conference awards, the US National Science Foundation Early Faculty Development (CAREER) Award (2008), an ERC Advanced Grant (2022), and an IEEE fellowship.Anita Farokhnejad, DTCO Program Manager - imec Anita Farokhnejad earned her PhD from Universitat Rovira i Virgili (Spain), specializing in FEOL and device modelling. She joined imec in 2021 as an R D Engineer, focusing on BEOL optimization and future roadmap development. Collaborating closely with integration and physical design teams, she develops models for PnR data analysis and BEOL optimization. Her recent work on the enhanced Ring Oscillator (eRO) model aids in the early assessment of new materials and BEOL boosters. In August 2023, she advanced to team lead for PDK Enablement, translating advanced semiconductor nodes into Pathfinding-PDKs. Farokhnejad is also dedicated to education, conducting courses that make sophisticated technological concepts accessible to both industry veterans and aspiring engineers. Currently, she serves as Program Manager of DTCO at imec, where her contributions continue to drive innovation in the semiconductor industry.AcknowledgementThis work was enabled by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union’s Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. For more information, visit https://www.nanoic-project.eu.DisclaimerFunded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or Chips Joint Undertaking. Neither the European Union nor the granting authority can be held responsible for them. SEMI ContactJames Lam, Business Development ManagerEmail: [email protected]

In the rapidly-evolving semiconductor industry, maintaining a competitive edge is crucial. To position Europe at the forefront of global semiconductor innovation, imec is leading the NanoIC pilot line initiative. Aligned with the European Chips Act, this initiative is a strategic move to bolster Europe's leadership in key markets like high performance computing, automotive, and healthcare.SEMI spoke with Srikanth Samavedam and Jo De Boeck from imec, Belgium, to learn more about the NanoIC pilot line and to better understand its goals, challenges, and prospects. From transitioning to gate-all-around (GAA) nanosheet devices, to developing advanced memory technologies and interconnects, this conversation highlights the cutting-edge advancements made possible through collaboration across the industry’s value chain.SEMI: How is the NanoIC pilot line working to revolutionize the semiconductor industry, and what are its main objectives?Samavedam: The NanoIC pilot line is a European initiative aimed at bridging the gap between R D and industrial innovation. The project is creating a beyond-2nm system-on-chip (SoC) pilot line, developing advanced logic, memory, and interconnect technologies. This effort supports the European Chips Act's vision for leadership and competitiveness in global semiconductor innovation, particularly in critical markets like high performance computing, communication, automotive, energy, and healthcare. However, advanced technologies come with more complexity, and addressing these complexity challenges requires more mature module baseline flows. By improving baseline flow repeatability and variability while reducing defectivity, we can accelerate the development of future technologies. The NanoIC pilot line is working to provide access to these advanced technologies and baselines to develop future compute systems. This will help ensure European competitiveness across the industry – from semiconductor materials, equipment and design to systems and applications.SEMI: Who are the core partners involved in this initiative?De Boeck: Key partners of the pilot line include CEA-Leti, Fraunhofer-Gesellschaft, VTT Technical Research Centre of Finland, Tyndall National Institute, and the Center for Surface Science and Nanotechnology of the University POLITEHNICA of Bucharest. This project is also supported by the Flemish government, other participating states, and the Chips Joint Undertaking of the EU Chips Act.These institutions and organizations bring a wealth of knowledge and resources, and imec compliments their efforts by providing access to its global partnerships with key industry leaders. The NanoIC pilot line is helping strengthen Europe’s global semiconductor industry leadership while aligning efforts with other regional Chips Acts. SEMI: Can you elaborate on the significance of transitioning from field-effect transistors (FinFETs) transistors to GAA nanosheet devices in CMOS technology?Samavedam: The transition from FinFETs to GAA nanosheet devices is a significant advancement in CMOS device technology. FinFETs have been the backbone of CMOS technology from the 22nm to the 3nm node. But starting at the 2nm node, nanosheet devices will need to be introduced. Nanosheet devices, including variants like Forksheet devices, are expected to drive scaling and performance through three generations – 2nm, A14, and A10. Complementary FET (CFET) architectures are also expected to be introduced around 2031 at the A7 node, which will represent another major inflection point in CMOS device design. This progression requires extensive research into new materials, process modules, equipment, and advanced patterning capabilities using high numerical aperture extreme ultraviolet (high NA EUV) lithography – all of which will be implemented on the NanoIC pilot line. FIGURE PROVIDED BY IMEC │ SCHEMATIC ILLUSTRATION OF A FUTURE COMPUTE SYSTEM. THE SYSTEM IS MADE OF LARGE MULTI-DIE ELECTRICAL-OPTICAL INTERPOSER PROVIDING ELECTRICAL AND OPTICAL INTERCONNECTS BETWEEN THE VARIOUS CHIPLETS (CPUS, GPUS, HBM). ALSO SHOWN ARE CONNECTIONS TO PACKAGE SUBSTRATE, AS WELL AS FIBER CONNECTORS AND AN INTEGRATED LASER SOURCE. CENTRAL PROCESSING UNIT (CPU); GRAPHICS PROCESSING UNIT (GPU); HIGH BANDWITH MEMORY (HBM); PROCESSING UNIT THAT CAN INCLUDE CPUS, GPUS, AND OTHER SPECIALIZED PROCESSORS (XPU); APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC); ELECTRONIC INTEGRATED CIRCUIT (EIC); FF-LEVEL: FEMTOFARAD-LEVEL; FIELD-PROGRAMMABLE GATE ARRAY (FGPA); GAAS QD: GALLIUM ARSENIDE QUANTUM DOT; INTEGRATED SILICON PHOTONICS PLATFORM 300MM (ISIPP300); REDISTRIBUTION LAYER (RDL); SILICON PHOTONICS (SIPHO); THROUGH PACKAGE VIA (TPV). SEMI: What are the key innovations necessary for advancing memory technology?Samavedam: As SRAM scaling slows, the exploration of novel, dense embedded memory concepts will become imperative. Technologies like spin orbit torque magnetic RAM (SOT-MRAM) and 2-transistor 0-capacitor (2T0C) embedded DRAM using deposited semiconductors like indium gallium zinc oxide (IGZO) are promising. These innovations address memory capacity and bandwidth challenges from new workloads in compute systems. Additionally, developing a 3D memory platform to explore future memory options will be essential for improving SRAM and DRAM. These advancements will help meet the demands of new applications like machine learning, augmented and virtual reality, and autonomous vehicles.SEMI: How do advanced interconnect technologies contribute to the future of semiconductor design?Samavedam: Advanced interconnect technologies, like chip-to-chip lateral (2.5D or interposer technologies) and vertical interconnects (3D technologies), play a crucial role in addressing memory capacity and bandwidth challenges. These technologies enable the partitioning of SoC functions into separate dies, allowing for more efficient and scalable designs. Advances like pitch scaling of micro-bumps and copper (Cu) hybrid bonding are facilitating this fine-grained partitioning of SoC functions. Additionally, optical interconnects and 3D interconnect-enabled co-packaging provide high-bandwidth and low-power connectivity at wafer scale. The rise of chiplet architectures and standardization will also increase the demand for low-cost, tight-pitch interconnect technologies like Cu/polymer redistribution layers.SEMI: How do your collaborators benefit from the NanoIC pilot line? De Boeck: One of the biggest collaborator benefits is the pilot line’s commitment to knowledge sharing through R D access and training. We invite foundries, IDMs, materials suppliers, equipment suppliers, and system companies/OEMs to jointly develop the materials, process modules, and integration flows to accelerate the development of beyond-2nm SoC technology pillars.Design pathfinding and system exploration process design kits (PDKs) will be available for start-ups, small- and medium enterprises, universities, and design and system companies to aid in prototyping and testing their designs. The NanoIC pilot line will also offer comprehensive training programs, including virtual PDK training, bootcamps for faculty, and internships and expert courses for students. To learn more, experts and key partners of the NanoIC pilot line will be presenting from 14 -16:40 at SEMICON Europa on November 12. imec’s program, ITF Chip into the Future, will highlight advancements in digital technology, capacity building through the European Chips Act, and the role of the NanoIC pilot line in accelerating beyond-2nm innovation. The conversation will also address industry requirements for pilot lines, emerging initiatives boosting Europe’s innovation and competitiveness, and perspectives on advanced materials and semiconductor equipment. Srikanth Samavedam, Senior Vice President of Semiconductor Technologies at imec, oversees programs in logic, memory, photonics, and 3D integration. Previously, he was a senior director at GlobalFoundries, leading 14nm FinFET technology into production and developing 7nm CMOS. Starting his career at Motorola, he worked on strained silicon and other advanced materials. He holds a Ph.D. in materials science and engineering from MIT and a master's degree from Purdue University. Jo De Boeck, Executive Vice President and Chief Strategy Officer at imec, oversees the company’s strategic direction and serves on its executive board. He joined imec in 1991 after earning his Ph.D. from KU Leuven and has since held various leadership roles, including head of imec’s Smart Systems and Energy Technology business unit and CTO. De Boeck is also a part-time professor at KU Leuven. Maria Daniela Perez / Communications Manager, SEMI EuropePhone: +49 160 2562977Email: [email protected]

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