Day 1
Laith Altimime, President of SEMI Europe
Biography
As President of SEMI Europe, Laith Altimime leads SEMI’s activities in Europe and Middle East and Africa (EMEA). Altimime has P&L responsibility as well as ownership of all Europe region programs and events, including SEMICON Europa. He is responsible for establishing industry Standards, advocacy, community development, expositions, and programs. He provides support and services to SEMI members worldwide that have supply chain interests in Europe. He manages and nurtures relationships with SEMI members in the region and globally as well as with local association and constituents in industry, government, and academia.
Altimime has more than more than 30 years of international experience in the semiconductor industry. Prior to joining SEMI in 2015, He held senior leadership positions at NEC, KLA-Tencor, Infineon, Qimonda and imec.
Altimime holds an MSc from Heriot-Watt University, Scotland.
Dario Alliata, Director of Business Unit, Unity-SC
Abstract
Keeping the product manufacturing profitable with the increasing demand of device performances is nowadays a challenge. With the explosion of cost and complexity at the most advanced front-end silicon technology nodes, alternatives ways must be explored.
Advanced Packaging has become a key differentiator for achieving next-generation requirements, and thereby continued sustainability [1], in the semiconductor industry. Since early 2000, when the Embedded Wafer Level Balling (EWLB) approach was introduced, several flavors of advanced packaging based on fan-out (INFO, EMIB, SWIFT), 2.5D and even 3D has been adopted.
Despite the maturity of the advance packaging industry, we are still in an era where several issues can put at risk the process chain. Therefore, the need of process control solutions with systems as much as possible capable of covering inspection and metrology needs at 360 degree on the very same platform. Key process steps like molding and passivation in WLFO, TSV etch in 3D stacking, bonding in Chip to Substrate and/or Chip to Chip stacking are still requiring major control. RDL entering the sub-micron territory also represents a challenge in term of metrology & inspection.
In this paper, we are presenting our progress in developing solutions for the Advanced packaging arena by combining inspection and metrology strategies to identify the root cause of the yield loss. Multiple inspection techniques are used to identify and classify visible and invisible defects at each surface of the wafer. Complementary metrology techniques are used to secure the process development and high-volume manufacturing. Customizing the solution is the new way to secure the manufacturing.
Biography
Dario Alliata received his MDs in Physics from the University of Milan (Italy) and PhD in Physical Chemistry from the University of Berne (Switzerland).
He covered several positions in Public Research centres as Surface Science Scientist and moved to Semiconductor Industry in early 2000 as Applications Scientist for Inspection & Metrology. He joined Unity Semiconductor SAS as Product Manager in 2016 and is now Director of Applications.
Alexandre Balmefrezol, Head of Product R&D Imaging Division, STMicroelectronics
Abstract
Alexandre Balmefrezol will speak about ST optical solutions market focus & perspectives.
Biography
Alexandre Balmefrezol is Senior R&D director of System & Silicon design of the Imaging sub-group within ST’s Analog, MEMS and Sensors Group and has held this position since 2015.
Alexandre Balmefrezol joined STMicroelectronics as designers in 1997 . He held various positions in product design management focusing on Analog baseband , Power management IC for Mobile phone. Later on, in 2009 , Alexandre Balmefrezol was transferred into ST-Ericsson (an ST & Ericsson joint venture in charge to design & commercialize 4G Mobile Chipset ). He was managing Analog & Mixed signal R&D there and was also promoted company Fellow for the last years .
At the end of ST-ericsson in 2013, Alexandre Balmefrezol was transferred back to ST , inside the imaging division with the mission to lead the Analog & Mixed signal R&D. 2 years after, in 2015 Alexandre was appointed Senior R&D director for the System & Silicon product design of the imaging sub group.
Alexandre Balmefrezol was born in Millau, in 1974 He graduated with a degree in Electronic Engineering from ISIM in Montpellier & earned a business master diploma from the Grenoble Ecole the management.
Dr. Anthony Barker, Senior PVD Product Manager, SPTS Technologies Ltd
Abstract
It is well-established that the addition of scandium increases the piezoelectric performance of an AlN-based piezoMEMS device, but this enhancement does not come without some processing challenges.
AlN and AlScN can be deposited using PVD, however film stress state is of utmost importance and to maximize yield, manufacturers look to minimize stress variation across the wafer. When scandium (Sc) is added, the stress range of the PVD film tends to worsen with increased Sc content, and crystallite defects become more likely which would reduce the piezoelectric efficiency. It has also been found that etching Sc-doped AlN also becomes more challenging as Sc content increases. In fact, standard inductively coupled plasma (ICP) technology is unable to etch AlScN with doping levels >10at.% Sc, so an alternative process is necessary.
This presentation will explain the latest plasma etch and deposition capabilities for processing AlN films that have been doped with high levels of scandium (≥30at.%Sc) to realize the potential performance benefits for piezoMEMS and BAW filter manufacturers.
Biography
Anthony Barker joined Surface Technology Systems (STS) in 1997 as Etch Process Engineer. He went to manager STS’ non-Si based Etch and deposition process groups. After leaving STS he joined Trikon as Etch Process Engineer in 2005, which became Aviza Technology and then merged with STS in 2009 to form SPTS Technologies. Most recently, Anthony worked as Principal Process Engineer in R &D Accounts group before joining SPTS’s PVD Product Management team in May 2017.
Before STS, Anthony worked as Thin Film Process Engineer at Gems Sensors. Dr. Barker has a B. Eng Honours degree in Materials Engineering and a Ph.D in Electronic Materials in association with Rolls Royce, both from Swansea University
Eric Beyne, Senior Fellow, VP R&D, Director 3D System Integration Program, imec
Biography
Eric Beyne was born on May 26, 1960, in Tienen, Belgium. He received the Electrical Engineering degree and Ph.D. degree in applied sciences from the Catholic University of Leuven, Leuven, Belgium, in 1983 and 1990, respectively. From 1983 to 1985, he was a Research Assistant at the Catholic University of Leuven. In 1986, he joined the Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium, where he was involved with research on the interconnection of high-frequency digital circuits. He is currently the Head of the High Density Interconnection and Packaging Group, IMEC. Dr. Beyne is the secretary of the International Microelectronics and Packaging Society (IMAPS) Benelux Committee.
Ruurd Boomsma, CTO, Besi
Abstract
Due to increased complexity and cost in advanced front-end technology, as well as new ideas about integration we see a shift towards increasing importance in back end technologies. This will require new technologies how to stack and bond different device classes in a productive way. In order to fully utilize next generation front-end technology, there will also be strong requirements to data transfer speeds and higher contact densities when connecting these devices.
Current and future demands for the connecting technology like TCB and Hybrid Bonding will be discussed. A short update of latest status of developments on advanced die bonding technologies will also be given.
Biography
Ruurd Boomsma studied Semiconductor Physics and started working in the semiconductor industry in 1984. He held leading positions at major equipment manufacturing companies including ASM, MRC and Unaxis/Oerlikon. In 2010 he started at Besi. After being responsible for the Plating Group and the Die Attach Product Group, he now holds the CTO responsibility at Besi, which includes responsibility for the key Technology Directions, Strategic Supply Chain and overall Quality.
Jürgen Burggraf, Process Technology Manager Bonding, EV Group
Abstract
The introduction of 2.5D and 3D integrated devices into the market has sparked new developments overall different applications towards increase performance. Especially high performance computing, image sensing and memory technologies are driving the hybrid bonding development and integration today.
Over the last decade fusion and hybrid bonding on wafer level has developed and is now readily available as unit process in most foundry and device manufacturers worldwide. In the current industry transformation away from optimization on planar devices towards system integration and towards 3D stacked devices, bonding technologies are playing a crucial role. While most devices such as image sensors or stacked memory have been designed specifically for 3D integration and bonding, the next technology transformation as a universal high density interconnect technology will also trigger a new integration process. Therefore, wafer-level as well as die-level hybrid bonding technologies are being developed and depending on interconnect density, chip size, system yield and cost, the best fit in terms of integration flow will be selected.
In this presentation we will provide an overview on the current industry trends and technological developments both for wafer-to-wafer as well as die-to-wafer hybrid bonding. Key technology differentiators, integration scenarios are discussed with respect to the hybrid bonding schemes.
Biography
Jürgen Burggraf started at EV Group (EVG) 2007 as Process Technology Engineer for wafer bonding applications. Currently Jürgen is the Process Technology Manager for wafer bonding and he is responsible for EVG’s worldwide process development for wafer bonding such as temporary wafer bonding/debonding and permanent bonding. He holds an engineering degree in Bionic & Sensor Technology and a diploma degree in industrial engineering.
Jacques Cochard, Business Development, TEMATYS
Abstract
We will present the results of a study realized by TEMATYS in cooperation with Photonics21. The global market for Photonics has grown very fast in the last years and accounted for $733 billion in 2019. Our study shows that the European photonics industry also had a sharp increase (from 76 B€ in 2015 to 103 B€ in 2019) at more than double the rate of global GDP and outperforming EU GDP and EU industrial production growth by three and five times, respectively.
We will also present an analysis of EU and global Photonics industry by component and by application segment. In fact, present in various high-end, next-generation products, Photonics technologies have proved to be long-term drivers of growth through their indispensable role in many current and future markets.
Biography
After a degree received from the Ecole des Mines of Nancy (France), he started his career as a consultant for the European Commission.
In 2000, he joined OPTICSVALLEY, the photonics cluster of Paris as Project Manager. In 2004, he became Senior consultant at TYKYA before being one of the founder of TEMATYS.
Jacques has run more than 70 marketing and technological studies for photonics companies (Cilas, Genoptics / JobinYvon Horiba…), photonics clusters and R&D laboratories (CEA, CNRS, Paris VI Pierre & Maris Curie, GeorgiaTech, Institute of telecom Paris…). Jacques has published more than 20 articles in business press dedicated to laser and photonics (laser focus world, Biophotonics, Optik & Photonik…).
Darragh Corrigan, Senior Staff Product Definition Engineer – MEMS Microphones, Infineon Technologies AG
Abstract
Continuous MEMS technology innovation has been a key enabler of new audio features in true wireless stereo (TWS) earbuds. This presentation will showcase current and emerging differentiators in the TWS market and will explain how MEMS microphones have become the most suitable technology.
Biography
Darragh started his career eleven years ago at Analog Devices in his native Ireland, focusing on capacitive touch and presence detection applications.
He has been working in the field of consumer sensor applications ever since, using his technical and interpersonal skills to anticipate market developments and define the new technologies needed to capitalise on these opportunities.
In 2016 he relocated to Munich to join Infineon Technologies AG, helping to drive advancement in MEMS microphone to enable ever more complex smartphone applications, and the emerging TWS ANC market.
In his spare time he is an avid photographer and enjoys both listening to and playing music.
Dimitrios Damianos, Custom Project Business Development / Technology & Market Analyst, Yole Développement
Biography
Dimitrios Damianos, PhD joined Yole Développement (Yole) as a Technology and Market Analyst and is working within the Photonics, Sensing & Display division. Dimitrios is daily working with his team to deliver valuable technology & market reports regarding the imaging industry including photonics & sensors.
After his research on theoretical and experimental quantum optics and laser light generation, Dimitrios pursued a PhD in optical and electrical characterization of dielectric materials on silicon with applications in photovoltaics and image sensors, as well as SOI for microelectronics at Grenoble’s university (France). In addition, Dimitrios holds a MSc degree in Photonics from the University of Patras (Greece). He has also authored and co-authored several scientific papers in international peer-reviewed journals.
Alain Delpy, Business Development Manager for MEMS, Imager and photonics, Soitec
Abstract
Engineered substrates are booming in many applications such as RF, FD or new substrates like POI or SiC. Nevertheless, people could be unaware of many other applications . enabled by engineered substrates using SmartCut(™) and Smart stacking(™) technologies.
For future image sensor and MEMS applications, this presentation explores how these technologies are precursors of emerging usages with photons or electrons. The speech demonstrates also solutions for your design integrating other material than silicon beyond the well known SOI substrate
Biography
Alain Delpy’s microelectronics experience ranges from design through marketing in the areas of industrial and consumer applications.
He joined Soitec in 2018 as Business Development Manager for Imagers, Silicon Photonics and MEMS. His focus has been bridging Soitec’s substrate engineering with the market needs to partnering and creating innovative applications
Prior to Soitec, in 2013 Alain worked with a startup specialized in x-ray spectrometry for non destructive testing for IC devices.
In 1997, Alain joined STMicroelectronics where he focused on communications devices and applications. Later on he moved to the imaging area for camera applications.
Barbara De Salvo, Silicon Technology Strategist, Facebook
Abstract
The human relationship with computers and information has evolved in the past decades through continuous evolutions and revolutions. Imagine socially acceptable and all-day wearable, private and secure AR glasses which will give us perceptual superpowers and a context-aware personal assistant, and above all the ability to connect, share, and collaborate with others anywhere, anytime. AR/VR glasses will be the next wave of human-oriented computer platforms. These devices will require new human-machine input modalities that are intuitive, non-interruptive, and socially friendly and responsive, all in a stringent form factor.
In this presentation, we will explain the important role of image sensing in AR/VR. Then, we will present a custom global shutter, digital pixel sensor that leverages state-of-the-art stacked CMOS image sensor technology to meet the ultra-low power, ultra-wide dynamic range requirements of AR/VR applications. Finally, we will introduce our vision for the future AR/VR image sensor system to enable a full user experience, i.e. a distributed sensing and compute architecture.
Biography
Barbara De Salvo is currently serving as Silicon Technology Strategist in Facebook Reality Labs (US). Before 2019, she was Chief Scientist and Deputy Director of Leti (France). She was visiting scholar at IBM-Albany in 2013-2015 in the frame of the sub-10nm CMOS Technology Alliance. Before, she founded and led the advanced memory technology division at Leti. She authored more than 350 referred articles, eleven book chapters, a monography on Silicon NVMs edited by Wiley and Sons. She is currently serving as Technical Chair of IEDM 2021 and Chair of the IEEE Corporation Award Committee. She is a Fellow of the IEEE.
Bernd Dielacher, Business Development Manager, EV Group
Abstract
Sensors are a key technology for many of today´s applications and must meet the highest standards of performance and reliability. Today, they exhibit a high degree of complexity and integration, thus innovative manufacturing technologies are necessary to fulfil the requirements of next-generation applications. 3D sensing, either in consumer devices or in automotive LiDAR is a good example where many different technologies are merging such as MEMS structuring, hermetic sealing or vacuum encapsulation but also the integration of piezo and optical materials and even lens structures. This presentation will discuss the requirements and capabilities of wafer-bonding and lithography technologies for advanced 3D sensing applications.
Biography
Dr. Bernd Dielacher is business development manager at EV Group where he is responsible for the MEMS as well as the bio- and medical technology market.Bernd holds a master’s degree in Microelectronics from Vienna University of Technology and received a PhD in Biomedical Engineering from ETH Zurich, where he explored metal nanostructures for electrical and plasmonic sensing in biomedical applications.
Mark Gerber, Senior Director, Engineering & Technical Marketing, ASE Group
Abstract
Semiconductor technologies are fueling the digital transformation that is solving some of the world’s greatest challenges. Our connected lives generate vast amounts of data, driving unprecedented demand for bleeding edge digital networks, connectivity, storage, memory, edge to cloud compute, and so much more. Never has the need for semiconductor innovation been greater, and our industry is stepping up.
Heterogeneous Integration refers to the integration of separately manufactured components into a higher-level assembly (System-in-Package, known as SiP) that in the aggregate provides enhanced functionality and improved operational characteristics. It is now the key technology direction going forward, driving the pace of advancement for greater intelligence and connectivity, higher bandwidth and performance, and lower latency and power per function, all at a more manageable cost.
Mark Gerber will introduce the scope, reach and power of heterogeneous integration, describing how broad ecosystem collaboration is initiating a new era of technology and scientific advances that will continue and complement Moore’s Law scaling into the future. Gerber will expand by exploring some of the packaging innovations poised to achieve unprecedented impact on the way we live, work, play and communicate, paying special attention to MEMS and Sensor technologies.
Biography
Mark Gerber heads engineering and technical marketing for MEMS & Sensors, as well as System-in-Package technologies, in his capacity as Senior Director at ASE (U.S. Inc.). With over twenty-five years’ experience in the semiconductor industry, Mark previously held management and engineering roles at Texas Instruments, Motorola and Maxim Integrated in various areas of design, manufacturing, and assembly with an emphasis on the development of new technologies and processes. Mark serves on multiple committees for IEEE and IMAPS, and is an IMAPS Fellow. He holds a bachelor’s degree in mechanical engineering from Texas A&M University, has written over 20 papers and publications, and holds 36 semiconductor packaging related patents.
Atte Haapalinna, CTO, Okmetic
Abstract
Okmetic is the leading supplier of advanced silicon wafers for MEMS Sensors as well as RF and Power
applications. MEMS and Sensor applications benefit from Okmetic’s decades-long crystal growth and SOI
wafer expertise. Additional advantage for advanced MEMS manufacturing is provided by the company’s
unique in-house patterning line for embedded C-SOI® structures, enabling improved device performance and
reliability with shortened cycle time. Okmetic has complete set of 150-200mm SSP, DSP, SOI and High
Resistivity wafers for even the most demanding application needs.
Biography
Dr. Atte Haapalinna − CTO of Okmetic
Born 1969, D.Sc. (Tech)
Okmetic
- Senior Vice President, Products 2014-2017
- Business Development Manager, new business development 2011-2013
- Application Manager 2008-2011
- Senior Application Engineer, Customer Support Engineer, Development Engineer 1998-2008
Fraunhofer Institut für Prodktionstechnologie (IPT)
- Visiting Scientist 2001
- Helsinki University of Technology
- Scientist 1995-1998
Jani Karttunen, Product Manager for Patterned Products, Okmetic
Abstract
There is an ongoing shift towards more advanced and complex MEMS devices and more streamlined MEMS manufacturing. The choice of substrate has a significant effect on the performance, TCO and time-to-market of MEMS devices, which is why the demand for tailored, process-optimized substrates is surging. Okmetic has large family of Bonded SOI (Silicon-On-Insulator) wafers that can be customized for different MEMS device and process needs. These kinds of advanced silicon wafers enable more optimized MEMS processes as they reduce the production process complexity and total cost of ownership significantly compared to bulk silicon wafers.
Biography
Mr. Jani Karttunen is Product Manager of the Patterned Wafer Products at Okmetic, the leading supplier of advanced silicon wafers. He has been with Okmetic since 2007, in various positions including sales, new business development and customer support. He has 20 years of hands-on experience in process development and process integration of state-of-the-art MEMS devices. His career to date includes engineering positions at VTI Technologies Oy (now Murata Finland), the State Research Centre of Finland (VTT) and petrol company Neste Oyj. Mr. Karttunen received his Master’s degree in Materials Science at the Helsinki University of Technology (now Aalto University) Finland.
Chris Jones, Senior Director, PVD Product Management, SPTS Technologies Ltd.
Biography
Chris Jones is Senior Director of PVD Product Management at SPTS, responsible for the SPTS PVD product line, covering all aspects of marketing including product positioning and the provision of support to the worldwide sales team.
After completing his BEng in Mechanical Engineering in 1995 at the University of Bristol, UK, he joined SPTS working in Customer Support and then Process Engineering before moving into Product Management in 2004. Chris has presented widely on SPTS products and is an author of several technical articles.
Haechang Lee, Senior VP Automotive Sensor, Samsung
Abstract
Image sensors have advanced tremendously over the last 10 years fueled by the growth of the smartphone market. Over the next 10 years, we observe two major trends: a continued effort to emulate human vision and another to augment humans with the primary objective of safety. The talk will outline key requirements in each trend and the technologies being pursued to realize them.
Biography
- Standford University, BS, MS, PhD Electrical Engineering
- Rabus Inc, Principal Engineer
- Arda Technologies, Manager of System Architecture
- SiTime, Director of Circuit Design, Characterization/Packaging
- Altera, Director, Analog and Serial IO Technology
- Google, Sensor Team Lead, Technology Engineering, D&S PA
- Samsung Electronics, Automotive Sensor Team Lead
Eric Mazaleyrat, Technology Scouting and Innovation Director, STMicroelectronics
Biography
Eric Mazaleyrat is a Technology Scouting and Innovation Director with STMicroelectronics. He has more than 20 years of experience in semiconductors in different technical and management job position. He specializes in R & D project management and manufacturing.
Dragomir Milojevic, Senior Scientist, imec
Abstract
Current hybrid wafer-to-wafer bonding allows stacking with 3D structure pitches below 1um, allowing heterogeneous system integration, where each wafer FEOL, BEOL can be optimized for a given functionality to trade-off system performance, power and cost. Typical functional system partitioning aims the split of memory from the logic. While 3D structures with coarser pitches (micro-bumps) are already used to split main or higher cache memories (HBMs, Foveros, AMD V-Cache), finer 3D structures (Cu pads) can be used to split lower and intermediate cache memory layers (L2,L1) from the core logic. System performance gets better since delay & latency are reduced, but also the system cost, since only the core layer is built using expensive technology. In this presentation we will describe 3D system design enablement flow based on industry qualified EDA tools, together with design methodology for Memory-on-Logic applications. Then practical implementations will be discussed to quantify benefits of 3D technology using advanced CMOS processes (sub-10nm).
Biography
Dragomir Milojevic received his master’s and PhD degrees in Electrical Engineering from Ecole polytechnique, Université libre de Bruxelles (ULB), Belgium, where he holds the position of professor in digital electronics and digital systems design. In 2004 he joined IMEC where he first worked on multi-processor and Network-on-Chip architectures for low-power multimedia systems. Since 2008 he is working on system, design and technology co-optimization with advanced nodes, as well as design methodologies & tools for technology aware design of 3D integrated circuits. Dragomir Milojevic authored or co-authored more than 100 journal and conference articles and served as technical program committee member to several conferences in the field.
Dr. Christian Ohde, Global Product Director – SC/FEC, Atotech
Abstract
We present next generation chemistry and equipment solutions for upcoming requirements of the electronics and semiconductor industry along specific examples such as RDL, pillars, PLP.
Biography
Today, Christian Ohde is leading Atotech’s global Semiconductor and Functional Electronics Coatings activities. He is a reputable industry expert and a thought-leader in his areas of responsibilities.
Christian finished his PhD in chemistry and joined Atotech Group in the year 2010. Holding various management positions, he was appointed as Head of R&D for the companies Electrolytic Copper plating activities, mainly focusing on plating of various metals in different equipment tool sets (horizontal and vertical) in 2013.
In October 2020, Christian was appointed as the Global Product Director for Semiconductor and Lead Frame and Connectors.
Ulrich Peuchert, Global Senior Product Manager SCHOTT
Biography
Ulrich Peuchert got his Diploma degree on Mineralogy and Material Science from University of Munich, Germany. Ulrich received his Phd from University of Cologne on Structural and Physical Investigations of Single-Crystalline matters.
Since 1998 Ulrich Peuchert has worked at SCHOTT AG in various functions. Starting within Corporate R&D, Ulrich headed various material, product, technology as well as business related development projects and programs. Ulrich’s main focus has been on customer-driven identification and definition of new product opportunities and early-stage promotion to various industries such as energy storage, optics, display and medical. Currently Ulrich is working as Global Senior Product Manager and Business Developer within Strategic Business Field Specialty Flat Glass and Wafer with focus on FLEXINITY® Structured Glass for Semicon & Sensor industries.
Matthias Schicke, Global Senior Key Account Manager, FUJIFILM
Biography
Matthias Schicke received his PhD in Physics in 1998 from the University of Hamburg, Germany, for his work on superconducting photon detectors at IRAM (Institute for RadioAstronomy in the Millimetre range) in Grenoble, France. After 8 more years as senior staff and finally head of R&D and Device Production at IRAM, Matthias joined Fujifilm Electronic Materials (FFEM) in 2007. Today Matthias is Senior Global Key Account Manager and European Advisor for FFEM’s WCM (Wave Control Materials).
Thomas Uhrmann, Business Development Director, EV Group
Abstract
Even though heterogeneous integration is not new to the industry, the packaging aspect has not been the focus on any of the PPAC metric. In recent years the system performance is getting more important, where heterogeneous integration and system-technology co-optimization (STCO) are the key building blocks for future devices, especially in high performance, AI and mobile applications. The presentation will give a short outlook into the session, including key building blocks of technology.
Biography
Dr. Thomas Uhrmann is director of business development at EV Group (EVG) where he is responsible for overseeing all aspects of EVG’s worldwide business development. Specifically, he is focused on 3D integration, MEMS, LEDs and a number of emerging markets. Prior to this role, Uhrmann was business development manager for 3D and Advanced Packaging as well as Compound Semiconductors and Si-based Power Devices at EV Group. He holds an engineering degree in mechatronics from the University of Applied Sciences in Regensburg and a PhD in semiconductor physics from Vienna University of Technology.
Jean-Luc Jaffard, Consultant and Advisor, RedBelt SA
Biography
Jean-Luc Jaffard has been graduated from Ecole Supérieure d’Electricité of Paris in 1979.
He started his career 1980 joining Thomson- Semiconductor Bipolar Integrated Circuits Division as Analogue and Mixed Designer for Consumer applications.
In 1987 after the creation of SGS Thomson Microelectronics (merger of Thomson Semiconductor and SGS Microelectronica) he became Video Division - TV Design Manager coordinating the development of Analog TV and VCR product family.
From 1996 Jean-Luc Jaffard paved the way of imaging activity at STMicroelectronics being at the forefront of the emergence and growth of this business
At STMicroelectronics Imaging Division he was successively appointed Research Development and Innovation Director managing a large multidisciplinary and multicultural team and later on promoted Deputy General Manager and Advanced Technology Director in charge of identifying and developing breakthrough Imaging Technologies and to transform them into innovative and profitable products
In 2010 he was appointed STMicroelectronics Intellectual Property Business Unit Director
In January 2014 he created the Technology and Innovation branch of Red Belt Conseil , bringing expertise in optimisation of complex and innovative solutions to develop competitive products.
Since 2014 he has been appointed SEMICON Europa Imaging Conference chairman.
In 2016 he joined Prophesee as VP Hardware in charge of developing Event Based Image sensor technology.
Hanna Kahari, Technical Leader Materials, Nokia
Abstract
5G communications solutions require ultra-low loss laminate materials and PCBs/substrates. Manufacturers of these materials have no consistent methodology for measuring complex permittivity at 5G mmWave frequencies, making the comparison of the data difficult. Moreover, the complex permittivity data is typically available only for certain frequencies that often differ from the 5G mmWave frequencies, so the dielectric properties must be extrapolated from the low frequency data. All this can lead to costly errors in designs and makes it difficult to choose the optimum materials. To find solutions for these problems, Nokia participates in INEMI’s (International Electronics Manufacturing Initiative) 5G Materials Assessment and Characterization Project. This presentation summarizes the first results of the project, where current and emerging industry best practices for complex permittivity measurements were benchmarked. The findings of the global Round Robin testing across multiple resonator types and reference materials are also shared.
Biography
D.Sc. Hanna Kähäri received her M.Sc. (Chemistry) in 2006, and M.Sc. (Tech) and D.Sc. (Tech) degrees in Electrical Engineering from the University of Oulu, Finland in 2012 and 2016, respectively. After finishing her Doctoral degree in the field of Materials for Electronics and Telecommunications Devices, she has been working for Nokia in Mobile Networks Business Unit. Currently she is working as a Technical Leader, Materials, in a team focused on Radio System Architecture. She represents Nokia in iNEMI's 5G/mmWave Materials Assessment and Characterization Project.
Pawel Malinowski, Program Manager “Pixel Innovations”, imec
Biography
Pawel E. Malinowski was born in Lodz, Poland, in 1982. He received the M.Sc.Eng. degree in electronics and telecommunications (thesis on design of radiation-tolerant integrated circuits) from the Lodz University of Technology, Poland, in 2006. In 2011, he received the Ph.D. degree in electrical engineering from the KU Leuven, Belgium (thesis on III-nitride-based imagers for space applications).
Pawel is working at imec since 2005, and in the Large Area Electronics Department since 2011 (currently Sensor & Actuator Technologies). He is Program Manager “Pixel Innovations” and he focuses on disruptive optical sensor technologies, including new types of image sensors enabled by thin-film semiconductor integration. Pawel overlooks the innovation actions, works closely with tech teams, sets the technology roadmaps and prepares go-to-market scenarios.
Pawel has coauthored more than 50 publications and submitted 6 patent applications. He was a recipient of the International Display Workshops Best Paper Award in 2014 and the SID Display Week Distinguished Paper Award in 2018. He co-supervised the work leading to the I-Zone Best Prototype Award at SID2019. Pawel is Member of IEEE and SID, and served on the ODI Committee (Optoelectronics, Displays, and Imagers) of the 64th and 65th IEDM conference. He is currently a member of the program committee of SEMI Connected Heterogeneous Systems Summit. Pawel has been an evaluator for EC-MSCA (Marie Skłodowska Curie Actions) since 2019.
Kaladhar Radhakrishnan, Intel Fellow, Intel
Abstract
As monolithic scaling slows down, the semiconductor industry is increasingly relying on advanced packaging technologies to extend Moore’s law through heterogeneous integration. Interest in advanced packaging is driven by the need for increased on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries. While these advanced packaging technologies are extremely effective at solving these problems, they introduce some challenges of their own. Delivering power in an efficient manner to all the different domains in a heterogeneous system is one such challenge. In this talk we will go over some of the solution vectors and the technology ingredients needed to address the power delivery challenge.
Biography
Kaladhar Radhakrishnan is an Intel Fellow and a Power Delivery Architect with the Technology Development group at Intel. He has played a significant role in shaping and driving power delivery technologies for Intel microprocessors. His areas of expertise are in integrated voltage regulators, advanced packaging and passives technologies. Kaladhar is a two-time recipient of the Intel Achievement Award. He has authored four book chapters, over 40 technical papers in peer reviewed journals, and has been awarded 35 US patents. He has also served as an Adjunct professor at Arizona State University. Kaladhar joined Intel in 2000 soon after he received his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign.
Gihun Ryu, Senior Application Engineer, ULVAC
Abstract
Piezoelectric thin films have been integrated with advanced silicon-based microfabrication methods in the formation of both sensors and actuators that are called “MEMs”. Currently, (I) Ultrasound, (ii) Inkjet-printheads and (iii) Micro-mirror applications - based on the MEMs actuators, are driving the market with a forecast for 2026 of approximately $6,600, $3,500, and $800 US$M, respectively. New opportunities mentioned above could be the trigger for rapid growth of the MEMS Actuator market. For last few decades, most of commercialized piezo-actuators have been based on bulk piezoelectric ceramics. However, bulk piezoelectric ceramic faces difficulties due to the limitation of integration with MEMs, thickness demands as well as power consumption requirements.
ULVAC will introduce the newly developed mass production deposition and etching solutions that are applicable to CMOS compatible process with the threshold of < 500oC that address many of the previous bulk material limitation as well as the etching performance of Sc doped AlN that are currently leading this MEMS market area.
Biography
Gihun Ryu received his MSc in Applied Physics from Pusan National University, Busan, South Korea in 2005 and his Dr. Ing. in Material Science and engineering from Tokyo Institute of Technology, Tokyo, Japan in 2012. Before receiving PhD Degree, he worked as a Research Engineer in S&S Tech, South Korea (2005), for the development of advanced Mask Blank and Photo Mask using ULVAC In-line type Sputter and commercial dry/wet etching systems for ArF, EUV, as well as, LCD based Applications. After obtaining his PhD degree in 2012, he worked as post-doc scientist in Max-Plank-Institute for Solid State Research from 2012 to 2016 in Stuttgart and Max-Plank-Institute for Chemical Physics of Solids from 2016 to 2019 in Dresden, Germany where he studied the crystal growth mechanism, design of new functional inorganic compounds, analysis of physics properties for over 1000 new functional inorganic compounds. Dr. Ryu joined ULVAC in 2020 and is currently working as a senior application engineer for piezoelectric MEMS application and related MEMS projects in Europe. In particular, Dr. Ryu is interesting in the advanced deposition process of piezoelectric based thin film such as PZT, Sc doped AlN, lead-free piezoelectric compounds as well as etching process using ULVAC Sputtering and etching tools.
Martin Schrems, Senior Advisor, Boston Consulting Group
Abstract
Smart, autonomous systems are enabled by progress in sensing, computing/AI and wireless connectivity technologies. At the same time there is relentless pressure to get new high performance OEM products such as automated & connected vehicles, computers, cloud servers, smartphones, smartwatches etc. to the market faster and at the same time reducing the cost of electronics. Such stringent product requirements can be achieved by rigorous modularization of systems already emerging in recent product generations. Heterogeneous Integration (“System in Package”, “System in Board”,…) is the core technology enabling such modularization. Some major technology breakthroughs enabling the high level of electronics integration needed include chip stacking with TSV and Cu pillars or direct chip bonding, System-in Package with chiplets, “Fan-Out” architectures, advanced substrates and PCBs with embedded bridges and components or a combination thereof.
Starting from fundamental Heterogeneous Integration technology trends the presentation takes a look at the impact on the electronics supply chain. Changing roles of players from OEM and Tier1 to semiconductor companies and suppliers, PCB/substrate makers and EMS can be observed as a result of higher levels of system integration and modularization enabled by Heterogeneous Integration technology advances. Substrate and PCB markets for high-end consumer products are already converging. OSATs and EMS start to compete for module integration services, and other players such as PCB/substrate makers and Silicon Foundries are also entering this market. In conclusion the presentation will provide a brief outlook on future supply-chain dynamics scenarios for further discussion.
Biography
Martin Schrems joined the Vienna Office of Boston Consulting Group as a Senior Advisor in September 2020. In this role he supports the global BCG team with focus on semiconductor and electronics industry related projects.
In October 2020 Martin also founded his own company i-conel GmbH where he also serves as Managing Director. i-conel currently develops a new consumer electronics product for washrooms planned to be introduced to the market in late 2023.
Prior to this, Martin served as Corporate Director Strategy, Business Development and Market Intelligence at AT&S AG and VP R&D at ams AG. In both functions Martin was deeply involved in market analysis and development of products leveraging Heterogeneous and 3D Integration such as substrates and „Fan-Out System-in-Board“ technology for modules or the world’s smallest ambient light sensor using 3D/TSV technology. Earlier assignments included semiconductor R&D functions at Infineon, Siemens and Toshiba.
Martin holds a MSc degree (Physics) and a PhD (Microelectronics) from Technical University Vienna, and an MBA from IMADEC (Vienna) with faculty from McCombs school of business (Austin, TX).
Dr. Ralf Schmidt, Manager R&D – Semiconductor, Atotech
Abstract
Electrochemical deposition of copper usually results in certain crystalline layers at first, followed by growth of the individual crystals to the final microstructure. The deposit properties that determine the extent to which this growth occurs, the corresponding timeframe, and the required temperature strongly depend on the respective electrochemical deposition process. In turn, the result of the deposition process may be purposefully controlled by organic additives, their mutual concentrations, as well as process parameters such as current density, convection, or temperature. By this means, the behavior of the respective deposits may be tuned, e.g. as a function of the co-deposited impurities and the initial microstructure. Both, purity and microstructure usually depend on the electrochemical characteristics of the plating additives and the applied current density. By purposefully changing the post-processing behavior of the initially formed layer after deposition and throughout subsequent processes like, for example CMP, the formation of the final microstructure and properties of the deposits may be directed to a post-processing step at elevated temperatures. Depending on the respective application and integration scheme, such post-processing steps requires a certain thermal load. The temperature that allows to obtain the final deposit properties may also be controlled by the parameters of the electrochemical deposition process. Ideally, this temperature should be adjusted to the thermal load, which is required for the respective following process step of the particular application under consideration. The results of this study of the time- and temperature-dependent behavior of electrodeposited copper could potentially be used to optimize the process for upcoming Cu-Cu direct bonding technologies.
Biography
For the past 10 years Ralf Schmidt has held various roles related to R&D at Atotech, wherein he focused, amongst others, on the development of various metal deposition processes. He is currently R&D Manager Semiconductor and responsible for all R&D projects, which are related to Semiconductor and Advanced Packaging topics.
Ralf is author of numerous publications and patents in the field of metallization and materials for microelectronics applications.
Dr. Dave Thomas, VP Product Management, SPTS
Abstract
In 3D system integration, interconnects between chips can be achieved by wafer-to-wafer, die-to-die and die-to-wafer stacking. The choice of one approach over another is driven by the final applications and the desired pitch. There are a multitude of solutions for heterogenous integration of different functions into a single package, and hybrid bonding (a dielectric bond with embedded metal to form interconnections) is one option that promises a high density of interconnections, lower power losses and excellent mechanical reliability, if various material processing and alignment challenges can be overcome.
In this presentation we will describe the latest innovations in plasma etch and deposition technologies which are enabling cost-effective and reliable hybrid bonding, covering silicon etch processes to reduce/eliminate expensive chemical mechanical polishing (CMP), low temperature PECVD of optimized SiCN films for improved bond strength and resistance to copper migration, and plasma dicing where improved die strength and low particles can increase yields and device reliability of bonded stacks.
Biography
Dr. Thomas worked for Philips Components and Nortel before joining SPTS (at that time Electrotech) in 1994 as a PVD Process Engineer, becoming PVD Technology Manager for Japan in 1996. He became Product Marketing Manager for Etch Products in 1997 and promoted to Marketing Director for Etch Products in 2008, responsible for SPTS’s etch product line, including marketing, product positioning & sales support. In 2020, he was promoted to VP of Product Management, expanding his role to cover all SPTS plasma etch and deposition products.
Dr. Thomas holds a BSc in Chemistry (Leeds University), MSc in Surface Chemistry & PhD Plasma Etching & Deposition (University of Bristol), and actively participates, and presents widely on etch and deposition technologies at global conferences. He has also authored over 30 technical articles and papers.
Maurus Tschirky, Senior Product Marketing Manager, Evatec
Abstract
Deriving the figures of merit for your specific function of the piezo-layer is key to creating a successful product. Stress and thickness uniformities are certainly part of it, but how you seed and nucleate, deciding what level of doping is required and understanding what trade-offs you face in production is just as important as film crystallinity. Evatec uses its know how by providing more than just “one size fits all” solutions and supports your full integration needs letting you concentrate on your entire device, rather than parts of it.
Biography
Maurus is Senior Product Marketing Manager at Evatec responsible for the MEMS market segment . He holds a first degree as Engineer in Control Electronics from the University of Applied Sciences in Buchs, and a Masters in Business Engineering / International Marketing from the Hochschule für Wirtschaft und Technik in Zurich, Switzerland awarded in 2009. Prior to joining Evatec in 2016 he held a number of positions in the PVD-equipment industry and roles including application and system engineering, project and product management, and business development.
Frank van de Scheur, GM, Business MEMS & Micro Devices, Philips
Biography
Frank van de Scheur is General Manager of the business MEMS & Micro Devices in Philips since July 2016, based at the High Tech Campus in Eindhoven, Netherlands. His main areas of business interest include process development and manufacturing of thin films, capacitive micro-machined ultrasonic transducers (CMUT), BioMEMS and micro-assembly, for Healthcare and Industrial applications.
He is currently also chairman of the Dutch Association for Microsystems and Nanotechnology.
He has worked for Philips since 2003 in several different roles in R&D in the Netherlands and in Cambridge, United Kingdom. From 1994 to 2002 he worked for Unilever in R&D roles in the Netherlands and Italy.
He obtained a PhD degree in Chemical Engineering from the University of Amsterdam in 1994 and a MSc degree in Chemistry from the University of Utrecht in 1989.
Dr. Walter Weigel, VP, Huawei European Research Institute
Abstract
The talk will give an overview of the technology requirements from typical ICT-applications with regards to MEMS and semiconductors, e.g. for consumer devices, for optical communication and the future of AI. It will also include views on future challenges for the MEMS- and semiconductor industry.
Biography
Dr. Walter Weigel graduated from the Technical University in Munich, Germany, with the Master Degree in electrical engineering in 1984 and with the Ph. D. degree in 1990. From 1984 to 1991 he was assistant professor at the Institute of Data Processing at the Technical University in Munich.
Dr. Weigel is since 1st April 2015 VP of the European Research Institute of Huawei, based in Munich Germany.
He used to be from September 2006 to July 2011 the Director General of the European Telecommunication Standards Institute ETSI. Between February 1991 and February 2015 he held several positions within Siemens AG, including VP of External Cooperations and Head of Standardization in Corporate Technology, VP of the Research & Concepts-department of the Mobile Networks business unit as well as Head of the business segment Video Processing for the semiconductor business unit (today Infineon).
Dr. Wenke Weinreich, Deputy Institute Director, Fraunhofer IPMS-CNT
Abstract
Key Enabler of Edge & Tiny AI – Neuromorphic Computing and Heterogeneous Integration
Neuromorphic computing and heterogeneous integration are the key enablers for future edge as well as tiny AI system, providing energy efficient and fast computation and data storage close to local hardware. The running of AI algorithms can be realized locally and based on the data created by a device without requiring any connection to the cloud. Next to a short excursus on needed innovative design concepts, high potential technological concepts will be discussed. Non-volatile memories like FeFets are promising for low power in-memory and spiking neural network based computing. 3D integration, chipletization and heterogeneous integration allow to overcome the tight memory to logic computing paradigm.
Biography
Dr. Wenke Weinreich is graduated from Technical University Bergakademie Freiberg in applied natural sciences and holds a PhD in electrical engineering from Friedrich-Alexander University Erlangen-Nürnberg. She joined Fraunhofer IPMS in 2006 with focus on material development as well as FEoL and BEoL integration of DRAM, RRAM and MIM Caps. Her research interests are high-k dielectrics and CMOS compatible ferroelectrics for memory applications as well as their pyroelectric and piezoelectric application in sensors, energy harvesting and Si-Photonics. Since 2019 she is head of the Center Nanoelectronic Technologies at IPMS which is the frontend 300mm division of Fraunhofer.
M. Jürgen Wolf, Head of Department, Fraunhofer IZM-ASSID
Biography
M. Juergen Wolf received a M.S. degree in Electrical Engineering from the Technical University Chemnitz. After gaining fundamental experience in the industry and academia for several years, he joined the Fraunhofer Institute for Reliability and Microintegration IZM Berlin and worked as a group & project manager in the field of wafer level packaging and system in package (SiP). He was especially responsible for the development, coordination and implementation of new technologies for wafer level packaging and system integration. From 2000 until 2010 he additionally took over the referent position for the director of Fraunhofer IZM.
Starting in 2009, he was coordinating, planning and realization the new center - All Silicon System Integration Dresden – ASSID of Fraunhofer IZM. Under his leadership a full industrial compatible 12” process line for Wafer level Packaging and 3D integration was established. Since 2011, he is head of the department “Wafer Level System Integration” and also continued managing the center “ASSID”. He is also actively involved in a number of research projects on national, European and international level.
M. Juergen Wolf is a member of IEEE and SMTA and among others, a longstanding member and European representative in different technical international packaging roadmap groups e.g. formally TWG of Assembly & Packaging of the International Roadmap of Semiconductors (ITRS) and now the Heterogeneous Integration Roadmap (HIR) where he is actively contributing to strategy and definition of new technical roadmaps. Since 2016 Wolf is a member of the advisory board of 3D InCites.
Wolf is one of the initiators and co-chair of the Fraunhofer Cluster 3D Integration. He has also initiated the annual 3D European Summit Conference where he is a member of the steering committee. He has authored and co-authored numerous scientific papers presentations and reports in the field of microelectronic packaging and holds a number of patents.
Taguhi Yeghoyan, PhD, Market and Technology Analyst, Semiconductor Manufacturing, Yole Développement
Abstract
Among More-than-Moore devices, CIS feature size is the smallest and requires sophisticated projection lithography equipment able to deliver high resolution feature patterning. Currently, there is only three players (Canon, ASML and Nikon) being able to satisfy the CIS lithography needs. Nevertheless, the revenue for lithography business dedicated to CIS exceeded $300M in 2020 for new brand equipment and is expected to grow in the following years with a CAGR2020-2026 of 11% . CIS is also the main adopter of 3D integration with established high-volume production of sensor stacking with logic die via hybrid or fusion bonding (used respectively in 41% and 23% in total CIS dies shipped in 2020). Hybrid bonding is expected to increase its adoption in CIS die manufacturing to 64% in 2026. Again, only few players will be able to satisfy the needs for HVM of 3D stacked CIS dies (EVG, TEL, SÜSS MicroTec). Nevertheless, in 2020, CIS-dedicated tools exceed 25% of total permanent bonding market of approximately $259M.
MEMS manufacturing technologies are more diverse due to the variety of sensor architecture and application. That leads to high fragmentation of MEMS lithography tool vendors market, offering Mask Aligners, projection steppers/scanners and newly entering Maskless Lithography. Bonding dedicated to MEMS devices constitute also a large part -of permanent bonding tools sold in 2020, including the usage of mature bonding techniques such adhesive, anodic bonding and solder bonding.
This presentation aims to overview technology and market aspects for lithography and bonding equipment dedicated to CIS and MEMS.
Biography
"Taguhi Yeghoyan PhD., is a Technology & Market Analyst, Semiconductor Manufacturing at Yole Développement (Yole), within the Semiconductor, Memory & Computing division.
Taguhi’s mission is to follow daily the semiconductor industry and its evolution. Based on her expertise in this field, especially on the semiconductor value chain (processes, materials, equipment, and related applications), Taguhi performs technology & market reports and is engaged in dedicated custom projects.
Prior to Yole, she worked in world-class European research centers and laboratories, including imec (Belgium), LMI (Lyon, France) and LTM at CEA Leti (Grenoble, France). All along her past experiences, Taguhi has authored or co-authored one patent and more than nine papers.
She has graduated from Wroclaw University of Technology (Poland) and University of Lyon (France). Taguhi also completed her PhD. in Material Science from the University of Lyon (France)."
Day 2
Mor Azarya, Senior Director of Engineering, KLA
Biography
Mor is Senior Director, Head of Packaging business’ central engineering and research team. She joined KLA in 1995 as a software engineer in the OMD (Overlay) division in Israel, and has since been involved in the development of various tools for OMD, EBEAM, and NeXus, in Israel and in the US. Mor was Chair and founder of the Women in STEM Empowered (WISE) ERG in Israel and currently serves as co-Chair. She is also an active member of KLA Israel’s senior staff helping to drive initiatives such as the local hackathon and providing mentoring to several people over the years. Mor holds a Bsc. in computer science from the Technion institution in Israel.
Nicolas Blouin, Sr Manager R&D, JSR Micro NV
Abstract
JSR Corporation's global network is headquartered in Tokyo (Japan) and has factories and offices all over the world. Our strong expertise in the field of Polymer Technology enabled JSR to successfully serve the semiconductor industry for more than 30 years. Our manufacturing and innovation excellence have contributed to a comprehensive line up for high performance semiconductor lithography materials, including advanced materials for packaging and imager. JSR’s presentation will focus on our recent innovation related to new materials for next generation microlens, including material performance and versatility for conventional and grayscale applications.
Biography
Nicolas Blouin studied chemistry at Université Laval, Quebec City, Canada where he was awarded a PhD degree in 2008 for his research work on polymer and material chemistry . From 2009 until 2020, he works in Chilworth, England and Darmstadt, Germany in various positions in R&D within the Performance Material division of Merck KGaA. Since September 2020, he jointed JSR Micro NV as Senior R&D manager overseeing the semiconductor R&D activities within Europe. Throughout his career, he managed a variety of multi-disciplinary technology projects in the fields of organic electronic, photovoltaic and semiconductor.
Beate Burkhart, Head of Materials Innovation Pipeline, Semiconductor Solutions, Merck
Abstract
Merck is committed to expanding opportunities for female leadership, and to having a gender-balanced workplace, enriched by the perspectives of both women and men.
In this presentation, we will talk about Merck's Material Innovation Pipeline team and how they benefit from a diverse organization. As the leader of the team, Beate will share personal stories and anectodes around what is going well, but also where she sees room for improvement.
We will conclude the presentation with concrete examples of Merck's D&I activities - including groups the different activities focus on, events and activities and also the need to make Diversity a responsibility for everyone in the company.
Biography
Beate Burkhart is the Head of Materials Innovation Pipeline, Semiconductor Solutions in our Electronics business sector and holds a Ph.D. in Polymer Chemistry from the University of Southern California.
She and her team are looking into the next generation needs of the semiconductor materials industry. This requires proprietary materials innovation and a deep understanding of materials' structural properties for sustainable business development and to remain competitive in the market.
Jean Charbonnier, R&D Project Leader, CEA Leti
Abstract
To reach quantum supremacy, large scale integration of quantum bits through three dimensional (3D) architectures functional at sub-Kelvin temperatures is required. Electrical signals will be transferred by 3D interconnects which need to be carefully designed in term of materials and dimensions to optimize the whole system performance. To that end, SnAg microbump-based interconnects and direct Cu bonds have been fabricated with die-to-wafer processes and tested until 400 mK. These last year results will be introduced with a general overview on the advantages of 3D integration for quantum computing.
Biography
Jean Charbonnier, is graduated from National School of Physics of Grenoble in 2001 and obtained his Phd degree in crystallography from University Joseph Fourier of Grenoble in 2006. He joined the 3D wafer level packaging group of CEA-Leti in 2008. He has been working for more than 10 years in Through silicon vias, 3D interconnections and silicon interposers technology. His research interests include High Performance computing, Silicon Photonics Interposer as well as cryo-packaging for Quantum architecture applications. He is currently in charge of coordinating the High Density 3D Integration group within the 3D Integration Technologies Laboratory of CEA-Leti.
David Haynes, Managing Director, CSBG Strategic Marketing, Lam Research
Biography
David gained a B.Eng and PhD in Materials Engineering from Swansea University. His PhD thesis was in the field of organic semiconductors for electronic and optoelectronic applications.
In his professional career, David has accrued more than 20 years of experience in the Semiconductor Capital Equipment and research instrumentation sectors with STS, SPTS and Oxford Instruments. Focused on new technology development, he has a strong process background in plasma etch and deposition for optoelectronics, photonics, MEMS, Power and RF Electronics, as well as advanced chip packaging technologies.
Building on this technical knowledge, David has a proven track record in developing strategic business partnerships; specialising in new technology developments and introduction of enabling process capabilities to leading semiconductor fabs worldwide.
David Joined Lam Research in June 2016 and is currently Managing Director of Strategic Marketing in Lam’s Customer Support Business Group.
Yoav Hirsch, Project Manager CIS R&D, Tower Semiconductor
Abstract
Among Industry 4.0 pillars are the smart sensors, wide bandwidth of communication and the ability to convert data into information. In this session we will take a short glance at the latest innovations of the image sensors technology, which stretches the technology boundaries of semiconductor industry to support the need for beyond state-of-the-art cyber-physical devices.
Mr. Yoav Hirsch serves as a leading project manager at Tower’s Sensor business unit. As part of his role he is in charge of various image sensor technology projects, supporting the sensor’s business unit development roadmap. Mr. Hirsch has extensive experience in the semiconductors industry, specializing in the field of CMOS image sensor. Throughout his career, he held various positions in SCD, ECI-Telecom and AFCON-industries where he managed a variety of multi-disciplinary technology projects, which required, amongst others, expertise in the fields of industrial control, system engineering, manufacturing, and design electronics.
Mr. Hirsch holds a B.Eng Electrical Engineering from Coventry University, England, M.Sc. in Electrical engineering from Tel-Aviv University and an MBA from Haifa University, Israel.
Tony Mastroianni, Advanced Packaging Solutions Director, Siemens EDA
Abstract
Current Artificial Intelligence (AI) ASIC devices are generally comprised of a two dimensional array of processing blocks, with external DDR or HBM memory interfaces, external Serdes data interfaces, a PCI Serdes PC interface and general purpose test and control IO and logic. These AI ASIC processers are then populated on a PCB board interconnected through the embedded Serdes data interfaces. AI ASIC devices deploying HBM memories leverage 2.5D packaging technology to mount and connect the AI ASIC to the HBM memory within the package. As an ecosystem of general purpose chiplets become available, alternative micro-architectures of AI ASIC devices can be considered. This presentation will present a few alternative AI ASIC micro-architectures to stimulate the concept of leveraging heterogeneous, System in Package (SiP) to design higher performance and/or lower costs AI systems.
Biography
Tony Mastroianni has more than 30 years of experience as an engineer and engineering manager in the global semiconductor industry. In recent years, he has focused significantly on advanced ASIC package design flow development (2.5/3D). He currently leads development of Advanced Packaging Solutions for Siemens Digital Industries Software. Prior to joining Siemens, he served in engineering leadership positions at Inphi and eSilicon. He earned a bachelor’s degree in electrical engineering from Lehigh University and a masters in electrical engineering at Rutgers University.
Marek Kysela, Senior Coordinator Advocacy, SEMI Europe
Biography
Marek is SEMI Europe’s Senior Coordinator for Advocacy, responsible for coordinating SEMI Europe’s R&D projects and technology policy program. Prior to SEMI, he obtained experience in ICT project management with EU institutions and gained experience of (cyber) security policy. Marek obtained his master’s degree in International Relations with focus on technology from Sogang University in Seoul, Republic of Korea and specialized certification in Chinese Foreign Affairs from Peking University in Beijing, China. During his studies, Marek actively promoted cooperation between Europe and the Asian region in the field of technology and cyber/ICT security by encouraging discourse with government stakeholders through bilateral and multilateral platforms.
Vladimir Koifman, CTO & Founder, Analog Value Ltd.
Abstract
Despite COVID pandemic across the world, the image sensor technology and business progress continues. A part of the progress is incremental improvements of pixel and sensor technology, while the other part is new and disruptive ideas. The presentation covers both technology and business developments in the last two years.
Biography
Since 2011, Vladimir Koifman is CTO of Analog Value Ltd. developing new approaches in image sensor design. Prior to that, in 2004, Vladimir co-founded Advasense image sensor company acquired by Pixim, and, later, by Sony. Prior to that, he co-founded AMCC Israel analog design center. In 90s, Vladimir worked for Motorola Semiconductor, developing mixed signal processors for the company's mobile phones. Vladimir has authored 10 papers and received over 50 patents. Among his other activities, Vladimir maintains the Image Sensors World blog over the last 15 years.
Maarten Liebens, Product Marketing Manager, KLA
Abstract
The ability to directly stack die utilizing direct Cu-to-Cu connections rather than microbumps has revolutionized CMOS image-sensor (CIS) technology and promises to do the same in the integration and packaging of Memory and Logic Devices. This capability, when combined with new multi-die heterogeneous integration system architectures, has the potential to drive significant changes in advanced packaging. This workshop will explore the process, inspection, and metrology challenges that need to be solved in order to enable hybrid bonding in new product types.
Biography
Maarten Liebens received his M.S. (2006) in electro-mechanical engineering from the Catholic University of Leuven. He is currently working at KLA as product marketing manager for metrology equipment in the advanced packaging market, both wafer and substrate level manufacturing. Prior to KLA, he worked at imec and held several positions as integration engineer in the 3D program, defectivity & metrology engineer, and lithography process development engineer. After his studies he started at ASML as a development engineer for stage positioning measurement systems of the advanced lithography scanners and worked afterwards at KLA-Tencor as applications engineer for automated defect inspection systems for LED, MEMS and packaging applications.
Cassandra Melvin, Director, Operations & Business Development, SEMI Europe
Biography
Cassandra Melvin received her BS in Business Management and Neuropsychology at Rensselaer Polytechnic Institute and is Director of Operations & Business Development at SEMI Europe. For the nine years prior to joining SEMI, she held the position Global Product Manager at Atotech Deutschland GmbH, where she was responsible for managing several hundred electroplating chemistry products in its Semiconductor and Functional Electronic Coatings division. She began her career at the SUNY Polytechnic Institute (formerly the College of Nanoscale Science and Engineering) as a Business Manager focused on strategic and technical programs for semiconductor chemistry and equipment manufacturers. She also held various project and program management roles in clean room operations and IT at SUNY. Cassandra's written work has been published in leading technical magazines and presented at key conferences globally. As an advocate for diversity and inclusion, she is actively involved in SEMI's efforts to promote diversity within the semiconductor industry.
Christine Pelissier, Business Line Manager EMEA, Edwards Vacuum
Abstract
What does your company do to drive inclusion in the workplace? How is D&I perceived by employees and leaders? Is it just a reporting goal or does it change awareness and behaviour?
In her presentation Christine talks about the change journey in the last 2 years at Edwards.
Biography
Christine Pelissier is Business Line Manager EMEA at Edwards Vacuum. She has over 25 years’ experience successfully growing markets and customers in a high-tech environment and has broad international experience building networks in North America, Europe, and Asia. Prior to joining Edwards, Christine has held senior strategic marketing positions, business development, operations and applications roles with Applied Materials, KLA-Tencor and Soitec.
M. Jacques Renaud, Ph.D., Process Integration Manager, Teledyne DALSA Semiconductor
Abstract
MEMS market success relies heavily on product quality, but the one product one process paradigm and the complex integration challenges that are common for most of MEMS manufacturing can make this condition difficult to achieve. In this presentation we will discuss a few smart processing technologies that will help the next generation of MEMS improve quality to achieve success.
Biography
Jacques is the Manager of the Process Integration team at Teledyne DALSA MEMS foundry in Bromont and has Ph.D. in Physics from the University of Sherbrooke. After completing his Ph.D. in 2006, he joined Teledyne in the bonding and wafer level packaging process engineering team. Since then, he held multiple roles in process engineering, technology development, project management and process integration. During those years he played key roles in the process development and high volume production ramp of many highly successful MEMS programs for the consumer, industrial and automotive markets. He also managed the start-up of thin film, wafer bonding and polishing technologies at C2MI. Currently, as part of his role as Process Integration Manager, he leads the technical business development efforts for the Teledyne DALSA MEMS foundry.
Tim Skunes, VP of R&D, CyberOptics Corporation
Abstract
Recent results have correlated copper thickness variations across a wafer during electrochemical deposition (ECD) to variations in metal dishing depth variations in hybrid bonding applications. Copper pillar coplanarity is also correlated to ECD plating uniformity in wafer bumping applications. The plating uniformity during ECD is directly affected by plating cell contact resistance. In-process monitoring of plating cell contact resistance can accurately predict when preventive maintenance is required to maintain thickness uniformity and to save time and costs associated with test wafer measurements. Tim Skunes of CyberOptics presents a real-time sensor for measuring plating cell contact resistance.
Biography
Tim Skunes is the Vice President of R&D at CyberOptics Corporation. He was previously the Director of Product Development from 2003 to May 2010. He held the position of Vice President, Systems Development at Avanti Optics Corporation from 1999 to 2003. Prior to this, he was the Research Manager at CyberOptics from 1997 to 1999. He holds a M.EE., Optics and Electrical Engineering from the University of Minnesota and has 28 U.S. patents in his name for optical measurement systems, optical manufacturing, and fiber optic devices.
Ralf Schellin, Head of Product Area MEMS, Robert Bosch GmbH
Abstract
MEMS sensors are playing a key role as the silent enablers of todays and future consumer electronics applications. With the growing relevance of social trends like safety, health and personalization, the complexity of daily-life use cases is increasing. To tackle the resulting challenges, new approaches are required in the MEMS sensor industry. In order to continue providing additional value to customers, a stronger focus on hardware-software co-design is required by using advanced algorithms and embedded AI. In his keynote presentation, Dr. Ralf Schellin, Vice President and Head of Product Area MEMS at Bosch Sensortec, will illustrate the “silent” role of advanced algorithms, MEMS sensors and embedded AI by providing specific use case examples in the context of localization, environmental sensing and self-learning.
Biography
Ralf Schellin received his PhD degree in Electrical Engineering and his Master degree in Technical Physics at the Technical University of Darmstadt, Germany. Currently he is based in Reutlingen, Germany, where he is Head of the Product Area MEMS of Bosch Sensortec. Prior to this, he was Director of Product Management of Bosch Sensortec. From 2010 to 2014 he was leading a cross divisional project at Bosch on Tiny Wireless Sensors for the Internet of Things. From 2007 to 2009 he was leading an engineering group at Bosch Sensortec. Between 2001 and 2006 he held various positions in engineering and product management at Siemens in Munich, Germany, in the area of mobile devices based on IP technologies. Between 1996 and 2000 he was leading various projects in the automotive area of Bosch in Reutlingen working on safety relevant MEMS based sensors. Prior to Bosch he was holding a post-doc position in biosensors at University of Twente, Enschede, The Netherlands.
Franz Schrank, Director R&D - Wafer Level Integration & Photonics, ams-OSRAM group
Biography
Franz Schrank has 20 years of experience in 3D integration, CMOS post processing and MEMS. Franz received the Dipl.-Ing. degree in physics and the M.A.S. degree in Nanoelectronics and Nanoanalytics at the University of Technology in Graz, Styria, Austria. He currently holds 34 patents in the field of 3D technology, MEMS and opto technology.
Pascal Vivet, Scientific Director of the Digital Systems and Integrated Circuits Division, CEA-LIST
Abstract
Overview on 3D technologies for Smart Imagers, presenting various successful circuit architecture and design projects integrating Smart Imagers, with insights towards the realization of future Multi-Layer Imagers integrating advanced AI features.
Biography
Pascal Vivet is Scientific Director of the Digital Systems and Integrated Circuits Division in CEA-LIST, Grenoble, France. He received his PhD from Grenoble Polytechnical Institute in 2001, designing an asynchronous microprocessor. After 4 years within STMicroelectronics, he joined CEA-Leti in 2003 in the digital design lab. His research interests covers wide aspects of circuit and system level design, ranging from system integration, multi-core architecture, Network-on-Chip, energy efficient design, related CAD design aspects, and in strong links with advanced technologies such as 3D integration, Non-Volatile-Memories, photonics. He was project leader on 3D circuit design and integration since 2011. He participates to various TPC such as ESSCIRC, DATE, 3DIC, ISLPED, ASYNC, conferences. He served as a member of the organizing committee of the 3D workshops series at DATE from 2013 to 2015, and to the D43D workshops since 2011. He has authored and co-authored more than 100 papers and holds several patents in the field of digital design. He co-authored a book chapter on “3D Integration in VLSI Circuits: Implementation Technologies and Applications”.
Dr. Alexander Weiss, Department Manager Fraunhofer ENAS
Abstract
We report on the progress in miniaturization of micromechanical components for spectrometer systems in the infrared. MEMS-based spectral technologies from Chemnitz have a long tradition, starting with Fabry-Pérot interferometers (FPI) that are used for narrow band filtering of electromagnetic radiation in the visible and infrared wavelength ranges. With apertures larger than 2x2 mm², these filters can also be used in hyperspectral camera systems.
Other, more recent developments deal with miniaturized, modular spectrometer system that combines a large number of individual optical and micromechanical components, which can be combined at chip level to form diverse spectrometer systems. This has the advantage that the complexity of the system only affects the design, but not the technology sequence. Fabrication in a near-surface micro technology allows guidance and modulation of infrared radiation at the chip level. Thus, a high degree of miniaturization and complexity of the overall system is achievable. The talk shows aspects of these technological developments as well as achieved results and application scenarios.
Biography
Alexander Weiß received the Dr.-Ing. degree on spectral sensor system design, test and application from Chemnitz Univ. of Technology in 2013. He is active in the field of optical and spectral components and systems as well as hybrid sensor systems based on micro and nanotechnologies for industrial applications. Since 2021, he also leads the department Multi Device Integration at the Fraunhofer Research Institute for Electronic Nano Systems (ENAS) in Chemnitz, Germany.
Xavier Rottenberg, Scientific Director - Group Leader Wave-Based Sensors and Actuators, imec
Abstract
Future sensing techniques and applications require ever higher performance and integration at lower power and cost. As an example, ultrasonography and photoacoustic imaging require the development of matrixes of high frequency, small and sensitive ultrasound sensors with read-out through flexible cables maintaining high signal quality. Silicon photonic ultrasound sensors have the prospects of enabling these emerging imaging techniques. Indeed, these small and sensitive sensors are fabricated at wafer-scale in emerging integrated photonics platforms and can be interrogated through matrix read-out via single optical fiber using photonic multiplexing. This presentation will introduce optical sensors and in particular pressure sensors in static and dynamic domains, reaching to the ultrasound. We will focus on optomechanical ultrasound sensors with extreme sensitivity, achieved with an innovative optomechanical silicon photonic waveguide in an acoustical membrane.
Biography
Dr. Xavier Rottenberg obtained his MSc degree in Physics Engineering and the DEA in Theoretical Physics from the Université Libre de Bruxelles in 1998 and 1999, respectively. In He 2008, he earned his Ph.D. degree in Electrical Engineering from the KU Leuven. Xavier worked at the Royal Meteorological Institute of Belgium in remote sensing from Space for one year and has been at imec since 2000, contributing to research in the field of RF, RF-MEMS, photonics, and microsystems modeling/integration. As an imec fellow, Xavier currently leads the Wave-based Sensing and Actuation Developments, working among other topics on integrated photonics, flat optics, acoustics, photo-acoustics, and M/NEMS. He has authored or co-authored over 150 peer-reviewed publications, has been granted various patents, and has lectured or been an invited speaker at notable events including: DTIP (‘05), EuroSimE (‘08), ESREF (‘08), ESoA (‘10/‘12/‘14), RF-MEMS summer school (‘13), FETCH 2016, NERF Neurotechnology Symposium (‘16), OpenMinds (‘17), and Nanoworkshop at Beijing University (‘18). In 2019, Xavier co-founded Pulsify Medical—a young company developing ultrasound imaging patches.
Day 3
Michael Bailly, CEO, Silina
Abstract
Silina is a deeptech startup in microelectronics, offering technological solutions to curve the imaging sensors produced by traditional sensor manufacturers, at industrial scale. Curved imaging sensors are the next major innovation for the imaging industry. They unlock hardware limitations that no software can solve, and bring a whole new generation of vision systems. They enable drastic improvements on four key fields: image quality, low-light detection capability, camera cost reduction and camera compactness.
Biography
Michael Bailly is the CEO of SILINA. He holds an Engineering degree in physics from Ecole Polytechnique and a Master’s in Management of Technology from UC Berkeley. Most of his professional career has been spent managing and setting up First-Of-A-Kind industrialization projects in long cycle technological industries. In 2020, he started a new challenge by creating SILINA with his Co-founder and inventor of SILINA's technology, WIlfried JAHN.
Daniel Graf, Business Development Manager, 0eC
Abstract
Zero EC, a Swiss-Israeli technology Startup, has successfully demonstrated the ability to transport data at extreme low energy (0.001 pJ/bit).
The technology which is Silicon- and CMOS-Compatible provides a high-scalable solution to increase bandwidth density for Interconnects in the upcoming years to entirely new levels and therefore can be considered a key technology to overcome the end of Moore’s law.
Besides Interconnects the technology can be applied in Quantum Computing, AI, SoC and might even one day replace the transistor as it is known today.
Join our presentation to learn about the LED for Data!
Biography
Daniel Graf is Head of Business Development at Zero EC since 2019. He is responsible for marketing and investor relations as well as the public presentation of Zero EC.
Prior to his work at Zero EC, Mr. Graf spend more than 10 years as IT Consultant and has been Co-Founder and CEO of a consulting company which supported Investors and StartUps to develop and scale their business using agile Methods.
Recently he, together with Zero EC, was rewarded with the “German Innovation Award ‘21” in the category Excellence in Business to Business - Electronic Technologies.
David Keicher, VP, IDS
Abstract
Integrated Depostion Solutions (IDS) has developed the next generation aerosol printing technology (trademarked NanoJet™) for printed electronics and bioprinting applications. This talk will cover recent improvements aimed at providing a viable print option for features from 10µm to 100µm in width and ranging from a few microns to over 30 microns in height. The focus of this effort is for production applications. Data will be presented showing printed line widths and measured conductivity for continuous printing of conductors to form coils that are ued for wireless power transfer and data transfer for embedded circuits. Clean printed line edge quality will be shown and methods used to achieve these results will be discussed. Printed circuits for implantable medical devices requiring inductive power coupling will be discussed.
Biography
Mr. Keicher has been involved in the field of Additive Manufacturing (AM) since 1993. He is an inventor of the Laser Engineered Net Shaping (LENS) process developed at Sandia National Laboratories. Mr. Keicher is a founder of Optomec and was instrumental in the development and commercialization of the LENS and Aerosol Jet printing processes at Optomec. While at Optomec, Mr. Keicher was instrumental in growing Optomec from approximately $150k/year to over $10M/year prior to exiting Optomec in 2011. Mr. Keicher returned to Sandia in 2011 after his exit from Optomec to focus on developing new technologies in the AM arena. During his tenure at Sandia, Mr. Keicher was able to collaborate with Dr. Marcelino Essien to develop the next generation aerosol printing technology trademarked NanoJet™. Together Dr. Essien and Mr. Keicher have developed and productized the NanoJet printing technology to address needs in aerosol printing. Mr. Keicher joined Integrated Deposition Systems (IDS) in July 2018 to help drive the commercialization of the NanoJet technology at IDS. The NanoJet print technology is gaining industry acceptance by providing a compact, reliable, easy to use and cost-effective aerosol printing technology well suited for production applications.
Łukasz Kosior, Business Development Manager, XTPL
Abstract
Additive manufacturing transforms the landscape of the semiconductor industry. Recent years have witnessed tremendous progress in the area of printable imaging, sensor, and MEMS systems. The trend towards increasing complexity and miniaturization of these devices, and therefore the need for efficient, precise, and cost-effective fabrication techniques is very clear.
To tackle these challenges, we developed a novel ultra-precise deposition (UPD) technology for heterogeneous integration in semiconductor devices. This includes vias filling with conductive and non-conductive material, as well as printing micro-bumps and creating conductive top-to-bottom connections.
UPD allows maskless, direct deposition of highly-concentrated silver and copper inks (even 82% wt. of metal content) on complex substrates. The printed structures are characterized by feature size in the range from 1 to 10 μm and remain uniform regardless of the wetting properties of the substrate. Therefore, it is possible to print on materials with very different wetting properties, such as oxides (e.g. SiO2), nitrides (e.g. SiNx), metals, glass, and foils (e.g. PI, Kapton), as well as to print on junctions (metal/semiconductor/insulator) and cover vertical steps. The electrical conductivity of the metal structures is up to 45% of the bulk value.
Thanks to these features, we argue that UPD can become an indispensable element of modern production lines of high-performing imaging, sensor, and MEMS systems, facilitating next-generation design and architectures.
Biography
Responsible for commercialization of XTPL products and technology to the R&D and manufacturing sectors. He received his Master of Science degree in the field of Electronics Photonics and Microsystems at Wroclaw University of Science and Technology. After graduation he continued his research activities in the projects related to fabrication of optoelectronic and other semiconductor devices, including Quantum Cascade Lasers. For over 3 years Łukasz has been working at the Business Development department at XTPL, managing commercialization activities and introducing Ultra-Precise Deposition technology to industry and R&D customers.
Andreas Kopetz, Vice President Environmental Sensing, Infineon Technologies
Abstract
Andreas Kopetz as part of his updates as the past technology showcase winner will demonstrate on the use case and value add enabled by CO2 sensors and list examples that make our lives easer safer and greener.
Biography
Andreas Kopetz received his Master of Computer Science from Vienna University of Technology in 2004 and a Master of Engineering Management from Duke University, in 2005. Andreas started to work for Infineon in 2005 in the Operations & Supply Chain group covering several positions in USA, Austria and Germany. In 2010 Andreas joined Infineon’s Automotive division as product marketing manager for Electric Drivetrain power modules for hybrid and electric vehicles. In 2013 he transferred to the RF & Sensors business line within Infineon’s Power & Sensor Systems division. He has been substantially growing Infineon’s MEMS Microphone & pressure sensor business since then, recently as Director Marketing heading the product marketing and application engineering teams. Since March 2019 he is in charge of the accelerator program for environmental sensing.
Takashi Mochizuki, Global Product Manager, Merck
Abstract
Transient liquid phase sintering (TLPS) pastes are similar in form, fit and function to conventional lead-free solder pastes. Unlike single element solders, TLPS is formed with several alloys and metals providing high thermal stability after low temperature curing. These features allow TLPS compatibility in circuit designs with low temperature process requirements and yield improvement for devices requiring a secondary thermal process step.
The low temperature assembly with non-remelting characteristics, deliver the solution for small components assembled on an advanced package substrate, an embedded or BGA package assembly as well as a Heterogeneous substrate “board to board inner metal layer interconnect ” in the Z axis . .
1. Components assembly on Advanced Package Substrate
No-Remelt under multiple reflow: Improved fatigue resistance, reduced shorting potential with very small component sizes.
2. Advanced BGA Package Assembly on PCB
Low temperature TLPS (<150℃) contributes to mitigate the Warpage for both BGA Package and PCB Board during assembly process. And not remelting for further Pb-free solder reflow process.
3. Board to Board interconnects (Z-axis interconnects)
Integration and density drive semi additive processes involving Z Interconnects Shorter circuits improve signal integrity, less lamination cycles increase reliability and improve production yield compared to the existing build-up process by plating for high layer counts.
Biography
Takashi Mochizuki has more than 20 years of experience successfully growing the electronics material industry. He is currently working at Merck as a global product manager for conductive paste in the packaging, substrate, and assembly market. Before Merck, he worked at DuPont as the new business development and sales/marketing roles for Conductive paste. He earned a bachelor’s degree in material science from Teikyo University in 2000.
Abul Nuruzzaman, Vice President, Product Marketing, Xperi Corporation
Abstract
As the limits of Moore’s Law are being challenged, the industry is looking beyond conventional 2D scaling techniques to 3D structures, packages and interconnect innovations. Xperi has achieved fundamental advances in 3D semiconductor packaging and interconnect required to satisfy the demanding size, performance and functionality requirements of consumers today and tomorrow.
In this presentation speaker will go over how hybrid bonding technology in enabling new generation of semiconductor devices. Speaker will explain Xperi’s continuous innovation in Hybrid Bonding- its foundational DBI and DBI Ultra hybrid bonding technologies that are reshaping the semiconductor industry through various 2.5D and 3D integrated solutions.
Biography
Abul Nuruzzaman is VP, Product Marketing at Xperi Holding Corporation, San Jose, California. He leads the marketing of Xperi’s semiconductor technologies and IP portfolio. Prior to joining Xperi, he worked in product management, marketing and business development roles at AMD, Infineon (Cypress Semiconductor), TE Connectivity and Lattice Semiconductor. He is fluent in Japanese and holds a BSEE degree from Osaka University, Japan, and an MSc degree in Electrical Engineering from the University of California, Los Angeles (UCLA).
Steven Steen, Director, Product Management - 3D Memory Solutions, ASML
Biography
Steven Steen is director of Product Management at ASML. In this role he is responsible for the applications to drive overlay performance of ASML’s scanners. After his education at the Hogeschool Enschede he already started his career at IBM’s T.J. Watson Research Center during the final stages of his education.
Leading edge innovation is the consistent thread during his 24 years’ experience in semiconductor R&D (of which 20 in lithography). Steven joined IBM Research in 1997 to develop and commercialize full chip timing diagnostics through Picosecond Imaging Circuit Analysis. In 2001, Steven moved to the chip processing side by joining the Microelectronics Research Line at IBM Research and started his lithography career there. During a wide variety of roles he worked to realize numerous device technologies and business opportunities. He moved to the Netherlands and joined ASML in 2012 to lead the definition and development of innovations and unique product offerings to ASML’s customers.
Holder of over 22 US Patents and 35 published research papers, Steven continues to think of new applications and the challenges of the future. Outside of work he is often found near the water for sailing, swimming or other forms of water sports.
Dr. Martina Vogel, Advisor to the institute management, Manager Marketing/PR, Fraunhofer ENAS
Biography
I studied physics at the Chemnitz University of Technology, Germany. I obtained my PhD from the same university in 1994. From 1996 until 2001 I worked as project manager in the GPP Chemnitz mbH. From 2001 until 2006, I was responsible for quality assurance of memory products at ZMD. In 2006, I joined the Center for Microtechnologies of Technische University Chemnitz. Since 2009 I am with Fraunhofer ENAS and work as advisor to the institute management, manager marketing/PR and since 2017 also as head of Quality Management.
Since many years I work in the MEMS & imaging sensor SEMI committee of the MEMS & Imaging Sensors Forum.