Technology and Trends

Daniele Pagano is a Project Manager at STMicroelectronics and standardization leader for the Heterogeneous Integration for Connectivity and Sustainability (HiCONNECTS) consortium, a coalition of 65 partners from 15 countries developing solutions for electronic components and systems. Through his work, Pagano is directly shaping the next generation of semiconductor manufacturing. SEMI spoke with Pagano about how integrating standards earlier in the development lifecycle can help bridge the gap between lab innovation and commercial deployment.SEMI: Could you tell us about your role at STMicroelectronics (ST) and what first drew you to semiconductor manufacturing?Pagano: At ST, I focus on advanced semiconductor manufacturing and innovation projects. I coordinate multidisciplinary teams, drive manufacturing development initiatives, and ensure that research outcomes translate directly into industrial applications.In parallel, I lead standardization activities focused on maintenance and cybersecurity for HiCONNECTS. These areas are central to our mission, which is to develop core technology solutions for heterogeneous integration. Through HiCONNECTS, we emphasize development in areas like RF infrastructure and IT data applications, which are quickly becoming the backbone of modern digital society. Semiconductor manufacturing attracted me because it combines science, engineering, and real-world impact. Semiconductors also underpin every technology we use today. They power everything from smartphones and electric vehicles to medical devices and industrial automation. I was also fascinated by the challenge of transforming cutting-edge research into innovations that are both highly scalable and reliable. SEMI: In HiCONNECTS, you're involved in both advanced manufacturing development and standardization. How do these two areas complement each other?Pagano: Both disciplines are closely interconnected. Advanced manufacturing focuses on creating technologies and processes that improve performance and reliability. Meanwhile, standardization helps ensure those innovations can be scaled. Without standardization, many promising technologies would struggle to move beyond the lab.Working across both areas within HiCONNECTS gives me a valuable perspective. As new technologies emerge, we can identify potential standardization needs early to ensure that available data is usable, complies with privacy and cybersecurity requirements, and can be broadly implemented across different applications. Daniele Pagano presenting at SEMICON Europa 2023SEMI: Your work explores areas like AI, digital twins, and data analytics. How do you foresee these technologies changing the way chips are produced over the coming years?Pagano: All of these technologies are becoming more crucial for the industry as semiconductor manufacturing processes get more complex. For instance, modern production environments generate large amounts of data, and AI can extract meaningful insights from that information to improve processes down the line. Digital twins are particularly valuable because they can generate virtual representations of entire production lines. They create a realistic environment for engineers to predict outcomes and improve operations without halting the entire production line. Within the HiCONNECTS project, new digital twins are being developed to optimize dispatching, scheduling, and shop floor productivity.Semiconductor factories will also become even more data-driven in the coming years, with higher levels of automation and real-time decision-making. Ultimately, digitization gives manufacturers greater freedom to produce the devices the world depends on. SEMI: Sometimes, standards are only considered after innovation. Why do you think it’s important to think about standardization throughout a research project like HiCONNECTS?Pagano: In reality, standardization should occur alongside innovation. When standards are considered at an earlier stage, researchers can better identify interoperability requirements, common terminologies, measurement methods, and best practices. However, due to the complexity of heterogeneous integration, addressing use-case requirements and standardization in tandem is key if we want to bring new technologies into production. To do this, we need cross-disciplinary collaboration. Ultimately, the goal can be broken into three steps. First, create innovative technologies in the lab. Second, ensure they can be successfully transitioned into high-volume manufacturing environments. And finally, leverage AI and digital twins to improve innovations over time. Standards play a crucial role in making all of that happen, and accomplishing each of these things is only possible when we work together. SEMI: HiCONNECTS brings together partners from industry, academia, and research organizations. What have you found most valuable about working in such a collaborative European project?Pagano: One of the greatest strengths of HiCONNECTS is our diversity of expertise. Industry partners contribute practical knowledge of manufacturing challenges and market needs, while academic and research organizations often bring fresh perspectives, novel methodologies, and deep scientific insights.Merging different disciplines also creates an environment where innovation can flourish. Challenges can be approached from multiple angles, and solutions benefit from more resources than any single organization can provide. From a personal perspective, I find the exchange of knowledge to be particularly valuable. Collaborative European projects like HiCONNECTS encourage openness, learning, and the creation of long-term professional networks. These relationships often continue beyond the life cycle of the project, and they help strengthen Europe’s semiconductor ecosystem. SEMI: Finally, what advice would you give to students and early career engineers who are considering a career in the semiconductor industry?Pagano: The first piece of advice is to embrace continuous learning. The semiconductor industry evolves rapidly, and new technologies emerge all the time. A strong foundation in engineering, physics, materials science, data science, or computer science can open several career opportunities in this field.Second, focus on developing strong technical abilities alongside effective collaboration skills. Modern semiconductor innovation relies on multidisciplinary teams, so the ability to communicate effectively and work across different domains is just as important as technical expertise.Lastly, do not underestimate the importance of resilience and problem solving. Semiconductor manufacturing is one of the most challenging engineering environments in the world, but it’s also one of the most stimulating. The technologies we develop directly impact society, so for anyone passionate about technology and innovation, it’s an exciting industry to build a career in. About HiCONNECTSHiCONNECTS (Heterogeneous Integration for Connectivity and Sustainability) is a three-year project bringing together 65 partners to develop sustainable, energy-efficient cloud and edge computing platforms. The project focuses on high-performance computing, storage infrastructure, network interfaces, and real-time analysis of IoT sensors and big data. SEMI Europe actively contributes to EU-funded initiatives, including Horizon Europe and Erasmus+ programs, capitalizing on its global member base and its role as the voice of the microelectronics industry. These activities enable SEMI to connect industry, research, and policy stakeholders while advancing European competitiveness and technological leadership. Learn more.Kartikey Srivastava is Lead of EU Projects at SEMI Europe.Daniele Pagano is Project Manager at STMicroelectronics Italy.

The headlines are dominated by the unprecedented growth in data centers and their rising energy consumption, along with the skyrocketing user cost of AI for inference at scale. Perhaps less obvious is the direct connection between the two – reducing energy consumption reduces AI cost. This is because both require smart use of AI system capability at maximum efficiency, which is often not the case today.Energy efficiency must be a strategic priority for all companies using AI inference, not just for data center builders. Smarter AI usage with lower energy consumption and less cost will help enhance the financial bottom line. Leadership in energy efficiency innovation will also generate a topline reward for companies expanding into AI’s next frontier, physical AI – when AI ventures off the computer screen into the real world. A robot, a drone, or a wearable typically run on a limited battery, so energy efficiency is a must-have, not optional!Each of these challenges can turn into opportunities.EnergyAI training compute is growing at an estimated 4–5x per year, with the latest large language models (LLMs) reportedly using 5-50 trillion parameters. The rapid growth of AI inference at scale amplifies this massively and generates enormous energy demand. In the US, data center energy consumption has tripled over the past decade and by most projections, it will triple again in just 5 years! The International Energy Agency (IEA) estimates that globally, data centers consumed ~460 terawatt-hours (TWH) of electricity in 2025, which will more than double to 945 TWH by 2030. For perspective, this is more power than the entire country of Japan uses today!The global energy infrastructure was not designed to absorb this level of demand. Communities across the world are pushing back against this strain on their power grid and water supply, as prices rise and shortages occur. Nuclear energy may help augment the traditional grid, but it is a distant hope, at least a decade away. This challenge cannot be ignored and could become a major roadblock for the future of AI. It is no surprise that energy is now the strategic currency for AI globally, with AI business transactions now being announced in Gigawatts, rather than Megaflops.CostInvestment in AI system infrastructure is rising at a dizzying pace: top players invested ~$100B for data centers in 2020, and this will increase TENFOLD to ~$1 trillion in 2026! Broader global investments are even higher. But there is no free lunch: everyone must pay! AI users are now feeling the pinch as they use more AI for inference, and even big players have reportedly blown through their annual AI budgets in just months. To make matters worse, only a small fraction of AI applications currently generate financial value and provide the expected return-on-investment (ROI). In part, this is because basic AI capabilities are becoming table stakes: companies invest in expensive AI tools that may enhance a product or service, but competitors do the same; so there may be no price premium to be had. AI tokens have become the basic unit for quantifying workloads and cost, as AI providers typically bill usage in millions of input and output tokens. Daily token consumption in the US is projected to increase TENFOLD from today’s ~200 trillion units per day (TUs/day) to ~2250 TUs/day by 2030. Token prices are falling, but not fast enough to keep up with the rising token usage; so AI costs will continue to rise sharply on the current trajectory. Little wonder that CFOs and finance departments are sounding alarm bells and beginning to ration AI budgets.Physical AIAI has grown from data analytics to generative AI and is now crossing another frontier by stepping off the computer screen into the physical world. “Physical AI” – intelligent systems like robots, drones, or medical wearables – require fusion of software intelligence with mechanical, electrical, and optical systems like sensors, actuators, cameras, radar, LIDAR etc. Physical AI systems must be autonomous because they cannot rely on data center communication, which adds latency and security risks. So, they must possess “edge intelligence” for real‑time decision‑making to sense, think, and act continuously in the physical world. Each of these functions consumes energy, and an autonomous unit usually operates on a limited battery. Without breakthroughs in energy efficiency, these physical AI systems would either become tethered to power sources or operate with short duty cycles of limited usefulness. The Path ForwardInnovation is the magic wand that can turn these challenges into opportunities. The technology industry excels at innovation, but the spotlight needs to shift from “ever-larger” to “smarter and efficient” systems. Further, point solutions in silos are no longer sufficient – radical efficiency improvement requires system-level optimization of the entire AI stack. Join SEMI’s Smart Data-AI Initiative with our Alliance Partner, City of San Jose, for an insightful workshop on September 9 where we will explore how to bend the curve for energy, cost and performance for future AI computing. We unite leading industry experts across the whole AI ecosystem to see the big picture for future materials, devices, and systems; with deep dives on photonics, hardware-software co-optimization, and chip-to-grid enhancements. This is not yet another AI conference – it is a workshop to explore practical solutions and amplify your business strategy by connecting the dots across the AI stack. You’ll learn about cutting-edge innovations, network with experts, and explore meaningful collaborations.Frequently Asked QuestionsWhy is energy efficiency becoming a strategic priority for AI computing? AI training and inference are driving massive increases in data center energy use, putting pressure on power grids, water resources, and operating budgets. Mitigating the skyrocketing cost for AI users is also a growing strategic priority. Reducing energy consumption directly reduces cost of AI for users, since it implies that AI system capability is being used at maximum efficiency.How are AI tokens connected to rising AI costs?AI providers typically bill usage based on input and output tokens, making tokens a key measure of workload and cost. As daily token consumption grows, total AI spending can rise even if token prices fall, prompting companies to look for more efficient ways to use AI.Why does physical AI make energy efficiency even more important?Physical AI systems such as robots, drones and medical wearables must sense, think, and act in real time, often while running on limited battery power. Without major gains in energy efficiency, these systems could face shorter operating times, reduced usefulness, or dependence on external power sources.How can companies and industry stakeholders help drive innovation in smarter, more efficient systems?Companies and industry stakeholders can engage with SEMI’s Smart Data-AI Initiative by joining workshops, connecting with experts across the AI ecosystem, and participating in discussions on materials, devices, systems, photonics, hardware-software co-optimization, and chip-to-grid innovations. These forums are design to help organizations identify practical solutions, explore meaningful collaborations, and shape a more energy-efficient future for AI computing.Dr. Pushkar P. Apte is Global Lead for Smart Data-AI Initiative Strategic Technology Advisor at SEMI.

The counterfeit semiconductor market is estimated to be multi‑billion‑dollar in scale. OBSIDIA's own customer interviews put the true toll above $100 billion a year, touching everything from foundries losing 5%+ of revenue to counterfeits to failures downstream that cost reputation, business, or lives.As semiconductor devices become increasingly central to artificial intelligence, critical infrastructure, automotive systems, and national security applications, trust in the underlying hardware is emerging as a strategic concern. While the industry has made significant progress in tracking materials, documenting supply chains, and improving cybersecurity, questions remain around authenticity, provenance, and whether organizations can truly trust the devices powering modern technology.To explore these challenges, SEMI’s Mayura Padmanabhan and Nishita Rao spoke with Erik Hosler, Founder and CEO of OBSIDIA Semiconductors Inc, about counterfeit electronics, traceability, trusted hardware, AI infrastructure, and the role industry collaboration can play in securing the semiconductor ecosystem.For readers who may not be familiar with OBSIDIA, what challenge is the company trying to solve?Hosler describes OBSIDIA's mission through a comparison that many technology professionals immediately understand."OBSIDIA is focused on delivering security at the hardware level for the semiconductor industry. A great way to think about that is the analog of antivirus in software." While software has long benefited from tools that help validate and protect systems, he believes the semiconductor industry has lacked an equivalent capability at scale for hardware."Nothing really exists in the semiconductor ecosystem on a large scale for hardware security. The ability to really trust that the semiconductor devices that we rely on every day are authentic and conforming." That gap is what OBSIDIA aims to address. By examining the physical characteristics of devices, the company seeks to verify authenticity at multiple points throughout the semiconductor lifecycle."Through our technology, we're able to authenticate the integrity and quality of devices at any level of integration within the semiconductor supply chain, from the wafer level all the way up to and including the application." This capability was demonstrated as part of a DARPA Small Business Innovation Research (SBIR) Phase II award OBSIDIA completed a few years ago as well as projects with MITRE and Kostas Research Institute for Homeland Security.Why has semiconductor authenticity become such an important issue today?According to Hosler, semiconductor authenticity is no longer a niche concern. As the world becomes increasingly dependent on electronics, the potential impact of counterfeit and non-conforming devices continues to grow."There have been a lot of studies over the past couple of years analyzing how many of these types of devices are actually in our ecosystem. Even at the highest level of scrutiny within the Department of Defense in the U.S., anywhere from 10 to 15 percent of their electronics contain counterfeit devices. That's a very scary statistic."The issue extends beyond critical systems and into everyday life."The chance that you have a counterfeit device in one of your electronics within arm's reach at any point in time during the day is very real." Interestingly, Hosler does not characterize counterfeiting primarily as sophisticated malicious activity."It's not a targeted event. It's a crime of opportunity." He pointed to supply chain disruptions as examples of how legitimate shortages can create openings for non-conforming devices to enter the market."Counterfeits aren't just something bought off the back of a truck. They're sprinkled into our ecosystem and appear seemingly at random." SEMI's Traceability Phase Zero discussions highlighted industry concerns around provenance, authenticity, lifecycle visibility, and supply chain assurance. From your perspective, what are the biggest traceability challenges facing the semiconductor industry today?When discussing traceability, Hosler pointed to a challenge that extends beyond tracking high-value chips themselves."Let's say we have a $30,000 NVIDIA GPU. Tracking that through the supply chain is dollar-for-dollar kind of equivalent to tracking a car through the supply chain. You're going to want to make sure you know where that asset is at any point in time."The challenge begins after that component becomes part of a larger system."Where this paradigm breaks is at integration." Modern electronics consist of hundreds of interconnected components. Even when a high-performance processor has been carefully tracked and validated, a much smaller supporting component can introduce unexpected risk."If one of those five-cent devices on that PCB is counterfeit, it compromises the entire performance of that board, and by extension, that $30,000 GPU." That observation became one of the defining themes of our conversation:“A $30,000 GPU can be compromised by a five-cent component.” For Hosler, true traceability cannot stop at flagship devices. It must extend across entire assemblies and systems.OBSIDIA was recently named among the seven companies signing U.S. CHIPS and Science Act letters of intent for compute supply chain R D. What does this recognition say about the growing importance of hardware trust and security within the semiconductor ecosystem?Hosler views the recognition as evidence that the industry is paying increasing attention to the importance of trusted hardware."What the CHIPS R D money allows us to do is accelerate the commercialization of the technology."He noted that OBSIDIA has already moved beyond the lab and into commercial deployment."We already have a system deployed at a commercial site today. We are in the field running our machine, collecting data with our customer, providing feedback to their customers and suppliers about what's happening in the ecosystem." The funding, he explained, helps accelerate the journey from research to industry adoption while enabling the company to scale its technology across a growing number of use cases.Hosler also contrasted OBSIDIA's approach with current industry practices."If you receive a thousand devices, you typically send three of those devices out for validation at a third-party lab. Then you have to assume the other 997 were authentic."OBSIDIA's vision is to move beyond sampling."What OBSIDIA allows you to do is measure every single device that you receive." By reducing dependence on sample-based validation, organizations gain the opportunity to improve confidence in every component entering their manufacturing process. Many companies already have authentication, tracking, or security technologies. What is still missing to achieve true end-to-end traceability across the semiconductor lifecycle?A recurring theme during industry traceability discussions is the tension between sharing information and protecting intellectual property.Hosler acknowledged that companies are understandably protective of their manufacturing knowledge, process data, and design information."There is a strong desire to control IP, control process data, and control yield data." Rather than attempting to change that reality, OBSIDIA designed its technology around it."So OBSIDIA really looked at its technology and asked how we can be IP and data agnostic." That philosophy led to one of the most memorable statements from the interview:“We're the company that knows nothing.”Hosler explained that customers can maintain existing workflows, processes, and controls without exposing sensitive data."You can maintain whatever structures and regulations and procedures you have already and we will be an addition to that without any need to know anything about what you are doing."By focusing on spectroscopic measurements rather than imaging or design extraction, the company seeks to strengthen trust without requiring access to proprietary information. As AI systems become increasingly important in commercial and national security applications, how does trust in the underlying hardware affect trust in AI itself?Artificial intelligence emerged repeatedly throughout the discussion, particularly as organizations invest heavily in AI infrastructure and advanced computing systems."The AI infrastructure buildout is one of the greatest projects within the U.S. from a manufacturing perspective that has happened in decades." Hosler sees this expansion as both an opportunity and a responsibility for the semiconductor industry."AI is going to be active in the systems that we directly engage with on a daily basis, whether that's the plane you're flying on, or the car you're driving." As AI becomes integrated into transportation, industrial automation, critical infrastructure, and consumer applications, trust in the underlying hardware becomes increasingly important.Drawing a comparison to the evolution of cybersecurity, Hosler believes the industry is approaching an important moment."We don't want to end up with a major incident that we all look back on as a major misstep by us in the industry, just like we saw with cybersecurity." "We are poised for a similar incident when it comes to hardware security." Where do you see the greatest opportunities for progress in the next three years, and how can SEMI help support that progress?Despite the challenges, Hosler remains optimistic about the industry's direction."I think where we are seeing the most progress is the recognition of the problem." He pointed to increasing attention from government, industry, and technology providers as evidence that momentum is building around hardware trust and infrastructure assurance."This is a major opportunity for the industry to rally around that call and deliver a solution that not only covers AI space but covers the rest of our infrastructure as well." Hosler also sees a critical role for standards organizations."SEMI is the perfect place, given that all the partners are already there, all the end customers, all the interested parties." Reflecting on SEMI's Traceability Phase Zero effort, he described it as an important starting point that helped identify both challenges and opportunities."The Phase Zero study was a great first step to realize what the challenges are and what the potential opportunities are. Now a Phase One is required to consolidate the feedback and align on a solution." One trend worth watching going forward: the industry's accelerating shift toward chiplets and multi-vendor advanced packaging means a single finished package can now contain die from several different suppliers, assembled by a third party - a structural change to the supply chain that raises new provenance questions of its own.Closing ThoughtsAt the conclusion of our discussion, Hosler offered a simple piece of advice for organizations focused on quality, trust, and supply chain security:“Be skeptical.” He encouraged leaders to look beyond documentation and assumptions and spend more time understanding what is happening on the factory floor."Even though everything looks okay on the outside, what's happening on the factory floor could be a very different story.""Don't assume everything is okay. Dig that next layer deeper." As semiconductor supply chains become increasingly complex and AI systems become more deeply embedded in everyday life, trust can no longer be viewed solely as a matter of paperwork, compliance, or process. As Hosler emphasized throughout our conversation, building confidence in modern technology ultimately begins with confidence in the hardware itself. About Erik HoslerErik Hosler is Founder of OBSIDIA Semiconductors, a company focused on semiconductor authenticity, hardware trust, and supply chain security through advanced RF-based device verification technologies. OBSIDIA's mission is to enable scalable, non-destructive verification of semiconductor devices across the electronics lifecycle Mayura Padmanabhan is a Technical Project Manager at SEMI, focused on advancing semiconductor cybersecurity, traceability, and supply chain resilience through industry standards and collaborative initiatives. Nishita Rao is Director of Product Marketing at SEMI, leading global marketing initiatives that drive industry engagement, thought leadership, and awareness across the semiconductor value chain.

As semiconductor manufacturing advances through technologies such as advanced packaging, hybrid bonding, and increasingly complex process chemistries, the infrastructure supporting the fab is becoming more critical than ever. Yet many engineers and industry professionals remain unfamiliar with the systems collectively known as the “subfab.”In this blog, SEMI’s Mayura Padmanabhan spoke with Ilya Zabelinsky, founder of the International SubFab Research Labs (ISRL), about the growing importance of subfab infrastructure, the industry’s biggest challenges, and opportunities for collaboration, sustainability, and standards development.Padmanabhan: For readers who may be unfamiliar with the term, what is the subfab and why is it a critical part of semiconductor manufacturing?Zabelinsky: Linguistically, the term subfab refers to something underneath the fab. In many modern semiconductor factories, it is literally the floor below the cleanroom. However, the definition is much broader than a location. The subfab can include spaces below, above, or around the fab, and in some cases even systems located within the cleanroom itself.At its core, the subfab encompasses the equipment, technologies, and systems that support manufacturing. These include vacuum pumps, gas abatement systems, chillers, temperature control systems, chemical and gas distribution systems, and waste management infrastructure. While these systems often operate out of sight, they are essential to enabling the manufacturing processes that occur in the fab.“Subfab is a very broad definition of systems, equipment, technologies, and systems of systems that support manufacturing.”Padmanabhan: What are the most important subfab systems and concepts that every semiconductor professional should understand, even if they don’t work directly in facilities or operations?Zabelinsky: I generally group subfab systems into three major categories. The first includes equipment that is effectively part of the manufacturing tool itself but may be too large, noisy, or vibration-sensitive to sit inside the fab. Examples include vacuum pumps, chillers, heaters, RF generators, and electrical systems. Without these components, many semiconductor tools simply cannot operate.The second category includes systems that supply the process. These are the gas and chemical delivery systems that provide materials used in deposition, etch, lithography, CMP, and other manufacturing processes. Delivering materials at the proper purity, pressure, flow rate, and temperature is essential for yield, process control, and safety. The third category includes systems that remove what manufacturing leaves behind, including exhaust systems, waste streams, abatement systems, and cooling infrastructure. I often compare these systems to the human body’s digestive system. People rarely think about it when everything is functioning properly, but when it stops working, nothing else matters. Subfab systems play a similar role in semiconductor manufacturing. Padmanabhan: You recently delivered the Subfab 101 course in partnership with SEMI University, which sold out. What do you think resonated most with participants?Zabelinsky: Interest in subfab technologies has grown dramatically over the last few years. When I launched the ISRL initiative several years ago, there were very few publicly available resources on the topic. Today, there are more articles, videos, images, and technical discussions available, reflecting a growing awareness of how important these systems are to semiconductor manufacturing.Despite that increased awareness, many professionals still only see a small piece of the overall picture. Engineers may work with a pump, an abatement system, or a facility network without fully understanding how everything connects together. The course helped participants understand the broader ecosystem, including fab layouts, system interactions, technology evolution, and the role that subfab infrastructure plays in enabling manufacturing. For many attendees, it was the first time they could see how all of these systems function as a complete integrated environment.Padmanabhan: As fabs become more advanced, what new challenges are emerging in the subfab? Where do you see the greatest opportunity for improvement?Zabelinsky: One of industry’s biggest challenges is that we still do not fully understand what happens after materials leave the process chamber. While we understand many fundamental principles, there are still significant unknowns related to chemical reactions, particle formation, material behavior, and transport phenomena inside the systems that support semiconductor manufacturing.Without deeper scientific understanding, we often compensate by adding more equipment, consuming more energy, and relying on larger volumes of support resources such as purge gases. The opportunity lies in better understanding the underlying physics and chemistry so we can develop more efficient solutions. At the same time, many subfab systems continue to follow design approaches that were established decades ago. As advanced packaging, hybrid bonding, and new manufacturing techniques become more widespread, the industry has an opportunity to challenge long-standing assumptions and develop entirely new approaches to subfab design.“The first challenge is understanding the physics and chemistry of what the subfab deals with. The second is breaking paradigms and going after new concepts.”Padmanabhan: You founded ISRL to address challenges in this space. What inspired you to start ISRL, and what role does the organization play in advancing subfab knowledge, innovation, and industry collaboration?Zabelinsky: Throughout my career, I saw significant investments made in new transistor architectures, process technologies, materials, and manufacturing equipment. However, comparatively little effort was dedicated to understanding what happens to materials after they leave the process chamber or how those materials should be handled, treated, recycled, or neutralized. As semiconductor processes become more complex, these challenges become increasingly important.That realization led to the creation of the International SubFab Research Labs. The vision is to establish a collaborative environment where universities, chipmakers, equipment suppliers, material providers, and researchers can work together to better understand material behavior and develop next-generation subfab technologies. Ultimately, ISRL aims to provide infrastructure capable of replicating high-volume manufacturing conditions so that new concepts can be researched and validated without disrupting production fabs, where the primary focus must always remain on yield, quality, and output.Padmanabhan: Sustainability is becoming a major priority for semiconductor manufacturing. How can improvements in the subfab help reduce environmental impact while supporting manufacturing growth?Zabelinsky: Sustainability, operational excellence, and manufacturing economics are increasingly interconnected. As advanced semiconductor technologies require more deposition, etch, vacuum, and abatement processes, the supporting infrastructure grows in complexity and resource consumption. Every new node introduces additional demands on energy, gases, heating systems, cooling systems, and environmental controls.One example is nitrogen consumption. Modern fabs use tremendous amounts of nitrogen for purging and dilution, particularly within subfab systems. Producing that nitrogen requires energy-intensive air separation processes, which contributes indirectly to a fab’s environmental footprint. Heating requirements create another challenge. Many process byproducts require elevated temperatures throughout exhaust and handling systems to prevent unwanted deposition. This increases both direct energy consumption and the cooling demand needed to remove that heat from the facility. Improvements in subfab technologies have the potential to reduce energy use, lower emissions, improve resource efficiency, and support sustainable manufacturing growth across the industry.Padmanabhan: If the industry could collaborate on one subfab-related standards initiative, what should it be and how can SEMI help bring the industry together to make it happen?Zabelinsky: One area that stands out is helium leak detection. Today there are often different requirements and specifications depending on the equipment supplier, construction contractor, factory owner, commissioning organization, or semiconductor manufacturer involved. The lack of consistency creates unnecessary complexity and can lead to additional cost, longer implementation timelines, and inconsistent results.Developing a common industry approach would help establish a shared technical language across stakeholders. Standardization would improve consistency, reduce inefficiencies, and provide clearer expectations throughout the supply chain. It is a practical opportunity where industry collaboration could deliver immediate benefits, and SEMI is uniquely positioned to bring together the relevant stakeholders to help make that happen.“We need standards so the industry can talk the same language.”Looking AheadThe subfab may operate behind the scenes, but its impact is central to the future of semiconductor manufacturing. From vacuum and abatement to chemical delivery, waste handling, heat removal, safety, and sustainability, subfab infrastructure is directly tied to fab performance and manufacturing growth.For Ilya Zabelinsky, the path forward is clear: the industry needs focused research, independent infrastructure, and stronger collaboration among fabs, equipment suppliers, material suppliers, universities, and standards organizations. A practical starting point could be the standardization of helium leak detection specifications, an area where SEMI could help bring stakeholders together and enable the industry to speak a common technical language. Mayura Padmanabhan is Technical Program Manager at SEMI.

The SEMI Standards Team activities in Q2 focused on responding to the rapidly evolving needs of the microelectronics industry with critical revisions on key SEMI Standards. SEMI Standard F51, Guide for Elastomeric Sealing Technology, is a foundational standard for choosing and evaluating elastomeric seals. However, today’s manufacturing processes are demanding more seals with stronger chemical compatibility, lower particle and outgassing contribution, and other new and emerging considerations. SEMI is requesting industry feedback on F51 as part of its five-year review process. To participate in the next iteration of SEMI Standard F51, please complete the survey by October 15, 2026.Revisions are also underway for two important SEMI Standards. SEMI Standard E187, Specification for Cybersecurity of Fab Equipment, is currently being updated to include cybersecurity tiers based on application and need. Meanwhile, the revision to SEMI Standard E137, Guide for Final Assembly, Packaging, Transportation, Unpacking, and Relocation of Semiconductor Manufacturing Equipment, focused on an updated protocol that accounts for changes in the equipment handling environment. The revised version of E137, which included a title change, is being prepared for publication. The Korea Standards Team also hosted dedicated trainings for understanding and implementing SEMI S2, Environmental, Health, and Safety Guideline for Semiconductor Manufacturing Equipment. S2 covers the equipment used to manufacture, measure, assemble, and test semiconductor products, and it’s one of SEMI’s most widely referenced standards to date. With several new fabs coming online in 2026, SEMI Standard S2 is critical for establishing safety benchmarks ahead of tool installation. During Q2, the SEMI Water Management Group held a complimentary webinar that outlined its research findings for its two reports: Procedures Guide and Baseline and Water Savings Guide with Maturity Scale, and how the reports work with existing SEMI Standards. Some of these standards include SEMI Standard F98, Guide for Treatment of Reuse Water in Semiconductor Processing, and SEMI Standard F116, Guide for Drain Segregation for Semiconductor Manufacturing Tools to Support Site Water Reuse. The webinar can be accessed for free on demand. In addition, the SEMI Standards Team welcomed four new task forces chartered to respond to shifting industry demands. These task forces include the Flow Limiting Devices Task Force and the S2 Airborne Chemicals Task Force in North America, the Diagnostic Data Acquisition Task Force in China, and finally, the 310mm Square Panel Glass Carrier Task Force in Japan. Lastly, SEMI held 14 technical committee meetings in Q2 throughout Asia and Europe, with more than 20 standards either introduced or revised. To get involved in these SEMI Standards development efforts, become a member of the SEMI Standards Program. Membership is free. Feedback for SEMI Standard F51To adapt F51 to the modern manufacturing environment, the SEMI F51 Revision Task Force recently developed a feedback matrix outlining current priorities for this standard. For those working with elastomeric seals in any of the environments outlined on this webpage, please take a moment to provide additional input on which sealing characteristics, impurity concerns, and handling considerations should be most heavily considered in the revised version of F51. The SEMI F51 Revision Task Force is targeting a first draft by SEMICON West 2026, taking place from October 13-15. To have your feedback considered, please complete this survey by October 15, 2026. Revisions to SEMI Standards E187 and E137SEMI E187, Specification for Cybersecurity of Fab Equipment, is fundamental for outlining cybersecurity protocol for operating systems, network security, endpoint protection, and more. However, cyber threats are quickly evolving, and SEMI E187 will similarly need to be revised to address new and emerging concerns. One important revision to SEMI E187 is the introduction of three cumulative security levels (SLs), which will help equipment users and suppliers to select security profiles based on their needs. SL1 represents baseline compliance, while SL2 introduces stricter standards for equipment with greater exposure to cyber threats, like those with connections over public networks. Finally, SL3 is the most secure level of compliance, intended for applications with extremely sensitive assets to be protected. The revision of SEMI E187 represents an important step toward strengthening cybersecurity resilience across semiconductor manufacturing environments. The task force aims to advance this revision into the balloting stage this year, and continued industry participation will be essential to ensure that the final document reflects practical needs, global alignment, and broad technical consensus.Meanwhile, SEMI Standard E137, Guide for Final Assembly, Packaging, Transportation, Unpacking, and Relocation of Semiconductor Manufacturing Equipment, offers a reference for activities occurring between final assembly and moving equipment into a cleanroom. While today’s iteration covers recommended packing materials and step-by-step instructions for each subsequent process, it doesn’t account for changes in the equipment handling environment. In addition, the new version intends to be easier to understand while providing additional guidance on crating materials for specific circumstances. The revised document officially passed technical review and will be available soon. SEMI Korea S2 Safety Training From June 10-12, the SEMI Korea Standards Team hosted a SEMI Safety Standards training course. Divided into beginner and advanced sessions, the course offered a deeper understanding of safe semiconductor design and equipment evaluation. Held at the Suwon Convention Center in Suwon, Korea, it covered everything from safety standard basics all the way to in-depth explanations and practical implementation strategies for SEMI Standard S2. The June 10 program introduced the basics of SEMI Standard S2, explaining safety interlocks and emergency shutdown protocols, before diving into electrical design, fire protection, ergonomics, chemical, radiation, sound pressure, and more. For those more familiar with SEMI Safety Standards, the advanced course from June 11-12 provided more guidance on the installation of emergency stop and safety devices, chemical safety, machine safety, electrical design safety, and optimal risk assessment techniques. The advanced session went beyond SEMI Standard S2 and covered material related to SEMI Standards S6, S8, S10, S14, S17, and S28.The next SEMI Korea Standards course, SEMI Semiconductor Test Technology Training, will be held on September 9 in person at the same location. Apply today. Water Management Explanatory WebinarIn Q2, the SEMI Water Management Working Group held a webinar outlining its research for the Water Management Strategy Reports and explained how findings interact with SEMI Standards. The webinar covered procedure guidelines, water saving and baseline setting, and the solutions maturity scale. The reports were developed to help improve company water posture through recycling and reclaiming after implementing water saving strategies. They work to go beyond existing standards to help water managers understand water balance and set reasonable goals for new solutions. The reports can be downloaded here free of charge, and the webinar can be viewed on demand. New SEMI Standards Task Forces As the microelectronics industry continues to expand, four new task forces were developed in Q2 to address emerging needs. The Flow Limiting Devices Task Force was established in May 2026 to address issues identified during a reapproval ballot of SEMI S5, as well as other matters related to SEMI Standard S5 that are later identified. This task force is based and operated under the North America (NA) EH S Technical Committee Chapter. The revision to SEMI S5 was issued for ballot in Cycle 6-2026. The ballot results will be reviewed and discussed at the next task force meeting, which will be held in conjunction with SEMICON West 2026 in San Francisco, California.Also created in May, the S2 Airborne Chemicals Task Forcewill modify section 23.5 to require that the assessment criteria be demonstrated, but not necessarily during equipment evaluation. The task force leader believes that an equivalent level of safety can be achieved through alternative assessment methods. For example, industrial hygiene (IH) monitoring could be performed before opening a process chamber while personnel are wearing appropriate personal protective equipment (PPE). The results of the assessment would then determine whether PPE can be removed or should continue to be worn during subsequent work inside the chamber. This task force is based in North America and will fall under the EH S Technical Committee.Based in China, the new Diagnostic Data Acquisition Task Force will investigate problems with the implementation of Equipment Data Acquisition (EDA)/Interface A Standards in the China region and propose suggestions for improvement. This task force will also develop new SEMI Standards for EDA/Interface A and diagnostic applications as needed, in addition to promoting cooperation with other task forces in China involved with EDA/Interface A. This task force was approved in June and will fall under the China Information Control Technical Committee chapter. Finally, in response to a Line-Item Revision ballot for SEMI Standard 3D20, Specification for Panel Characteristics for Panel Level Packaging (PLP) Applications, that is being revised to include smaller panel sizes, the 310mm Square Panel Glass Carrier Task Force was formed on June 5 to revise SEMI Standard 3D23 to also include specifications for 310mm square glass carriers used in panel level packaging. Currently, 3D23 covers 510 x 515mm and 600mm x 600mm panel sizes. In its efforts to expand the standard, the task force will determine the length, width, thickness, and associated tolerances for the 310 mm panel, features like orientation corner and reference edges, backside ID mark location, and other necessary specifications. This task force is based in Japan and falls under the 3D Packaging and Integration Technical Committee. Interested in joining a task force? Apply for SEMI Standards membership.Outcomes from Q2 Technical Committee Chapter Meetings Q2 included several Technical Committee chapter meetings across Asia and Europe, where upcoming ballots and initiatives were discussed. To exchange ideas in real-time, a community page is now available on the Connect@SEMI platform. Japan Meetings The Automation Technology Japan Technical Committee met on June 19 and presented reports from the AI, Surface Mount Technology, and F-GEM task forces. The Information Control Japan Technical Committee convened on June 17 and approved SNARF 7476 , Guide for Maintenance Robot Communication.The 3D Packaging Integration Japan Technical Committee conducted ballot reviews on June 5 for a line-item revision to SEMI Standard G82-1115, Specification for 300 mm Load Port for Frame Cassettes in Backend Process, as well as a line-item revision to SEMI G95-1120, Specification for Mechanical Features of 450 mm Load Port for Tape Frame Cassettes in the Backend Process. The EHS Japan Technical Committee met on June 3 to present several task force reports, including one from the Global Seismic Protection Task Force, another from the Mobile Maintenance Robot Safety Task Force, and several more from various SEMI Standard revision Task Forces. The Gases and Facilities Japan Joint Technical Committee reviewed the revision ballot for SEMI Standard E137-0705 on May 29. The committee approved the revision and a title change. Once published, the Standard will be called Guide for Final Assembly, Packing, Transportation, Unpacking, and Moving of Semiconductor Manufacturing Equipment. The Physical Interface Carriers Japan Technical Committee proposed a new primary standard, Specification for Enhanced Handoff Interface, and a complementary subordinate standard, Specification for Modbus Communication for Enhanced Handoff Interface, on May 21. These documents passed review and are currently being processed for publication.The Liquid Chemicals Japan Technical Committee met on May 21 to present several task force reports, including Liquid Filter Task Force, Liquid-Borne Particle Counter Task Force, and Valve Fitting Task Force. Ballot 7267A, Revision to SEMI C77-0818 with title change to: Test Method for Determining the Counting Efficiency of Liquid-Borne Particle Counters for Which the Minimum Detectable Particle Size is in the Range of 20 nm and 100 nm, was authorized in Cycle 8-2026, which will be issued in late September.The Information Control Japan Technical Committee met on April 17 to report the Ratification Ballot results for Line-Item Revision to SEMI E170-0520, Specification for Secured Foundation of Recipe Management System (SFORMS) and SEMI E170.1-0520, Specification for SECS-II Protocol for Secured Foundation of Recipe Management System. This ballot passed, and both primary and subordinate standards will be available soon. The Silicon Wafer Japan Technical Committee convened on April 17 to review ballot 6570D for a new SEMI Standard, Guide for Measuring Bulk Micro Defect Density and Denuded Zone Width in Annealed Silicon Wafers by a Laser Scattering Tomography Technique. This document passed review and is currently being processed for publication.Korea MeetingsThe EHS Korea Technical Committee also met on June 19 to discuss its Field-Based Safety Subcommittee, Regulatory Alignment Subcommittee, Robot Safety Task Force, and S2 Major Revision Liaison Task Force.The Information Control Korea Technical Committee reviewed reports from the GEM300 Task Force, the Diagnostic Data Acquisition Task Force, and the Advanced Back-End Factory Task Force, on April 23.China MeetingThe Information Control China Technical Committee met on June 2 and approved SNARF 7475, Line Item Revision to E90-1224, Specification for Substrate Tracking and E90.1-1224, Specification for SECS-II Protocol Substrate Tracking. The goal is to help both equipment manufacturers and factories using E90 achieve precise and consistent information exchange regarding substrate state.Taiwan MeetingThe FPD Metrology Taiwan Technical Committee discussed and adjudicated ballot 7352, Revision to SEMI D056-0519, Test Method for Measurement for Ambient Contrast of Flat Panel Displays, which failed technical review, on May 22. The updated ballot 7352A is issued in Cycle 7-26 and is scheduled for review on November 20, 2026.Europe MeetingThe Compound Semiconductor Materials Europe Technical Committee met on April 14. Ballot 7111, Revision of SEMI M81-0418, Guide for Defects Found in Monocrystalline Silicon Carbide Substrates, passed technical review. The revised SEMI M81 standard is being processed for publication and will be available for purchase online.In Case You Missed It – Standards Suite Overview White Paper The SEMI Standards team released a complimentary, 23-page white paper, titled Selecting the Right Standards for Your Factory Use Case and Technology Needs. This paper covers four SEMI Standards Suites to support equipment communications and automation. It breaks possibilities into smaller groups of existing standards to help factories and suppliers scale more efficiently. Download the white paper. New and Revised Standards Released in Q2 April 2026May 2026June 2026Get InvolvedSEMI Standards development activities take place throughout the year in all major manufacturing regions. To participate, join the SEMI International Standards Program.SEMI Standards are available through individual download purchases or online via SEMIViews. Watch this video to learn more about how SEMIViews offers a cost-effective and streamlined way to access 1,110+ SEMI Standards. Sign up for a 30-day SEMIViews trial.For more information, please visit the Standards website and events page. For any questions regarding SEMI Standards activities, please contact your local SEMI Standards staff.Paul Trio is Director of Standards at SEMI.

SEMI’s annual Surface Preparation Cleaning Conference (SPCC) brought industry experts to Chandler, Arizona, to address the biggest challenges affecting this area of the semiconductor industry. As the premier technical forum dedicated to advancing surface preparation, cleaning technologies, and wet processes, the conference featured dozens of speakers who shared insights on the current market, emphasizing key themes like advanced packaging, power delivery, advanced DRAM, sustainability, and more.Ahead of this year’s conference, SEMI and Global Net Corp. (GNC) developed a new report, Glass Core Substrate Market and Development Trends, examining manufacturing challenges, supply chain structure, and market outlooks through 2040. This resource helps organizations evaluate the glass core substrate landscape before committing to production. A sample of the report is available for complimentary download. High-Level Updates and SEMI Insights Joe Stockunas, president of SEMI Americas, kicked off SPCC 2026 by announcing that the industry is entering its biggest era yet, on pace to reach $1 trillion in annual revenue in 2026 – 4 years ahead of prior forecast. The semiconductor industry has become the third most valuable global industry with top companies' market capitalization surging over the past decade. By 2030, industry analysts expect annual revenue to soar to $1.9 trillion, driven largely by demand for AI infrastructure, with logic and micro capacity also expected to nearly double. However, Stockunas also noted headwinds including geopolitical tensions and a growing talent shortage.Duncan Meldrum from Hilltop Economics offered a cautionary macroeconomic view, warning that AI growth is now concentrated among a handful of hyperscalers and leading-edge chipmakers, creating concentration risk. Geopolitically driven inflation is squeezing consumers, while supply chain disruptions are impacting critical materials like sulfuric acid, helium, and tungsten. Meldrum also highlighted concentration risk in production, with a few ODMs and manufacturers dominating the AI server market.SEMI analyst Inna Skvortsova provided materials market updates, emphasizing that advanced devices are driving materials intensity per wafer. Lithography, wet chemicals, and CMP are already seeing double-digit growth, led by increasing number of processing steps, rising count of EUV layers, and tightening CMP process windows at advanced nodes. Deposition materials were noted as another fast-growing segment that is forecast to grow at a 13.5% CAGR through 2030, driven by molybdenum adoption and backside power networks. Furthermore, introduction of new materials, including Ruthenium and Tungsten Carbon Nitrite (WCN) hardmasks, brings new opportunities and challenges with regards to wet processes.On memory, Skvortsova confirmed that AI pull has made memory a compute-stack bottleneck, driving capital toward leading-edge logic and HBM. Logic and micro capacity nearly doubles by 2030, but growth is highly concentrated in advanced nodes (≤7nm) pressuring non-AI segments.Skvortsova also highlighted a supply chain shift from globalization to localized production networks, with China emerging as a significant player in areas like bulk wet chemicals, gases, and deposition materials. While alternative sources are emerging, supplier re-qualification may result in higher material costs.Theme 1 - Hybrid Bonding FluxSPCC 2026 highlighted cleaning innovations for hybrid bonding, a core technology enabling AI scaling and glass core substrates. Srini Raghavan (ProSys) presented a paper based on the collaborative work between Intel and ProSys in the area of megasonic removal of flux from narrow gaps in advanced packaging structures. His team found that application of 10 msec pulses of 925 kHz sound wave at 90% duty cycle was very effective in flux removal in a semi-aqueous formulation Acoustic streaming rather than cavitation appears to be the primary cleaning mechanism under the test conditions.Koji Nakata (Kurita Industries) tackled particle contamination, copper corrosion, and chemical consumption in 3D stacking. His solutions include:Functional water + megasonic cleaning for higher particle removal than SC-1.Alkaline water rinsing to reduce copper pad recessing vs. DI water.Functional water to lower chemical consumption, cost, and environmental impact.Theme 2 – Wet Etch, Gate-All-Around, SelectivityTwo presentations highlighted next-gen logic wet etch challenges. IBM's Alma Vela Ramirez showed that an oxide-selective wet chemistry reduced buried void defects by over 20× during dummy gate polysilicon removal in GAA nanosheet flows. From her findings, chemistry 1 showed higher defectivity, while chemistry 2, selective to gate oxide and compatible with spacers, drastically reduced void formation by preserving the bottom oxide layer.Mitsubishi Chemical Corporation’s Tomoki Nara demonstrated a Si/SiGe selective etchant achieving a record 750:1 selectivity, critical for protecting thin SiGe layers during Si thinning in backside power delivery networks (BSPDN). His new alkaline wet etchant and single-wafer spin process address conventional etchants' inability to stop cleanly on SiGe, significantly expanding the process window during Si thinning and reducing the risk of SiGe damage.Theme 3 – Scaling DRAM to Advanced NodesMicron presented two DRAM manufacturing breakthroughs. Shihui (Adara) Yang introduced a dilute sulfuric peroxide clean achieving 3.59× BCF:TCF (bottom container fill and top container fill) selectivity—solving uniformity issues where conventional fluorine-based chemistries etch both layers at similar rates, causing container shorts and yield loss at advanced nodes.Hiroki Uoyama introduced a wafer backside polishing brush incorporating diamond or silicon carbide, achieving over 90% defect height reduction with no wafer thickness loss. This physical cleaning approach improves focus control, alignment accuracy, and overall yield — critical as lithography margins narrow dramatically at smaller nodes.Theme 4 – Sustainable Materials Stripping Solutions Sustainability was another core focus at SPCC 2026, with three distinct approaches taking center stage — each addressing a different facet of environmental impact in the fab.PFAS are among the major pollutants in semiconductor manufacturing waste streams, whose separation and destruction are challenging. As demonstrated by imec’s Sina Kaabipour, representing the collaborative research work between imec, Purdue University, and Enspired Solutions, UV destruction can achieve more than 99% PFAS destruction efficiency for simulated semiconductor manufacturing waste, showcasing great potential for scale-up and direct mineralization from liquid fab waste effluents.Diane Bijou from Technic launched TechniStrip® Micro 680, an NMP-free stripper with sub-2-minute stripping time, better loading capacity, extended bath life, and lower cost per wafer than NMP/amine-based strippers.Chihiro Kobata of JSR unveiled a water-rich stripper removing both photoresist and spin-on glass without NMP, DMSO, and TMAH, at lower temperatures (40–60°C), with ECO conscious, high performance, and high material compatibility and fab-part compatibility.Connect With SEMI SEMI would like to thank all speakers, sponsors, and attendees for the success of SPCC 2026. Download a preview of SEMI and GNC’s new report, Glass Core Substrate Market and Development Trends, and stay connected with SEMI on LinkedIn and X. Clark Tseng is Senior Director of Market Intelligence at SEMI.

The SEMI Smart Manufacturing Initiative is a global effort focused on leveraging the most advanced technology to enhance productivity of electronics manufacturing facilities. Among the key technology advances this group seeks to promote is the value of implementing Industry 4.0/5.0 technology to deliver increased return-on-investment (ROI). A recent white paper published by the initiative focused on the productivity improvements that can be achieved by the formation of digital twins in semiconductor plants [1]; however, sustainability was not the focus, providing an opportunity for future pre-competitive work.To address this, the SEMI Smart Manufacturing Initiative formed the Accelerating Sustainability with Smart Manufacturing task force in 2023 to benchmark industry best practices that enable manufacturing facilities to meet their sustainability goals faster. The roadmap would complement the SEMI Sustainability Initiative by following a bottom-up approach to identifying the industry’s best practices. The task force primarily focused on fab device production, which is widely seen as the largest driver of the microelectronics industry’s Scope 1–2 emissions, water use and hazardous waste consumption, versus other branches of the supply chain.This task force developed a comprehensive solutions-based Scope 1 (process-based, direct) and Scope 2 (energy-based, indirect) emissions roadmap, incorporating the Connecting, Sensing and Predicting pillars developed by the Smart Manufacturing Initiative [2], and applied them at cleanroom, subfab and facilities levels for brownfield device-making facilities. While these phases are meant to be cumulative for maximum impact on targeted sustainability metrics, the SEMI task force understands that not every fab that applies the roadmap as a tool for sustainability purposes will advance use cases all the way to the Predicting phase. Moreover, special use cases are defined for greenfield fabs in a separate section of the roadmap, covering new infrastructure and more disruptive changes to existing operations to guide streamlined deployment. These key features are the foundation used to develop the first half of the roadmap for addressing Scope 1 and 2 emissions, leveraging Industry 4.0/5.0 technology, and published as a collaborative SEMI white paper [2]. The second half of the roadmap presented at SEMICON West 2025 [3] is covered in this latest white paper [4] and follows the same methodology though focused on reducing water consumption and hazardous waste in device-making fabs. Altogether, both SEMI white papers comprise the first comprehensive semiconductor industry roadmap covering carbon emissions, water and hazardous waste, while emphasizing the benefits of smart technology. The roadmap numerically rates each innovative use case in terms of relative impact on reducing a fab baseline void of smart elements and based on technology readiness level (TRL) with respect to future production capability. This functional roadmap will be available soon to the industry as a customizable model, denoted as the SEMI Smart Sustainability Model (SSM), wherein users can estimate sustainability gains by applying some or all listed use cases based on the nature of the facility’s sustainability profile and goals (i.e. relative proportion of water consumption sources at all levels of their operation, by adjusting weighted impact factors in the model). A base case assessment of proportional resource consumption representing an industry average 300mm fab, based on published data and task force estimates, is provided for fabs without detailed tracking to constitute the SEMI Smart Sustainability Roadmap.Many sustainability organizations across the semiconductor industry are focused on problem-based assessments which often highlight water scarcity or total industry carbon footprint growth and this can lead to IDMs, foundries, OSATs and others in the supply chain tackling sustainability from an isolated, project-based perspective. Moreover, a top-down approach to sustainability in fabs does not scale as well as a bottom-up approach to counteract the issue of increasing device process complexity and the larger associated process flow, requiring a higher amount of carbon emissions, water and hazardous waste, which needs to be addressed. For instance, a purchase power agreement for renewable energy is determined based on a finite amount of expected fab energy usage. However, energy-efficiency aided by AI across all levels of the fab is much more scalable, as a fab expands or additional process steps are added per product. Therefore, a data-driven approach, tracking emissions, water, and waste and linking technologies to future targets, is most effective, making this roadmap unique in scope and approach. A unified fab-wide data platform leveraging digital twins can further improve outcomes by linking water and waste metrics with downstream KPIs like recycling rates.The roadmap’s best practices can apply to any device-making fab, as it relies on Industry 4.0/5.0 technologies rather than compromising process flows as in alternative fab sustainability models. ROI benefits identified include cost-savings on process materials, utilities, regulatory, and labor plus higher yield and shorter cycle time after implementation. In summary, the use cases within the customizable model are quantified based on normalized impact to the current baseline level so that device-makers can benchmark themselves and prioritize investment in the most effective technologies to meet their sustainability goals.For future updates on the SEMI Smart Manufacturing Initiative, including the upcoming SSM product release, please visit the Initiative's website. To learn more about the roadmap, download prior white papers: White Paper 1: Accelerating Sustainability with SEMI Smart Manufacturing White Paper 2: Accelerating Sustainability with SEMI Smart Manufacturing: AI Roadmap for Device Makers Part II References:[1] M. da Silva and K. Somani, "Digital Twins in Semiconductor Manufacturing," SEMI, Milpitas, CA, 2024.[2] B. Coppa, A. Srivastava and M. da Silva, "Accelerating Sustainability with Smart Manufacturing: Roadmap for Device Makers," SEMI white paper (Available here) - November 2024.[3] B. Coppa, A. Srivastava, “SEMI Smart Sustainability Roadmap Part II: AI Blueprint for Device Makers,” at SEMICON West, October 2025.[4] B. Coppa A. Srivastava, “Accelerating Sustainability with Smart Manufacturing: AI Roadmap for Device Makers Part II” SEMI white paper (Available here) – May 2026 Brian J. Coppa, Ph.D., is Product Engineering Lead at ULVAC. Amit Srivastava is Staff Program Manager – Smart Manufacturing AI at Micron. Mark da Silva, Ph.D., is Senior Director, Manufacturing Coalitions at SEMI. Anshu Bahadur is Senior Program Manager, Technology Coalitions at SEMI.

For years, cybersecurity in manufacturing was often treated as a mere compliance issue. Suppliers filled out questionnaires. A scan report was produced before shipment. A checklist was reviewed during qualification. A document proved that the equipment was "secure enough" at a given point in time. This model is no longer sufficient. As equipment becomes more software-driven, connected, and remotely maintained, cybersecurity responsibility is moving closer to the product itself and therefore closer to the OEM. Fabs still define their security expectations, but OEMs are increasingly expected to provide evidence that their equipment can remain secure throughout its lifecycle.Semiconductor manufacturing is entering a new phase of cybersecurity. The question is no longer simply, "Was this equipment compliant when it was delivered?" A stronger question is emerging: "Can this equipment continuously demonstrate that it is operating securely and reliably?" This shift matters because semiconductor equipment is no longer isolated machinery. It is software-intensive, networked, remotely maintained, data-producing, and deeply integrated into fab operations. Equipment controllers, factory interfaces, service laptops, recipes, logs, remote access tools, operating systems, middleware, and data acquisition services now comprise a significant digital presence surrounding the physical process. The risk is not theoretical. Industrial automation and control systems are now considered cybersecurity assets throughout their lifecycle rather than merely engineering systems. In the global semiconductor manufacturing industry, this shift is evident through the following SEMI standards:SEMI E169 provides guidance for equipment information system security. SEMI E187 defines cybersecurity requirements for fab equipment.SEMI E191 addresses cybersecurity status reporting for computing devices connected to the factory network.These semiconductor-specific standards align with the broader industrial cybersecurity trend. The ISA/IEC 62443 series addresses cybersecurity throughout the industrial automation lifecycle, including product development, integration, operation, maintenance, and supplier responsibility. The National Institute of Standards and Technology (NIST) has moved in the same direction with Cybersecurity Framework 2.0 by adding "govern" as a core function and making cybersecurity the responsibility of leadership, risk management, and the supply chain rather than just a technical activity.In Europe, this shift is also becoming regulatory. Under the Cyber Resilience Act, starting September 11, 2026, manufacturers will be required to actively report vulnerabilities and severe incidents affecting products with digital elements. They must provide an early warning within 24 hours and a full notification within 72 hours. This will encourage many industrial suppliers to strengthen their vulnerability management.A fab does not only need to know that an equipment was shipped with a supported operating system. It also needs to know if the system remains aligned with the approved configuration after installation, maintenance, remote support, patches, upgrades, troubleshooting, and years of production use.A fab needs more than a document saying that network security was considered. It needs practical evidence showing which ports are open, which services are active, which accounts exist, which software is running, and whether local protection mechanisms are still enabled. A fab does not only need supplier declarations. It needs operational proof.This is where the semiconductor industry faces a specific challenge. A fab cannot simply copy standard IT cybersecurity practices and apply them directly to production tools. The cost of disruption is too high. A patch that is harmless in an office system may affect equipment behavior, timing, qualification, or process stability. A security scan that is acceptable in IT may be intrusive in a production environment. Generic endpoint controls can create unacceptable side effects if they interfere with motion, recipes, automation, or equipment availability.Therefore, semiconductor cybersecurity must balance three constraints simultaneously:Protect the equipment and the factory network.Preserve deterministic production behavior.Generate evidence that can be trusted by fabs, suppliers, auditors, and increasingly, regulators.For this reason, the future of cybersecurity in semiconductor manufacturing will likely be built around five practical pillars.1. Secure by design, but validated in operationSecurity measures must be implemented from the outset of equipment architecture. The product baseline should include supported operating systems, hardened configurations, secure communication channels, access control, logging, and vulnerability handling. Figure 1: Equipment controllers expose trusted security context However, design is only the starting point. The equipment must also support validation after delivery. Fabs need a way to confirm that the deployed configuration still matches the secure baseline. This is especially important after field service, software updates, recipe changes, local troubleshooting, or remote maintenance. The industry is shifting from "trust me, it was secure at release" to "here is the evidence that it is still secure today."2. Cybersecurity evidence must become structured dataAll too often, cybersecurity evidence remains trapped in PDFs, spreadsheets, emails, and manual audit reports. This approach is not scalable. A modern factory needs structured, machine-readable cybersecurity information. This data does not need to be collected at the same frequency as process data, it should rather be collected at the right frequency for assurance, such as daily, weekly, after a restart or maintenance, or before a production release.This creates a strong opportunity for equipment manufacturers. The equipment controller can serve as a source of trusted security context. It can provide controlled, well-defined information about the current state of the equipment's software and configuration. This does not replace cybersecurity tools. Rather, it complements them with equipment-native context.This is important because the equipment itself knows things that external tools may not: which services are expected, which processes are part of the controller, which ports are required for automation, which accounts are intended for servicing, and which configuration belongs to the validated release.3. Communication security must move closer to the protocol layerMany industrial environments have relied on network segmentation, virtual private networks (VPNs), and perimeter controls. While these controls remain useful, they are insufficient for a Zero Trust approach.The next step is establishing stronger identities and trust between communicating systems. When equipment and factory systems exchange messages, they must know with whom they are communicating, and the communication channel must protect the confidentiality and integrity of the messages.This direction already exists in part of the semiconductor communication landscape. In EDA, also known as Interface A, SEMI E132 defines equipment client authentication and authorization, requiring clients to authenticate before further communication and enabling authorization controls for access to equipment functions and data.The same trust expectation is now emerging more visibly for SECS/GEM communication. A SEMI task force is working to secure HSMS communication, which is central to SECS/GEM-based host-equipment integration. The objective is to improve trust at the communication layer while preserving the proven behavior and interoperability that made HSMS successful in fabs.For semiconductor manufacturing, this must be done carefully. The industry cannot disrupt decades of host-equipment interoperability. The practical approach is to secure communication while maintaining existing automation behavior. This is a good example of the semiconductor cybersecurity challenge: modernizing the trust model without destabilizing the production model.4. Cybersecurity must be lifecycle-managedA semiconductor tool can remain in operation for many years. During that time, operating systems age, third-party components evolve, vulnerabilities are discovered, remote support practices change, and fab expectations become stricter. This means cybersecurity cannot be treated as a delivery milestone. It must be managed as a lifecycle capability, from design and release to installation, maintenance, upgrades, and end-of-support planning.For semiconductor OEMs, this creates a very practical challenge. They need clearer answers to questions that fabs will increasingly ask:Practical questionWhy it mattersWhat is the support status of each software component?To understand exposure to known vulnerabilities and end-of-support riskHow are vulnerabilities evaluated?To separate theoretical exposure from real equipment riskHow are patches qualified without creating regression risk?To protect cybersecurity without compromising process stability or tool availabilityHow is the customer informed?To support faster risk decisions and stronger supplier trustWhat is the fallback if a patch cannot be deployed?To define compensating measures and avoid unmanaged riskHow is the secure baseline restored after maintenance?To prevent configuration drift after service actionsHow is evidence retained?To support audits, incident response, and lifecycle traceability The answer is not simply more documentation. The answer is better evidence: structured, repeatable, and linked to the real equipment state. For semiconductor OEMs, the practical task is to convert cybersecurity requirements into evidence that fabs can verify during integration, operation, maintenance, and upgrades.Evidence categoryWhat the fab needs to knowWhy it mattersOS and software baselineSupported OS, installed components, patch statusReduces exposure to known vulnerabilitiesNetwork exposureOpen ports, active services, remote connectionsHelps detect unexpected attack surfacesAccess controlLocal accounts, roles, privilege modelLimits persistence and unauthorized accessEndpoint protectionFirewall, anti-malware, hardening statusConfirms local defenses remain activeLogs and monitoringSecurity events, configuration changes, authentication eventsSupports investigation and traceabilityMaintenance historyUpdates, remote sessions, service actionsShows what changed and whenVulnerability handlingKnown vulnerabilities, mitigation status, patch planSupports lifecycle accountability This lifecycle view is important because every change can modify the equipment security posture. A patch, a remote support session, a local service action, a new account, an opened port, or a firmware update can all move the tool away from its validated baseline. Figure 2: Cybersecurity becomes a lifecycle process This is also where upcoming regulations will change the supplier conversation. Vulnerability handling, reporting, and product security documentation will become part of business trust, not only technical trust. For semiconductor OEMs, the direction is clear: cybersecurity evidence must become part of the product lifecycle, not a separate compliance package prepared only when the customer asks for it.5. Compliance must be risk-based, not tool-prescriptiveOne of the important lessons from industrial cybersecurity is that standards and customer requirements are most effective when they specify the necessary capabilities and evidence rather than forcing every supplier to use the same tools or implementation methods. In the semiconductor industry, the SEMI Standardized Semiconductor Cyber Assessment (SSCA) is a useful example of this direction. It provides a semiconductor-specific assessment framework designed to evaluate cyber readiness and risk across the supply chain, from device manufacturers to OEMs and beyond. It also uses maturity-based questions to help assess the security posture of an organization, which supports a more risk-based view of cybersecurity capability rather than a simple pass/fail interpretation.This risk-based and maturity-based approach is also important at the equipment level. Semiconductor tools are not uniform products with identical architectures. A metrology tool, a sorter, an inspection system, an etcher, and an AMHS component may have different risk profiles, software stacks, connectivity models, and operational constraints. Even within one piece of equipment, cybersecurity responsibility is distributed across multiple layers: the main equipment controller, load ports, robots, sensors, embedded PCs, software libraries, remote access components, and third-party subsystems. The right question is not: "Did every OEM use the same scanner, report format, or internal process?" A better question is, "Can each OEM demonstrate that the equipment meets the required cybersecurity outcome, that the evidence is repeatable, and that the lifecycle process is controlled?"This question must also be addressed recursively across the supplier chain. A fab will ask the OEM for evidence. The OEM, in turn, must obtain and manage evidence from its subsystem suppliers. Those suppliers may need evidence from their own module, software, firmware, and component suppliers. In practice, cybersecurity assurance becomes a chain of trust that runs from the fab down to the lowest relevant technical layer. Figure 3: Cybersecurity assurance becomes a chain of trust The strategic direction is clear for semiconductor OEMs. Cybersecurity should be part of the equipment's value proposition. A secure equipment controller will execute more than just automation logic. It will also support secure communication, controlled access, structured logs, lifecycle traceability, vulnerability management, configuration evidence, and visibility into the security state.This is not just about reducing cyber risk. It is also about reducing integration friction with advanced fabs. It is about conducting audits more quickly. It is about limiting late-stage surprises. It is about giving customers confidence that they can operate, maintain, and upgrade the equipment without compromising factory security.The semiconductor industry is entering a phase in which cybersecurity will be judged less by static declarations and more by operational proof. That is a healthier model. Static compliance tells a fab what was once true. Operational proof shows what is true now. For semiconductor manufacturing, this distinction will become more crucial.About Dr. Fahad GolraAs Director of Product Innovation for Agileo Automation, Dr. Fahad Golra drives next-generation solutions in connectivity, data modeling, and communication architectures. Since joining the company in 2019, he has been a key force behind Agileo’s push toward Industry 4.0, championing interoperability, digital twins, and edge-to-cloud systems. With 15 years of experience spanning academia, research, and industry, Fahad brings deep technical insight and thought leadership to the semiconductor industry. An active contributor to SEMI, the Semiconductor Manufacturing Cybersecurity Consortium (SMCC) and the OPC Foundation, he is a frequent speaker at industry events and a published author advancing the dialogue around smart manufacturing and automation.

As artificial intelligence (AI) workloads surge and hyperscale data centers expand, the semiconductor industry is confronting fundamental limits in electrical interconnects. Co-packaged optics (CPO) is emerging as a pivotal architectural shift, bringing optical connectivity closer to compute to deliver the bandwidth, latency, and energy efficiency required for next-generation systems. However, while the strategic value of integrated photonics is widely recognized, the transition from research to scalable manufacturing remains one of the industry’s most pressing challenges.At the heart of this transition are a range of process considerations that, while familiar, are fundamentally different for photonics than for traditional semiconductor manufacturing. In many cases, the underlying requirements mirror those of CMOS manufacturing—cleanliness, uniformity, and defect control—though often at a different scale and level of maturity. However, the introduction of heterogeneous materials, new device structures, and optical performance sensitivities adds layers of complexity that must be addressed to achieve consistent, high-yield production.The expanding role of wet processingWet processing plays a critical role in several key stages of photonic device fabrication, including cleaning, etching, and drying. These steps directly impact surface quality, defectivity, and, ultimately, optical performance.Critical considerations include:Etch uniformity, essential for maintaining consistent optical pathways and minimizing signal loss;Particle control, as even small contaminants can scatter light and degrade performance; and Drying processes, where residues, watermarking, or contact-related defects can impact yield and reliability.Drying, in particular, has emerged as a significant challenge. Techniques such as nitrogen blow-off or chemical vapor drying are being refined to address issues like residual marks or contamination. In some cases, additional process enhancements—such as sonic energy—are being explored to further improve particle removal and surface integrity.Increasingly, tighter control of process chemistries and concentrations is required to minimize residues and improve particle performance. As these requirements tighten, the industry is recognizing that wet processing is not just a supporting step, but a critical determinant of device performance.At the same time, photonics manufacturing introduces variability that is less common in high-volume CMOS environments. Differences in wafer size, material composition, and process flows demand a higher degree of flexibility. In many cases, both batch-style wet benches and single-wafer processing approaches are used, depending on the application. Equipment and processes must often be adapted—through changes in wafer handling, fluid delivery, or process parameters—to accommodate these variations. In some cases, hybrid approaches that combine immersion and spin-based processing are being adopted to support a broader range of process steps within a single workflow.Scaling for yield and manufacturabilityThroughput, while important, is not yet the primary constraint. The industry’s immediate focus is on achieving stable, repeatable processes that support high yield and consistent performance. Over time, as designs mature and volumes increase, throughput expectations will increase significantly, with industry targets moving toward several hundred wafers per hour.Another important consideration is how photonics capabilities are integrated into existing fabrication environments. Contrary to some expectations, this integration does not always require wholesale changes to fab infrastructure. In practice, integration challenges are often less significant than anticipated and are typically addressed through targeted engineering adjustments rather than fundamental infrastructure changes. This approach minimizes disruption while enabling manufacturers to extend their capabilities into new application domains.Yield remains a central concern throughout this transition. As with any emerging technology, variability in early-stage manufacturing can create cost and reliability challenges. Reprocessing is particularly undesirable in photonics, where complex material systems and tight performance requirements make defects difficult and expensive to correct. Achieving high yield, therefore, depends on precise control across all process steps, from chemical concentration management to particle mitigation and surface preparation.At the same time, the cost of ownership must be carefully managed. While photonics manufacturing may not yet demand the extreme throughput of advanced logic production, it must still be economically viable at scale. This creates a dual imperative: to optimize processes for yield and performance while maintaining the flexibility needed to adapt to evolving designs and standards.Sustainability and the path to adoptionSustainability is also becoming an increasingly important dimension of photonics manufacturing. Although optoelectronic technologies can deliver system-level energy efficiency benefits, their fabrication still relies on water, chemicals, and energy-intensive processes. As a result, the industry is beginning to apply lessons learned from CMOS manufacturing to improve environmental performance. This includes exploring alternative chemistries, particularly as regulatory pressures drive the reduction or elimination of substances such as per- and polyfluoroalkyl substances (PFAS), and aligning with established environmental, health, and safety frameworks.More broadly, the evolution of co-packaged optics highlights a familiar pattern in semiconductor innovation: the need to bridge the gap between laboratory breakthroughs and high-volume manufacturing. Standards are still maturing, design approaches continue to evolve, and early implementations may give way to new architectures. In this environment, flexibility and adaptability are critical—not only in device design, but across the manufacturing ecosystem.Demand signals, however, are unmistakable. AI-driven data center growth is accelerating the need for more efficient interconnect technologies, and photonics is widely expected to play a central role in meeting this demand. As more fabs invest in photonics capabilities, the focus will increasingly shift from feasibility to scalability—from demonstrating what is possible to delivering it reliably and cost-effectively.Wet processing, though often viewed as a supporting function, is deeply embedded in this transition. Its influence on cleanliness, uniformity, and defect control makes it a key enabler of photonic device performance and manufacturability. As the industry continues to refine processes and align standards, advances in wet processing will help define how quickly and effectively co-packaged optics moves into the mainstream.For SEMI members navigating this shift, the implications are clear. Success in photonics manufacturing will depend not only on innovation at the device level, but on the ability to translate that innovation into robust, scalable processes. In that effort, the fundamentals—precision, control, and adaptability—remain as important as ever.Dr. Ismail Kashkoush is Chief Technology Officer for JST, based in Meridian, Idaho. With more than 30 years of expertise in the semiconductor industry, he leads JST’s engineering, technology, and product lines teams to develop the next generation of sustainable surface preparation products and processes. Dr. Kashkoush earned his Ph.D. in engineering science from Clarkson University. Prior to joining JST, he served as CTO at Akrion Technologies Inc. He has a large patent portfolio and continues to contribute technical publications and seminars on wafer surface preparation technology for the IC, MEMS, flat panel display, and photovoltaics sectors.

Artificial intelligence (AI) is scaling at a pace that is reshaping semiconductor roadmaps, data center design, and long-term infrastructure strategy. AI promises many economic and social benefits; but the growth comes with an escalating demand for power, and energy has emerged as a major challenge.SEMI, as the global semiconductor and electronics association connecting over 4,000 companies, continues to unite the entire ecosystem to “bend the curve” – to maximize AI performance while minimizing power consumption. In a series of successful, sold-out workshops that the SEMI Smart Data-AI Initiative held on this topic, a resonant theme has emerged: sustaining AI progress requires energy-efficient computing with holistic co-design and co-optimization across materials, devices, systems, data transmission, data centers, emerging architectures and software. While this dialog is an important starting point, the ultimate goal is to drive concrete action through collaborative innovation.The AI Energy ChallengeAI training compute for frontier models is growing at an estimated 4–5x per year, driving unprecedented demand for hardware capability and infrastructure capacity. That trajectory has resulted in a global “data center gold rush” and is testing energy availability limits. As model sizes scale exponentially, so too does the energy required to train and deploy them; and power consumption has become a significant limiter to performance gains. Further, this increases heat dissipation, and requires innovations like direct liquid cooling.Modern AI and high-performance computing systems now operate at levels comparable to small cities, with tens of megawatts per installation and a trajectory toward gigawatt-scale data center campuses. Grid capacity—both in the U.S. and globally—may be challenged to keep pace with projected demand. Thus, AI infrastructure is no longer just a technical challenge, but it is an energy, systems, and policy challenge.System-Technology Co-OptimizationContinuous advances in chip and inference efficiency have delivered orders-of-magnitude improvements over many decades. These gains must now be expanded by holistic co-optimization of the entire compute system from silicon technologies to data center to the grid.For example, processors can be made more efficient by customizing them for specific workloads. However, only part of total data center power is consumed by the processor itself. A significant portion is used by data movement, power conversion and cooling. The energy required to move data increases dramatically with distance. Moving bits across packages, boards, and networks can consume far more energy than the compute operations themselves. This makes locality a critical design principle. The opportunity—and necessity—therefore lies in cross-layer optimization: efficient compute, efficient communication, and intelligent power management across the entire system. Not surprisingly, advanced packaging and integration are becoming central to performance. These technologies can enable architectures that tightly couple compute, memory, and I/O—using 2.5D and 3D integration techniques—reducing energy per bit and increasing bandwidth. Photonic interconnects and low-power materials can further lower the cost of processing and moving data.The bottom line is that incremental chip-level gains alone will not be sufficient and energy optimization cannot be siloed—system-technology co-optimization is needed.Hardware-Software Co-optimizationKeeping data as localized as possible depends as much on software algorithms as it does on hardware architectures. The challenge is that the development cycles are mismatched: new software models can be developed in months, while designing and fabricating new hardware can take years. While this cycle mismatch is fundamental, closer coordination between hardware and software developers can significantly improve efficiency. For example, offloading selected functions in the algorithm, including distributed DPUs, and reducing the level of data precision can reduce energy use. Partitioning workloads logically across the hardware/software stack between cloud services and compute-on-edge can also reduce energy appreciably. Further, risk mitigation techniques—for example, building in strategic redundancy—can make future designs more resilient to shifts in software algorithms and models.Diverse Computing ModalitiesWhile AI dominates current infrastructure investment, the future of computing will likely include multiple, diverse computational modalities such as quantum, neuromorphic, photonic and analog computing.Different computational paradigms will be applied where they are most effective. For example, quantum computing is likely to complement—not replace—classical systems; especially for specific classes of problems where it offers exponential advantages. However, progress in quantum computing is tightly coupled to advances in semiconductor infrastructure. Error correction, orchestration, and hybrid algorithms all depend on high-performance classical systems operating with low latency alongside quantum processors. While there is no single silver bullet, system-level design can ensure that multiple computing modalities work together within unified workflows spanning edge, cloud, and exascale environments.Why It Matters What to WatchEnergy will now be a key constraint for AI performance and infrastructure expansion.The evolution of gigawatt-scale AI campuses and their interaction with public energy grids will accelerate – or slow down – AI growth.Data movement, memory bandwidth, interconnect efficiency, advanced packaging and heterogeneous integration will be strategic levers. Enhanced system-technology co-optimization and integration of advanced technologies like 3D ICs and photonics will be critical.Co-optimization across hardware, software, and systems will be required.Future architectures will blend classical and emerging compute modalities like quantum, photonic and neuromorphic.In conclusion, AI has become a defining global force with much promise, but its trajectory will be shaped by technology, energy and infrastructure economics working together. This is a formidable challenge because it requires many diverse players with divergent priorities to collaborate effectively.We invite you to join the SEMI Smart Data-AI initiative to collaboratively address this challenge and help realize AI’s full potential sustainably. Our next workshop in this series will be on September 9 in Silicon Valley – please join us for this exciting event.SourcesSEMI Smart Data-AI Initiative – Future of ComputingEnergy-Efficient Computing for AI and Beyond, SEMICON West, October 2025Sustainable AI Systems, SEMI HQ, March 2026About the AuthorsDr. Pushkar P. Apte is the Strategic Technology Advisor for SEMI Global Lead for the Smart Data-AI Initiative Dr. Melissa Grupen-Shemansky is Senior VP and CTO of SEMI