Technology and Trends

In Q2, the SEMI International Standards Program made progress on several emerging initiatives. Together, we reached a critical milestone for one of our data standards initiatives with Document 6938C recently passing Technical Committee review in mid-June 2025. Ballot 6938C, which provides guidance on how to identify manufacturing equipment data provided by the equipment supplier that can be used in equipment engineering or analysis applications, is slated to join SEMI E190 and E190.1 in providing industry-enabling data standardization.In addition, we began major revisions to SEMI Standards S2, S8, and S10. These standards govern environmental, health, and safety (EHS) considerations, equipment user fatigue and injury reduction, and equipment risk assessment and evaluation, respectively. In our recently concluded North America Standards Summer 2025 Meetings, the NA EHS Technical Committee Chapter approved a revision ballot to SEMI S10. The ballot (7169) proposed several major revisions to the SEMI S10 Safety Guideline on risk assessment which included changes to references to equipment to objects under consideration. Other changes also included the relocation of the assessment of the risk of harm to property other than the OUC to a Related Information section. Additional details are provided below.We’re eagerly preparing for this year’s SEMICON West event, taking place for the first time ever in Phoenix, Arizona. We are also pleased to announce the return of the SEMI Global Standards Summit taking place Tuesday afternoon, October 7 at SEMICON West. Our inaugural Summit was held last year at SEMICON Japan 2024 last December. The Summit aims to identify standards-critical areas and work towards an industry standardization strategy for the next 3- and 7-year time horizons. This year's Global Standards Summit will feature sessions on Supply Chain Traceability as well as Environmental Sustainability. Similarly, as cybersecurity considerations become more complex, SEMICON West will host a dedicated Cybersecurity Forum from October 7-9 to address today’s most pertinent challenges. More detailed program information will be available soon. Finally, we’re looking forward to our SEMI Standards + Award Ceremony Networking Event at SEMICON West. Following the International Standards Meeting and Standards Summit on Tuesday, October 7, join us for appetizers, drinks, and great conversation from 6-7:30 p.m. In the meantime, learn more about becoming a member of the SEMI International Standards Program.Balloting for Document 6938Document 6938C introduces a new potential standard – Guide for Equipment Edge Data Governance. Under development by the Equipment Edge Data Governance (EEDG) Task Force since 2021, Document 6938C was balloted in Cycle 3-2025 and approved during the Information Control Taiwan Technical Committee (TC) Chapter meeting held on June 12, 2025. It has since received approval by the International Standards Committee Audits and Reviews Subcommittee and is now undergoing final processing for publication by SEMI. As manufacturing equipment offers more accessible data than ever, poor communication, inconsistent expectations, and data security concerns continue to halt or slow factory integration efforts. If passed, this new standard will help organize the information that supports smart manufacturing efforts at the edge. In addition, the EEDG Guide will provide a comprehensive set of best practices to both users and suppliers to increase the value of existing equipment data. Update on Revisions to SEMI S2, S8, and S10 Safety GuidelinesOur 2025 Q1 Standards Watch newsletter announced a significant overhaul for SEMI Standards S2, S8, and S10.S2, SEMI’s standard for performance-based environmental, health, and safety (EHS) considerations for semiconductor manufacturing equipment, is undergoing discussions on redefining safety interlock systems. The S2 task force will issue an informal ballot to the general audience for feedback. The results then will be used to develop a formal letter ballot.First developed in 1995, SEMI Standard S8 works to reduce fatigue and injury by matching equipment to the user’s size, strength, and range of motion. Although this safety standard has been periodically updated since its inception, its last substantial revision was in 2018. The ballot to revise S8 ultimately failed the EH S TC Chapter review at this year’s Winter Meeting. With 214 comments and negatives to consider, the task force is revising the ballot and plans to reissue in Cycle 7 of August 2025.Finally, SEMI Standard S10 is moving through ballot 7169. This standard defines a consistent means of risk estimation that other SEMI Safety Guidelines can invoke. Ballot 7169 will separate facility and building risk assessment to a non-normative portion of the document, ensure EHS risks are separately calculated from commercial object risks, and clarify risk assessment of observed events from risk assessment of foreseen events. Ballot 7169 results were reviewed on June 5 during the North America Standards Summer meetings. The document was approved and is being processed for publication by SEMI.Cybersecurity Forum at SEMICON West 2025This year’s SEMICON West will feature a dedicated Cybersecurity Forum to address the semiconductor industry’s rapidly-changing cybersecurity landscape. The SEMI Cybersecurity Forum will gather industry experts to share knowledge and experience on the following topics. The goal is to develop actionable strategies and a deeper understanding of current and future cybersecurity risks. Cybersecurity in Legacy Semiconductor ToolsEmerging and Existing Cybersecurity Legislation and ComplianceCybersecurity in Maintenance and ManufacturingImpact of Cybersecurity Events on Semiconductor Manufacturing OperationsSupply Chain SecurityThreat Landscape in Semiconductor ManufacturingThe 2025 call for abstracts is now closed. Speakers will be announced in Q3.SEMI E187 Compliance Guidance White PaperThe SEMI Semiconductor Manufacturing Cybersecurity Consortium (SMCC), in collaboration with industry experts, is pleased to announce the release of the SEMI E187 Compliance Guidance Whitepaper. This comprehensive resource is designed to support semiconductor equipment suppliers and device manufacturers as they work to meet the requirements of the SEMI E187 0122 Standard - The Specification of Cybersecurity of Fab Equipment.Professionals involved in tool development, manufacturing, operations, and security will find the guidance particularly relevant and actionable. It provides guidance to address all twelve SEMI E187 requirements and focuses on new to fab equipment.Download the Whitepaper for freeSEMI Standards North America Summer MeetingsThis year’s SEMI Standards North America Summer Meetings were held from June 2-5 at SEMI’s headquarters in Milpitas, California. The meetings convened 11 committees and 40 task forces to discuss topics ranging from EHS to facilities, 3D packaging, MEMS, and more. In addition to the results of ballot 7169, technical changes to ballot 6601B, New Standard: Guide for Meeting IRDS Yield Table Recommendations for High Purity Polymer Materials and Components Used in Ultrapure Water, was also approved by the Liquid Chemicals North America TC Chapter, since the activity began in 2019. A Ratification Ballot will be issued in Cycle 7-2025 to verify the changes. In total, over 15 activities, ranging from Auxiliary Information, Reapprovals, and Line-Item ballots, also recently passed Procedural Review by the International Standards Committee (ISC) Audits Reviews Subcommittee and will be forwarded to Publications for final processing. The next SEMI International Standards Meeting will be held at SEMICON West from October 7-9 at the Phoenix Convention Center. Some technical committees and task forces may meet virtually outside of this meeting set, so be sure to check the SEMI Standards calendar of events for updates. Standards Introduced in Q2 2025New and revised standards released in Q2. April 2025 standards: https://store-us.semi.org/collections/standards/stdpbc-0425May 2025 standards: https://store-us.semi.org/collections/standards/stdpbc-0525June 2025 standards: https://store-us.semi.org/collections/standards/stdpbc-0625Get InvolvedSEMI Standards development activities take place throughout the year in all major manufacturing regions. To participate, join the SEMI International Standards Program.SEMI Standards are available through individual download purchases or online via SEMIViews. Sign up for a 30-day SEMIViews trial.For more information, please visit the Standards website and events page. For any questions regarding SEMI Standards activities, please contact your local SEMI Standards staff. Paul Trio is Director of Standards at SEMI.

Ann Wu is CEO of EDA startup Silimate, developer of a co-pilot (chat-based GenAI) for chip and IP designers to find and fix functional and power, performance and area (PPA) issues in their designs. Rick Carlson is Vice President of Sales at ESD Alliance member company Verific Design Automation, provider of front-end EDA platforms to a range of small and emerging EDA companies like Silimate and larger EDA vendors.I recently talked with Ann and Rick who represent EDA’s new and old guard. I found them to be bullish about the emerging EDA space called AI EDA that uses GenAI and large language models as the foundational tools and the swelling numbers of well-funded startups entering this space.Smith: Ann, you were an Apple hardware designer. What encouraged you to leap into entrepreneurship using AI as the foundational technology?Wu: It was always my goal. Apple afforded me the opportunity to understand how one of the best companies producing some of the most cutting-edge chips in the world operates. It also gave me the opportunity to work with some of the most brilliant engineers and operators. My plan was then to go back to Stanford to explore and start a compelling venture with another similarly motivated friend, Akash Levy. That was the genesis of Silimate. The drive for leaping into entrepreneurship then ultimately stemmed from my frustrations with the existing chip design process. I sensed there was an opportunity to apply AI technology to solve some of these limitations of the existing approaches to chip design.Smith: What made you think that AI would be applicable to the EDA challenges that designers face?Wu: AI provides a compelling solution to some of the intractable problems that have existed in EDA. Traditional EDA solutions solve isolated problems through heuristic algorithms. There’s a high volume of gray area between the well-defined boxes of inputs and outputs that had previously been unsolvable. Now with AI, there is finally a way to sift through and glean patterns, insights, and actions from these gray areas.That’s the macro reason why there's so much excitement and appetite around the application of AI for EDA.Smith: It sounds like productivity enhancement. What are some other key words or selling points to use to convince a designer of AI’s potential for EDA?Wu: I would say "speedup" is one of those keywords. Ultimately, the designer is trying to meet or even shorten the time to tape out while hitting their design spec. That's driving all decisions, whether to throw more headcount at closing a certain block or to defeature something that's going to cause the team to miss the shuttle. It all comes down to whether a fully featured and functional design gets to tape out and gets to market ahead of competitors.Productivity as a keyword is not compelling. It’s hard to translate how saving minutes or hours of an engineer's time connects back to the bottom line. The bottom-line decisions are driven by the project’s timeline as time to market is everything.What’s needed is a way to sift out and resolve real design problems 100x faster, which ultimately results in real speed up on a project’s schedule. For example, processing large amounts of data with AI to find issues actively helps the designer converge their design to their target.Finding and resolving issues in a design within minutes instead of days or weeks instead of months is the kind of impact that directors, VPs, and managers want for adopting new tools.Smith: What is driving hardware designers into this EDA space?Carlson: The thing that's most intriguing is large language models, neural networks and AI. It seems like an “aha” moment when startup founders believe they can do something that's dramatic for the first time.When I look back over my photobook of moments in my time in the EDA industry, there's the wonderment. The things that can be brought to bear with iterative versions of new technology from companies like Ann's will offer multiple “aha” moments. This is game changing.Smith: Are venture capitalists investing in EDA again?Carlson: Yes. Some venture capitalists haven't invested in EDA for decades. These are smart people. They have plenty of good people that can do good due diligence. The amount of money that's being invested is significant. It's not just a little bit of seed funding. One startup’s first round was $3 million. They're now raising $20 million in the next round. They're saying that their pre-money has to be $50-$60 million. They're just coming out and there's a huge amount of interest.We're going to be looking back in a year and say we just couldn't believe how much money is pouring into this. It has a huge impact on the world stage. This is an amazing time to be doing anything in and around the design of computer chips.Smith: Y Combinator (YC) invested in Silimate.Wu: Yes, that's right. It's an honor to be the first EDA company that YC had invested in. The semiconductor and EDA space had been under the radar until recently—it’s such a critical piece of our technical infrastructure. The semiconductor industry hasn't been headline news in past years. Now every other day, the Wall Street Journal runs some semiconductor chip-related article. People are realizing this is a fundamental piece of our world's tech stack, and the software that drives this tech stack is equally important and there are investments to be made.Learn more about Verific and Silimate during the 62nd Design Automation Conference (DAC).Verific will exhibit in Booth #1316 at the Moscone Center in San Francisco from June 23-25.Silimate’s Akash Levy, Founder and CTO, will participate in a panel titled “AI-Enabled EDA for Chip Design” at 10:30am on Tuesday, June 24, 2025.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

The semiconductor industry is on track to expand and launch 97 new high-volume fabs online worldwide from 2023 through 2025, a major milestone that highlights the massive investment in chip production capacity. This rapid expansion is expected to drive a sharp increase in the deployment of pendulum valves. These valves, found in tens of thousands of semiconductor tools, are critical to the wafer manufacturing process.  Though hidden inside complex etch and deposition chambers, pendulum valves play a vital role in semiconductor manufacturing. They regulate gas flow and maintain the vacuum conditions required for precise wafer processing, ensuring efficient etching or deposition by controlling gases, managing exhaust flows, and maintaining chamber integrity. But what happens if a pendulum valve fails? It disrupts the vacuum necessary for wafer processing, causing chamber contamination and potentially ruining wafers. This leads to costly material scrapping, unplanned downtime, and production delays. Persistent failures can damage the turbo molecular pump or the entire tool, significantly increasing repair costs. Clearly, pendulum valves are essential for the reliability and performance of semiconductor equipment, particularly in etching and deposition chambers. Here are four critical reasons why:Consistent Vacuum Control: Maintaining a consistent vacuum environment is crucial for uniform layer deposition and etching, directly impacting the yield and performance of semiconductor chips. These valves regulate pressure and gas flow to ensure consistent and precise wafer fabrication processes. Contamination Prevention: Contaminants are a semiconductor manufacturer’s worst nightmare. Even microscopic impurities can destroy a wafer. Pendulum valves mitigate this risk with high-quality sealing mechanisms that create airtight environments, leading to high quality wafers and reducing waste.  Enhanced Yield: Pendulum valves are vital to achieving the highest possible yield in wafer manufacturing. Their ability to maintain operational stability and enhance process efficiency leads to fewer defects and higher productivity. By precisely controlling gas flows and preventing contamination, these valves reduce the likelihood of wafer defects and improve overall throughput. Minimal Footprint: Semiconductor fabs are high-tech, high-density environments where every square inch counts. Pendulum valves are designed with compact dimensions, allowing engineers to maximize production capacity without compromising performance or reliability.  Seal Performance Defines Valves’ Longevity  One of the core components of pendulum valves is its seals, directly impacting its durability, reliability, and maintenance. High-performance seals minimize downtime, reduce maintenance costs, and ensure a long operating life. However, achieving this performance requires attention to the challenges in semiconductor processes that impact performance and lifespan. Exposure to aggressive chemicals and plasma environments can degrade seals, causing erosion, sticking, and cracking. Continuous dynamic motion, including compression, decompression, and rotational movements, leads to friction and wear, shortening seal longevity. Errors, such as improper installation of static seals, can disrupt valve operation and cause delays. Extreme heat in wafer fabrication further tests the durability of valve components, while poor maintenance increases the risk of failures, resulting in costly downtime and repairs.  To keep valves operating at their peak efficiency, manufacturers need to prioritize five types of seals, identifying potential risks and tackling them effectively. The Pendulum Plate Face Seal, a dynamic component, must endure repeated compression and decompression during use. This constant motion, coupled with exposure to harsh chemicals, makes the seal vulnerable to issues like sticking and cracking. Without proper installation and attention, extreme failures, such as the seal dislodging entirely, can occur, disrupting operations.  Similarly, the Pendulum Plate Radial Seal performs a vital role, moving vertically within a piston bore. This component faces threats such as rolling, twisting, and chemical degradation, often leading to cracks or even fragmenting under severe torsional stress.   The Bonnet Seal, though static, is not exempt from potential difficulties. Improper installation or material cracking can severely compromise its functionality.  For dynamic applications like the Rotating Paddle Shaft Seal, friction is a constant adversary, compounded by chemical exposure that accelerates wear and tear.  Lastly, the Actuating Pins Seal, pivotal for enabling precise up-and-down movement within a piston bore, is particularly sensitive to installation errors.  When Failure is Not an Option  Addressing these challenges is essential to maintain the reliability and longevity of pendulum valves in semiconductor manufacturing. Greene Tweed uses a structured framework ‘Right Seal Pyramid’ to select the most suitable seal for every application. This process considers key factors like material compatibility, seal geometry, and operating conditions to develop solutions tailored to the specific needs of semiconductor manufacturing. By aligning seal types with precise engineering criteria, the Right Seal Pyramid methodology addresses key challenges like chemical resistance, mechanical stress, and installation accuracy, ensuring reliable performance in the harshest semiconductor manufacturing environments.  Explore MoreWant to learn how to prevent premature pendulum failure? Catch our full webinar replay or download our Semiconductor Playbook for expert insights, innovative solutions, and best practices tailored to your most critical applications. Carmen Quartapella is a Senior Engineer of Design Analysis at Greene Tweed. Quartapella has developed deep technical expertise over a three-decade career that spans multiple facets of the semiconductor industry. Throughout his career, he has gained expertise in Semiconductor Engineering, Engineering Management, Sales, Business Management, and Emerging Technologies. He graduated from Drexel University with a degree in Mechanical Engineering

As artificial intelligence (AI) proliferates rapidly, AI models and datasets are also growing rapidly in size. This growth far outpaces performance improvement in hardware systems, and is increasing AI’s energy consumption unsustainably. To address these challenges and explore collaborative solutions, SEMI’s Smart Data-AI Initiative - as part of its Future of Computing focus - recently hosted a day-long workshop on Sustainable AI Systems that brought together domain experts from the entire AI ecosystem. Speakers included industry leaders Applied Materials, AMD, Arm, ASE, Google DeepMind, IBM, Intel, Lam Research, McKinsey, Micron, NVIDIA, Qualcomm, SK hynix; exciting start-ups Cerebras, LightMatter, Mentium Technologies and Mueon; and leading-edge academic institutions, Stanford University and University of California, Davis Irvine. The keynotes, panels and spirited audience discussions covered novel devices, materials, advanced packaging, chiplets, photonics and architectures algorithms for data centers, cloud edge. This article synthesizes high-level insights from the workshop.The AI ImperativeThe day started with a basic question – why is AI essential to continued progress and prosperity? The answer lies partly in shifting global demographics, with the population aging in most developed economies. At the turn of the century, there were ~6 people in the workforce supporting each retiree, but projections indicate there will be only 2 active workers per retiree by 2050. In parallel, productivity growth rates have fallen to half of what is required. AI can help bridge this gap, if we can ensure continued progress of AI in a responsible and sustainable manner.The Energy WallA formidable roadblock to continued progress of AI is its rising energy demands. For example, the energy used by some large language models (LLMs) to run just one training cycle could be used to power thousands of homes. The switch to transformer models has increased AI-driven computing demand by a factor of 50 million over 5 years, and by some projections, this demand will consume half the world's generation capacity by 2050. This is clearly not sustainable! All players in the ecosystem are deeply committed to reducing AI’s energy consumption, and the industry has already decreased the energy used per token of computing by a factor of 100K in the past 10 years. However, the rapid growth of AI outpaces this, highlighting the huge challenge ahead.The System StackThis workshop was developed with the hypothesis that innovation is required across all segments, and an important first step is to initiate a dialog. Our highly distinguished speakers covered the entire solution stack, and while it is impossible to capture the ocean of insights that they shared, the following provides a flavor.Materials DevicesMaterials and devices used to build semiconductor chips form the foundation of the stack for all computing systems. Silicon substrates with copper interconnects remain industry’s mainstay, but are being augmented by innovative ideas. As device dimensions continue to shrink, novel 2D materials such as MoSe2, WSe2, ZrSe2 and NbP are being researched. While Si mobility degrades with decreasing film thickness, 2D materials maintain high electron mobility in thin-film substrates. These can be stacked to build 3D systems with lower power consumption than traditional planar structures. In parallel, novel device technologies such as gate-all-around (GAA) can provide power savings up to 25%.These novel materials and devices are complex, and require almost magical wizardry to build. For example, they may require depositing a stack of multiple defect-free films that are only a single (or few) atomic layer(s) thick, or etching a steep well that is one hundred times as deep as it is wide. It is an incredible accomplishment of the semiconductor industry to build these devices and chips successfully, but it is getting harder and more expensive. Consequently, AI is now being used as a tool to help with this ever-growing fabrication complexity of semiconductor R D and manufacturing. This is a synergistic virtuous cycle, where AI algorithms enabled by chips are used in turn to help with chip fabrication.System IntegrationThe next layer of the stack is the integration of individual devices into a system. Advanced packaging techniques, such as silicon or glass interposers (2.5D) for interconnecting chips, can reduce the communication distance and power consumption. These are often deployed for high-performance computing systems running AI algorithms. Beyond this, the industry is actively exploring 3D systems that are even more compact, both as multi-die 3D packages and as monolithic 3D chips.The concept of chiplets – smaller chips with specialized functions that can be assembled flexibly to optimize system performance – holds much promise. Industry consortia are developing protocols such as Universal Chiplet Interconnect ExpressTM (UCIeTM) to enable seamless integration of chiplets both in the planar and vertical dimensions. These advanced techniques pack more functional elements into increasingly compact form factors, but this proximity makes power delivery challenging and often generates intense heat. Much work is needed to ensure optimal power delivery and adequate thermal dissipation.Looking beyond traditional electronics, photonics represents an exciting opportunity. Most long-distance data communication is on fiber-optic cables and thus already photonic – bringing this to shorter distances can save energy while increasing bandwidth and performance. This requires efficient photonic-electronic integration at the packaging or even chip level, which is a major challenge requiring cross-disciplinary collaboration.Architectures and AlgorithmsAI algorithms need enormous amounts of data processing compared to traditional computing workloads. This requirement stretches (or breaks) the limits of traditional Von Neumann architecture, which requires frequent data movement between memory and processor elements for each computation cycle. Much of current architecture innovation focuses on bringing processor and memory elements closer to each other. System integration is already driving “compute-near-memory” architectures like high bandwidth memory (HBM). Other forward-looking implementations combine them into a single chip, known as compute-in-memory (CIM). Memory elements being explored for this purpose include resistive RAM (RRAM), phase-change memory (PCM), ferroelectric RAM (FeRAM) and magnetic RAM (MRAM). However, there is no one “perfect” memory – each has pros and cons in terms of latency, capacity, bandwidth, power consumed per operation, manufacturability, etc. Other researchers are also exploring devices like memristors for analog computing, which can improve energy efficiency for certain workloads.Finally, hardware-software co-optimization is crucial. Algorithms mismatched with the underlying system are energy expensive; conversely, co-optimized systems are highly efficient. While conceptually obvious, this is difficult in practice because development cycles are quite different – software algorithms can transform in a few months, while new hardware often takes years to develop. While some strategies can be used for mitigation – such as designing in redundancy/flexibility or making the hardware application-specific – much work remains to solve this conundrum.Pre-competitive Collaboration to Find SolutionsAll speakers emphasized that pre-competitive collaboration across the entire stack is critical, as these challenges are formidable and cannot be solved by one entity or in isolated silos. SEMI is a global and neutral organization with over 3,000 member companies, and is well-positioned to provide a pre-competitive collaboration platform to connect the dots across silos. In fact, SEMI’s mantra is “Connect, Collaborate, Innovate” – reinforcing its commitment to advancing the entire industry. For this purpose, SEMI’s Smart Data-AI Initiative continues to drive robust discussions on this topic – next there will be a roundtable discussion during SEMICON Southeast Asia, May 20-22 in Singapore, followed by a focused technology session at SEMICON West 2025, October 7-9 in Phoenix, Arizona. The overall objective is to move from “talking-the-talk” to “walking-the-walk,” towards creating system-level solutions for energy-efficient AI computing. Specifically, we want to identify the pre-competitive actions that could synergize individual innovations and make the whole greater than the sum of parts. Some ideas include collaborative proof-of-concept projects, industry standards and independent benchmarking. Come join us on this journey and connect with us at [email protected]. Dr. Pushkar P. Apte is the Strategic Technology Advisor and leads the Smart Data-AI Initiative at SEMI.

As healthcare undergoes a digital transformation, semiconductor technologies are emerging as a critical foundational enabler, making care more personalized, proactive, and accessible. At SEMI, we’re proud to highlight the leadership of STMicroelectronics (ST), a member and active participant in our Smart MedTech initiative’s governing council, for their commitment to advancing this critical frontier.With decades of experience in sensing, power management, and connectivity, ST is helping to shape a future where electronic systems seamlessly integrate with healthcare and wellness solutions, empowering both patients and providers.The Rise of Wearables and the Role of SemiconductorsST has long delivered innovation in automotive, industrial, and consumer electronics. Now, the company is applying its expertise to wearable health technologies, a rapidly growing segment that’s reshaping how we monitor, diagnose, and manage health.Today’s wearables go far beyond their predecessors. They capture vital signs and biomarkers such as heart rate variability, ECG signals, blood pressure trends, and more with medical-grade accuracy, providing real-time insights that can inform treatment and improve outcomes. This evolution represents not just a technological leap, but a shift in how we deliver and think about healthcare.A Shared Mission to Scale MedTech InnovationST’s active engagement with SEMI’s Smart MedTech initiative reflects our shared commitment to building an agile, responsive ecosystem that can bring life-changing technologies to the market faster. Through Smart MedTech, SEMI unites leaders across the electronics and healthcare value chains to identify systemic barriers, spark cross-sector dialogue, and co-create strategies for scalable success.ST brings invaluable perspective and technical depth to this mission. Their approach focusing on full solutions rather than standalone components, demonstrates how semiconductor companies can play a central role in enabling integrated healthcare systems.Meeting the Moment: Prevention, Personalization, and ReachHealthcare systems globally face mounting challenges: aging populations, chronic disease burdens, rising costs, and a projected shortfall of 18 million healthcare workers (WHO, 2019). Against this backdrop, wearables and remote health monitoring tools are poised to deliver tremendous value.As ST points out, the economic case is clear: treating chronic disease can be 100 times more expensive than prevention, wearables offer a proactive path forward. By enabling continuous, at-home health tracking, these devices empower individuals to take control of their wellness and allow providers to intervene earlier and more effectively.Accelerating the Future TogetherAt the SEMI 2025 Technology Workshop, ST joined a panel discussion exploring how semiconductors are reshaping healthcare. The session highlighted the need for earlier diagnosis, personalized care, and scalable solutions amid rising chronic disease and healthcare labor shortages.Panelists emphasized moving beyond component sales to integrated, system-level solutions. ST’s role on the Smart MedTech governing council emphasizes their commitment to cross-sector collaboration and advancing MedTech adoption.The MedTech revolution requires more than great products, it demands aligned ecosystems, shared knowledge, and coordinated strategies. As a member of SEMI and a key voice in our Smart MedTech initiative, ST exemplifies how semiconductor innovation can drive real change in healthcare.We’re proud to work alongside ST and other industry leaders who are committed to creating smarter, more sustainable healthcare through electronics. Because in today’s healthcare landscape, an ounce of prevention enabled by semiconductors isn’t just worth a pound of cure, it’s a blueprint for global health resilience.See the full ST article STMicroelectronics and Medtech: Enabling Personalized Healthcare and Wellness through the Integration of Electronics featured on Smart MedTech webpage.Gity Samadi is Senior Director of R D at SEMI.Rafael Tudela Senior Technical Marketing Manager at SEMI.Michelle Smith-Moritz is Senior Program Manager, Smart MedTech at SEMI.

Say ‘Ahhhh’ – imagine your doctor monitoring a health condition from afar or emergency responders receiving real-time alerts that could save a life. A new smart sensor is taking the ouch out of wound monitoring. By using laser-induced graphene (LIG), a two-dimensional (2D) material, researchers are developing a sensor that could revolutionize the tracking of wound healing and recovery. Doctors could get a much clearer picture of the healing process, identifying issues like inflammation, physical strain or a spike in body temperature early on. "This unique sensor material we've developed has potentially important applications in health care monitoring,” said Huanyu “Larry” Cheng, James L. Henderson, Jr. Memorial Associate Professor of Engineering Science and Mechanics (ESM) at Penn State. LIG sensors are self-powered which means they could be especially useful for continuous monitoring in clinical settings or helping detect fires in remote locations. Source: Materials Research Institute, Penn StateUnder the Sea – Mechanical engineers at Carnegie Mellon’s Soft Machines Lab have created a soft robot inspired by the quick and agile brittle starfish, the first mobile and untethered underwater crawling robot. Named after Sponge Bob Square Pants’ sidekick, PATRICK is an AI powered robot which operates without motors so as not to disturb delicate sea life. To make the robot move, the researchers hit it with electric current, causing the wires to heat up past its transition temperature and allowing the limbs to contract and move in different directions. “We want to put the power and the electronics on-board with the robots,” said Ph.D. candidate and PATRICK creator, Zach Patterson. The soft robotic systems which are ideal for tracking the health and quality of water, are biodegradable to eliminate waste and protect the natural environment.Source: Carnegie Mellon University, School of Engineering The sky is NOT the limit with engineering – While Blue Origin made the news recently for sending an all women crew to the edge of space, the first Mexican born woman to travel into space is Katya Echazarreta, an electrical engineer originally from Guadalajara, Mexico. Echazarreta was selected for the trip from a pool of 7,000 applicants from more than 100 countries based on her outstanding achievements in the space industry, including five NASA missions. She traveled to space in 2022 aboard Blue Origin’s NS-21 flight as one of Space for Humanity’s citizen astronauts. Echazarreta comes from a family of engineers and works to make space exploration accessible to young kids, teens, women, and other scientists and engineers through Fundación Espacial, a foundation started in Mexico. Source: Astronomy.comMargaret Kindling is Senior Program Manager at the SEMI Foundation. She promotes inclusive workplaces via initiatives including Women in Semiconductors, Semiconductor PRIDE and workforce and career development programming at SEMICON West and SEMIEXPO Heartland.

With microelectronics manufacturing increasing in complexity and facing more cybersecurity threats, the SEMI International Standards Program has made crucial progress on efforts to address these challenges and others, in the first quarter of 2025. MEMS manufacturing readiness and cybersecurity came into sharp focus with the introduction of SEMI Standard MS15 - Guide to MEMS Manufacturing Readiness Levels. In addition, this quarter saw the opening of the public commentary period for a SEMI-led semiconductor manufacturing cybersecurity profile, developed for the National Institute of Standards and Technology’s (NIST) Cybersecurity Framework (CSF) 2.0. Through collaborative efforts, we held a successful North America Standards Winter Meeting in February, co-hosted a MEMS webinar, and published over 15 new and revised standards in areas such as equipment automation software, facilities, materials, and more.With exciting developments still to come, we’re looking forward to a wonderful year ahead.MEMS Manufacturing Readiness This March, SEMI unveiled its new standard, SEMI MS15 – Guide to MEMS Manufacturing Readiness Levels. This standard offers readiness level definitions, processes, and practices for creating MEMS products that meet targeted specification performance, quality, cost, and time-to-market. This standard is broken into eight distinct levels that cover basic research, all the way through high-volume production. Prior to the official release of SEMI MS15, we held a webinar that previewed how MEMS Manufacturing Readiness Levels will facilitate efficient MEMS development. Led by co-chair, Michelle Bourke of Lam Research, the SEMI MEMS Sensors Industry Group (MSIG) hosted a webinar featuring MEMS experts from SoftMEMS, HP, Teledyne MEMS, and Polar Semiconductor. Speakers shared insight into creating a structured and balanced MEMS manufacturing approach to drive successful products to commercialization. Cybersecurity Resilience Like 2024, cybersecurity remains pertinent in 2025. Last October, SEMI introduced SEMI Standard E191 and its subordinate standard, SEMI E191.1 to help define cybersecurity status information reporting. SEMI E191 and E191.1 join SEMI’s existing cybersecurity standards, SEMI E187 and E188. Last year also saw the development of the NIST CSF 2.0 Semiconductor Manufacturing Profile under SEMI’s Semiconductor Manufacturing Cybersecurity Consortium (SMCC). In partnership with NIST, SMCC advanced a community profile for CSF 2.0 that will serve as a cybersecurity framework specific to semiconductor manufacturing. The profile opened for public commentary between February 27 and May 30, with the final version slated for official release in Q3 of this year.As the semiconductor industry becomes increasingly reliant on digital technologies, we will continue to prioritize cybersecurity standards and initiatives essential for safeguarding the global supply chain.North America SEMI Standards Winter MeetingsFrom February 24 to 27 at SEMI’s headquarters, leaders from 11 committees and over 40 task forces collaborated on new and revised standards and safety guidelines for environmental, health, and safety, equipment automation and software, liquid chemicals, traceability, and more. Three SEMI Standard draft documents that were reviewed at the North America SEMI Standards Fall Meetings last November have also been approved and published. In addition to SEMI MS15, SEMI F122 – Guide for Facilities Data Package for Manufacturing Equipment Installation and Building Information Modeling, and SEMI E193 – Specification for 300 mm Film Frame FOUP (FFF), have also been approved and published. SEMI F122 suggests formats for reporting facilities data required to plan, prepare, model, and optimize a facility for the installation of manufacturing equipment by fab owners and manufacturing equipment customers. SEMI E193 drives consistent implementation of interfaces for film frame carriers that are compact and work with existing 300 mm FOUP standards and BOLTS interfaces. These standards are now available for purchase. The North America SEMI Standards Summer Meetings will take place from June 2-5 at SEMI’s Milpitas, California headquarters. Some technical committees and task forces may meet virtually outside of this meeting set – check the SEMI Standards calendar of events for updates!Standards Introduced in Q1 2025New and revised standards released in Q1. January 2025 standards: https://store-us.semi.org/collections/standards/lang-english+stdpbc-0125February 2025 standards: https://store-us.semi.org/collections/standards/lang-english+stdpbc-0225March 2025 standards: https://store-us.semi.org/collections/standards/lang-english+stdpbc-0325TestimonialsHear from Doug Suerich, Director of Marketing at PEER Group, how his work is helping shape smart manufacturing standards and global cybersecurity policies through our powerful collaborative platform. Get InvolvedSEMI Standards development activities take place throughout the year in all major manufacturing regions. To participate, join the SEMI International Standards Program.SEMI Standards are available through Individual Download purchases or online via SEMIViews. Sign up for a 30-day SEMIViews trial.For more information, please visit the Standards website and events page. For any questions regarding SEMI Standards activities, please contact your local SEMI Standards staff. Paul Trio is Director of Standards at SEMI.

In a world where technological advancements move at lightning speed, the semiconductor industry is facing unprecedented challenges. The demand for smaller, faster, and more energy-efficient devices is growing, and traditional manufacturing processes are being pushed to their limits. Enter Spin-on Dielectrics (SOD), a breakthrough material technology that offers a cost-effective, scalable solution for micro-gap filling and high-performance dielectric films. As the industry evolves, SOD is expected to play a pivotal role in enabling the next generation of chips that power everything from AI to everyday electronics.To learn more, SEMI Europe and Merck KGaA, Darmstadt, Germany, held a joint webinar that focused on semiconductor device process evolution by SOD. The session featured insights from three technology experts in the company, including Dr. Surésh Rajaraman, Executive Vice President and Head of Thin Film Business Unit, along with Atsuko Yamamoto, R D Manager for Spin-On Dielectric, and Go Nakano, Global Marketing Manager for Dielectric Materials.SEMI: What is SOD, and how does it fit within the broader semiconductor manufacturing process?Rajaraman: SOD, Spin on Dielectrics, is a unique class of materials used to deposit thin layers of dielectric films, which act as insulators or other functional films, on semiconductor devices. The fabrication of a semiconductor chip involves thousands of intricate steps that incorporate conductors, semiconductors, and insulators. SOD is a versatile technology that supports device performance and miniaturization by enabling better gap fill and film uniformity, all while offering attractive cost of ownership.SEMI: Why is there so much focus on SOD materials, and how are they evolving to meet future industry demands?Rajaraman: As semiconductor devices become more complex—such as 3D NAND scaling to more than 300 layers and DRAM incorporating pillar capacitors—there’s a growing need for materials that can address challenges like interconnect delays, power consumption, and heat generation while maintaining optimal performance. Traditional dielectric materials are reaching their limits, making Spin-on Dielectrics (SOD) a critical solution. SOD offers advantages like bottom-up and seam-free gap filling, enabling ultra-thin insulating and other functional layers that enhance electrical and thermal efficiency and support next-generation device scaling.The industry is pushing the boundaries of scaling, with increasing aspect ratios and complex structures in Logic, 3D NAND and DRAM. Modern devices now require deposition in features which are not only incredibly narrow but also increasingly deep due to going into the third dimension. This creates new challenges, such as stress buildup and cracking in conventional SOD materials. To overcome this, we are developing enhanced formulations with improved mechanical stability and polymer backbone engineering. These innovations enhance gap-filling properties and resistance to process-induced stress, ensuring SOD remains a key enabler for advanced semiconductor manufacturing.SEMI: What are the current industry trends driving the adoption of SOD?Nakano: SOD is becoming a key technology because of its excellent gap-filling performance. Unlike gas-phase deposition methods like Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD), SOD is a liquid-phase process. This makes it more efficient for high-aspect-ratio structures. It also helps reduce costs while maintaining high-performance dielectric properties.With increasing demand for high-density memory and logic devices, SOD is crucial for applications like DRAM and NAND flash, which require precise dielectric layer formation. In DRAM, we’re witnessing a shift from planar to vertical transistors, and even to monolithic 3D DRAM. These changes require new materials for gate insulators and electrodes, alongside improvements in aspect ratio gap filling.For NAND memory, manufacturers are increasing the number of memory layers, leading to taller memory stacks and deeper trenches. As lateral scaling progresses, narrower and more complex structures demand high-aspect-ratio trench fills to maintain performance and reliability.Logic devices are also evolving, with transistor structures moving from FinFETs to nanosheets and forksheets. This transition enhances performance, but it also introduces challenges in wiring density and electrical properties. The narrower pitch of wiring requires advanced dielectric solutions, like SOD, to enable reliable, high-performance semiconductor architectures.SEMI: With all these recent innovations, what role does Merck KGaA, Darmstadt, Germany play in supporting these advancements, and what does the company offer its customers? Rajaraman: As the semiconductor industry pushes the boundaries of scaling, doing so requires materials that can support increasingly complex structures. We are the only materials company in the industry to possess the full spectrum of process technologies for gap-filling capabilities, including SOD, ALD, CVD, and Flowable CVD. Our strategic acquisition of Versum Materials has expanded our capabilities with organosilicon precursors. Combined with our SOD expertise, it allows us to reengineer material backbones with more material choices and tailored properties to optimize performance in high-aspect-ratio applications.To support this, we’ve expanded our global R D footprint. We now operate in various application labs, enabling close collaboration with customers for material customization and fine-tuning properties to address specific manufacturing challenges. Last year, we inaugurated a new R D center in Korea as part of our commitment to being near our customers and accelerating time-to-market for next-generation semiconductor solutions. As semiconductor roadmaps become more complex, customization and collaboration also become more critical. The key to innovation lies in working closely with our customers, understanding their challenges, refining materials, and optimizing processes together. By fostering this ongoing partnership, we can accelerate technological advancements and ensure that new solutions align seamlessly with evolving industry demands.SEMI: Can you share some technical insights on SOD?Yamamoto: SOD is a key material used in semiconductor manufacturing to create insulating layers with high precision. One of the essential components in SOD is PHPS (Perhydropolysilazane), a polymer composed of silicon, nitrogen, and hydrogen. This material is applied as a liquid solution and transforms into a high-quality silicon oxide film through a series of thermal processes.PHPS is essential because it enables precise gap filling in extremely small structures, helping to improve device reliability. The process involves spin-coating the polymer onto a wafer, followed by pre-baking to remove solvents. Then, it undergoes high temperature curing in an oxygen and steam atmosphere, forming a dense silicon oxide film. This method ensures uniform coverage and cost efficiency compared to traditional dry film deposition techniques.Our Spinfil® product line has evolved over the past two decades, starting with the Spinfil® 400 series and advancing through the Spinfil® 600 to the widely used Spinfil® 800 series. These improvements have enhanced gap-filling capabilities and film uniformity, making them ideal for high-aspect-ratio trench structures. The critical baking process involves spin coating and pre-baking before wafers undergo batch processing in a high-temperature furnace. Controlled temperature and moisture conditions transform Spinfil® into silicon oxide films, optimizing properties such as refractive index, shrinkage, and etching resistance and ensuring reliability in semiconductor applications.SEMI: What are the latest trends in new polymer development for SOD?Yamamoto: Our research focuses on three key areas: enhancing film quality, developing SOD for high-aspect-ratio trench filling, and advancing low-k SOD for semiconductor processes.To improve film quality, we introduced the Neofil®series, an evolution of the Spinfil® 800 series. This innovation reduces film shrinkage, lowers stress, and enhances wet etching rates, making it ideal for next-generation semiconductor nodes.Our latest Neofil® series for high-aspect-ratio trench filling is targeted for traditional dry processes like CVD and ALD, which can often lead to void formation and require multiple deposition-etch steps. Our latest SOD materials address this by improving polymer elasticity, ensuring uniform filling of deep trenches up to 16 microns without cracks, making them suitable for emerging 3D nanostaircase designs.In low-k SOD development, we’re focusing on siloxane-based polymers, which provide excellent trench-filling capabilities while maintaining strong mechanical and electrical properties. Compared to flowable CVD and ALD, SOD offers a more cost-effective and efficient alternative. With continued advancements, we anticipate SOD will become a key material for future semi-damascene processes, enhancing embedding performance and overall device reliability.SEMI ContactSitong He, Communications Manager Email: [email protected]

The world is abuzz with the new opportunities being created by artificial intelligence (AI), enabled by availability of unprecedented amounts of data. AI runs on the semiconductor engine, and in turn, creates a rising demand for semiconductor chips. The semiconductor industry is predicted to reach $1 trillion in revenue by 2030 by McKinsey Co., in large part due to the market demand for AI and data. There are, however, formidable challenges to overcome for this virtuous cycle to continue. The SEMI Smart Data-AI Initiative, together with the SEMI Future of Computing Think Tank, is working to help the industry address these challenges. This article paints the big picture and lays the groundwork for an in-person workshop on March 19, 2025, in Silicon Valley, where pre-competitive and collaborative solutions will be explored.“To unlock the full potential of AI, innovation is required across the technology stack – from the models and software to datacenter architecture, chip design and how those chips are made. Advancements in foundational semiconductor technologies will have a dramatic impact on system-level energy and cost reduction in the AI datacenter.” – Gary Dickerson, President and CEO of Applied MaterialsThe Performance ChallengeInvestment in AI system infrastructure is rising at a dizzying pace, with hundreds of billions of dollars being committed by individual companies as well as public-private partnerships around the world. AI models built on larger data sets generally deliver better results, so model sizes are growing exponentially each year, with leading-edge models requiring billions and even trillions of parameters. This is especially true with the rapid growth of the Large Language Models (LLMs) used for Generative AI. Can the foundational semiconductor technology keep up? Even if semiconductor chips were following the famous Moore’s Law, performance would only double every 2 years. The real pace of performance improvement is even slower, as leading-edge technologies are reaching physical limits of materials – with the tiniest patterned dimensions on chips now approaching the fundamental atomic separation distance. While semiconductor designers and process technologists continue to innovate with new materials, devices, 3-dimensional stacking and so forth, there remains a formidable challenge for silicon chips and hardware systems to keep up with the growth rate of AI models and data sets. The Energy ChallengeProcessing ever-larger data sets and AI models also requires increasing energy. A recent report by the US Department of Energy indicates that data center energy consumption tripled over the past decade and may triple again in just 5 years! Other analyses show that a single data center powered by 20,000 GPUs can consume almost 40,000 KW, which is enough to power 31,000 homes in the US! Consequently, it is challenging for data centers to meet their power needs through public utilities, and several hyper scalers are investing in nuclear power. This acceleration in AI energy demand is further exacerbated because silicon technology evolution no longer follows power scaling with “Dennard’s Law,” which states that power density remains constant as technology scales to tinier dimensions. In fact, energy consumption of silicon devices has been increasing with technology scaling for the last decade. These combined factors give rise to the second formidable challenge – energy consumption is rising unsustainably for AI systems.Exploring SolutionsAddressing these challenges requires innovation from algorithms and architecture to foundational silicon technologies. The following are illustrative examples (not comprehensive) spanning the entire AI system stack.At the software and algorithm level, innovators are finding ways to reduce model size and to use hardware more efficiently. For example, IBM’s Granite models are smaller in size, with less than a billion parameters. Similarly, Google's Gemma platform offers small language models (SLMs). The recent market disruption from the publication of the DeepSeek reasoning model suggests that relatively smaller domain-specific reasoning models may offer significant efficiencies. At the architectural level, multiple paths are being explored. Special-purpose (or domain-specific) processing elements can deliver improved performance at equal or lower power for specific tasks. Examples include Cerebras’ wafer-scale designs with optimized AI accelerators and Mueon’s system-scale integration solutions. Another innovation path focuses on bringing computing closer to the memory elements, where the data resides. This addresses the major bottleneck between processors and memory in the traditional Von Neumann architecture, which has been the mainstay of the industry since inception. In-memory or near-memory computing, such as memory-focused architectures from Micron or processor-in-memory (PIM) solutions from SK hynix, offer higher performance with lower energy consumption for certain workloads. In parallel, leading CPU and GPU makers like AMD, Intel, and NVIDIA continue to innovate with power-efficient solutions. And “Edge Intelligence” innovations – for example, internet-of-things (IoT) solutions from Arm and Qualcomm – help reduce the processing and power load on data centers by executing more operations on edge devices.Critical enabling technologies also contribute significantly. Advanced packaging, for example ASE’s heterogeneous integration solutions, enable efficient, high-performance computing by integrating multiple diverse components optimally. Another emerging development is the advent of “chiplets,” which split the chip into smaller parts, and enable special-purpose accelerator building blocks to be assembled with more general processor, memory, and interconnect elements. A well-developed chiplet ecosystem could provide silicon designers with more degrees of freedom to design optimized systems. Looking beyond electronics, the integration of photonics can enable low-power, high-bandwidth connectivity – for example, LightMatter’s silicon photonics interconnects and Ciena’s data center interconnects.Materials and devices form the foundation of the technology stack. Example technology innovations include Stanford University-led N3XT, a 3D solution that integrates multiple novel devices and materials including resistive and spin-torque transfer RAMs, carbon nanotubes and 2D materials. Similarly, a University of California-led effort synthesizes low-dimensional nanostructures, sensors, detectors and photonics in an integrated solution. Finally, advanced and innovative processes and equipment are being developed – for example, by Applied Materials and Lam Research – to fabricate these novel materials and devices.All these individual innovations are amazing and necessary, but are they sufficient? What if we could collaborate across the entire system and co-optimize hardware and software innovations synergistically? Could the integrated whole be greater than the sum of parts? What efficiencies could we unleash? And what business opportunities would this unlock?The SEMI Future of Computing workshop on March 19, 2025, seeks to answer these questions by uniting AI innovation leaders from industry, academia and start-ups, including most of the companies and universities mentioned in this article. We will begin building pre-competitive collaboration that breaks through silos and explores system-level solutions – with the ultimate objective of radically improving the energy-efficiency of computing for AI.Pushkar Apte is the Strategic Technology Advisor and leads the Smart Data-AI Initiative at SEMI.Jim Sexton is a Fellow at IBM.Melissa Grupen-Shemansky is CTO and VP of Technology Communities at SEMI.

Superconducting Naturally – Miassite is a naturally occurring mineral which scientists at Ames National Laboratory have identified as the first unconventional superconductor found in nature. Unlike conventional superconductors that follow the Bardeen-Cooper-Schrieffer (BCS) theory, minerals such as miassite exhibit unique properties outside of this framework. Made of rhodium and sulfur, miassite was initially recognized as a regular superconductor in 2010. Recent tests confirm it joins a small, exclusive group of unconventional superconductors previously limited to lab-made materials.Lab tests on miassite involved measuring magnetic reactions, inducing defects, and analyzing energy gaps, all confirming its unconventional behavior. While naturally occurring, samples are unlikely to be superconductive due to their disordered state, miassite’s lab-verified properties open doors to new research and highlight its unique duality as both a conventional and unconventional superconductor.Source: A Superconductor Found in Nature Has Rocked the Scientific WorldPheromones + vision = mate selection – When choosing a mate, Heliconius butterflies, despite their tiny brains can outperform current AI in multi-sensory decision-making by processing visual and chemical cues simultaneously. This discovery inspired Penn State researchers to develop a low-energy, multi-sensory AI platform using 2D materials. The device combines molybdenum sulfide (MoS2) to mimic visual capabilities and graphene to detect chemical signals like pheromones.The device could integrate visual and chemical cues, offering adaptability like a butterfly’s mating behavior. This innovation addresses limitations in current AI, which relies heavily on energy-intensive, single-sensory processes. Researchers aim to expand the device to process three senses, like crayfish using visual, tactile, and chemical cues. The work, supported by the U.S. Army Research Office and the U.S. National Science Foundation, could revolutionize applications in robotics, smart sensors, and critical environments, by enabling AI systems to detect issues using multiple sensory inputs efficiently. Imaging of Heliconius Butterfly A Butterfly Effect – Proving once again that there is a lot to be learned from nature, researchers from the Fraunhofer Institute for Solar Energy Systems ISE have developed innovative, colored solar facade elements inspired by morpho butterfly mimicry. These panels are aesthetically pleasing, integrate seamlessly into building exteriors, and retain high efficiency, achieving 95% of the power output of uncoated panels. Using vacuum-applied 3D photonic structures like those on butterfly wings, the panels produce vibrant, angularly stable colors with minimal energy loss. This MorphoColor® technology addresses architects’ and building owners’ concerns about design, offering an efficient, visually appealing solution for building-integrated photovoltaics while surpassing other technologies currently available.Close up of a morpho butterfly wingSustainable Flight – The world’s fastest supercomputer, Frontier, located at Oak Ridge National Laboratory, enables unprecedented advancements in sustainable aviation technology. Capable of over a quintillion calculations per second, Frontier allows GE Aerospace to conduct full-scale simulations of its revolutionary Open Fan engine design, accelerating insights into aerodynamics and turbulence. This groundbreaking tool aids the CFM RISE program, which aims to cut fuel consumption and CO2 emissions by at least 20%. Frontier’s detailed simulations predict engine performance under real-world conditions, saving years of testing. The partnership between GE Aerospace and Oak Ridge is expanding, promising future collaborations in climate modeling and advanced simulation techniques.An Open Fan engine design developed as part of a new project led by GE AerospaceSource: https://www.geaerospace.com/news/articles/new-frontier-how-ge-aerospace-using-worlds-fastest-supercomputer-help-design-open-fanMargaret Kindling is Senior Program Manager at the SEMI Foundation. She promotes inclusive workplaces via initiatives like Women in Semiconductors, Semiconductor PRIDE and workforce development programming at SEMICON West and SEMIEXPO Heartland.