Technology and Trends

The SEMICON West 2025 design program “The Convergence of Semiconductor Manufacturing and Design,” organized by the ESD Alliance (ESDA), a SEMI Technology Community, featured presentations about successful collaborations between the design and manufacturing markets. The three-hour program in a packed conference room included plenty of great material that we’re using as the basis for a blog series that you will see over the next several months. I’m working on them now based on my conversations with four of the speakers where we discuss key drivers behind the need for collaboration and what’s ahead.I’m starting with Dave Kelf, CEO of Breker Verification Systems, a company steeped in front-end chip verification, who describes an actual circular collaboration that effectively leverages AI and other electronic design automation (EDA) advances. We recently talked about collaboration, integrated design and manufacturing flows and AI.Smith: How does Breker define collaboration between design and manufacturing? Kelf: In general, at a technical level, we would define this collaboration as the sharing of data, methodology and/or information that improves both processes. As semiconductors become more complex, this sharing process is increasingly important to effectively manage the overall complexity of today’s chip designs.Smith: What trends are driving the need for this collaboration?Kelf: Apart from the ever-increasing size and density of semiconductors, there are specific trends that require more interaction between design, verification and manufacturing. Obvious developments include the advent of chiplets, given the changes in performance of signal paths, and 3D devices driving complex packaging, power dissipation and other issues. Design issues such as the increased need for SoC coherency testing and complex device structures such as multi-core processors, also play a role. With many of these issues, design and verification (D/V) trade-offs have an impact on manufacturing, and vice versa. For example, differing delays on a Universal Chiplet Interconnect Express (UCIe) interface—an open specification for a die-to-die interconnect and serial bus between chiplets—will have an impact on hazard testing in coherency verification. As another example, thermal hotspots on some parts of a chip package might need additional testing during the verification phase. Smith: What trends and challenges are preventing a fully integrated design and manufacturing design flow?Kelf: Traditionally, the D/V and manufacturing teams have remained separate in most organizations, as well as between the two industries. EDA companies sell primarily to the design teams, although they do interact with the foundries at the back end of the process. Manufacturing companies work directly with different teams at the foundries and not with the D/V teams at all. New relationships need to be built up. The general know-how in these disciplines is different, and methodology approaches tend to be disconnected. The tradition is to separate the processes and use standardized interfaces for communication that leaves little room for improvisation. All this needs to change so that teams can begin to work more closely.Smith: What is circular EDA-manufacturing collaboration and vertical integration?Kelf: In past EDA flows, we have seen disparate tools performing specific functions. As semiconductors got smaller, their physics changed and this led to the design process absorbing new characteristics. For example, abstract designs were run through synthesis to create gates connected by wires. This format was then passed to place and route (P R) tools that would lay out the gates in terms of transistors and interconnects on the silicon wafer. On large devices, the gate level signal delays were larger than the interconnect, allowing design to be separated from layout. As silicon became denser, the interconnect delays became the dominant factor, and the layout of the device impacted the design synthesis process. The two tools required forward integration—synthesis projected layout rules to P R, and a reverse integration where layout characteristics were sent back to synthesis for redesign where required delays could not be handled during P R. The methodology went from a simple flow to a circular design approach as synthesis and P R cooperated. The same is now true of design and manufacturing where solving the problems noted above requires this same circular cooperation. Smith: What will it take to have an integrated design and manufacturing flow?Kelf: A lot of cooperation between different groups. As we reach limits in areas such as signal integrity and thermal management that will squeeze silicon efficiency improvements, these methodology linkages will be required for continued progress and growth. The industry (both design and manufacturing) will be highly motivated to make this happen. Smith: From a personnel perspective, who (on both sides) are the typical touchpoints? Kelf: It will be the engineering staff from both the design side and manufacturing that work closely to develop technical solutions. Executive-level support is, of course, needed to cement the collaboration. Smith: Where does AI fit?Kelf: AI will have a role to play in this. Estimating the factors that drive efficient design to manufacturing to design flows is a critical step in speeding interaction and providing sensible estimated starting points. AI can process the large amounts of data necessary to provide these estimates as we now see complex chips that contain billions of transistors. AI will be needed to accelerate the interactions for different tools through the development process.As design and manufacturing collaboration becomes a critically important industry strategy, companies are turning to SEMI and its Technical Communities such as the ESDA and their wide-ranging initiatives. For details and to get involved, visit the ESDA website at https://www.semi.org/en/communities/esda. To learn more about Breker and its solutions that provide test content portability and reuse to solve complex semiconductor challenges across the functional verification process, go to: https://brekersystems.com.About Dave KelfDave Kelf holds the position of CEO of Breker Verification after serving as its Chief Marketing Officer responsible for all aspects of Breker’s marketing activities, strategic programs and channel management.Earlier, he served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions, was president and CEO of Sigmatix, Inc., and held senior positions at Cadence, Synopsys and Springsoft. Kelf holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University, both in the U.K., and an MBA from Boston University.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

Silicon carbide (SiC) has become a cornerstone of next-generation power electronics, driving advancements in electric vehicles, renewable energy, and industrial applications. After several years of rapid capacity expansion, the SiC industry is now entering a new phase focused on optimization, quality, and long-term scalability.This transition reflects a broader realignment across the global semiconductor ecosystem. As new fabs come online and supply chains mature, the industry is prioritizing stability, cost efficiency, and technical excellence over sheer capacity growth. SiC has moved from being a niche technology to a critical enabler of the energy transition, and this maturity demands not only investment in tools and materials, but also in process knowledge, cross-industry standards, and long-term partnerships that can sustain innovation at scale.To understand how this shift is unfolding, SEMI Europe spoke with Dr. Mark Puttock, Senior Director, Technology and Innovation at Entegris. Puttock shared his perspective on the industry’s evolution and how strategic collaboration and process innovation are shaping the next chapter of SiC manufacturing.From Ramp-Up to RefinementThe early growth of SiC manufacturing was driven by surging demand for high-efficiency power devices, particularly in electric vehicles. According to Puttock, that expansion period has given way to a new focus on yield, uniformity, and process control.The industry is entering a stage of maturity where success depends on optimization rather than scale alone. Improving consistency across crystal growth, wafer, and device fabrication is becoming just as important as adding capacity. This refinement phase calls for closer integration between materials science and manufacturing technology to ensure reliability and cost efficiency.A Focus on Process and Materials InnovationAs SiC moves toward high-volume production, challenges related to contamination control, defectivity, and wafer uniformity are taking center stage. Puttock noted that addressing these issues requires collaboration between materials suppliers, equipment manufacturers, and device makers.Efforts across the industry are converging on similar goals: enhancing purity, improving process repeatability, and developing new methods to enable larger wafer formats. Moving from 6-inch to 8-inch SiC wafers, for example, is widely recognized as a key step toward higher throughput and cost efficiency. Puttock emphasized that innovation in materials science and manufacturing technology must go hand in hand to support this scaling trend.Insights from Cross-Industry CollaborationA recent Entegris blog post featuring insights from Volkswagen Group Components and Porsche Consulting explores how SiC adoption is reshaping manufacturing strategies beyond the semiconductor industry. The post also highlights the strategy paper developed by Porsche Consulting in collaboration with Entegris. This joint effort demonstrates the value of aligning semiconductor-grade precision with automotive manufacturing demands. By sharing perspectives across industries, partners can accelerate best-practice adoption and strengthen the overall ecosystem for wide-bandgap technologies.Building a Sustainable FutureSustainability remains an integral part of this optimization phase. SiC devices themselves enable energy efficiency in end applications, but the way they are manufactured is equally important. Optimizing material use, recycling process consumables, and improving chemical delivery efficiency all contribute to a smaller environmental footprint. As production scales, attention to both performance and sustainability will be key to long-term success.Looking ForwardThe transition from expansion to optimization marks a pivotal moment for SiC manufacturing. Industry focus is shifting from building capacity to mastering control, quality, and resource efficiency. Puttock sees the future of SiC as one shaped by deeper digital integration, data-driven process development, and continued collaboration across disciplines. These advancements will help enable more consistent, sustainable, and cost-effective production—laying the foundation for the next generation of high-performance power devices.At the same time, Entegris continues to invest in materials science, contamination control, and advanced process technologies that help its customers overcome the complex challenges of SiC manufacturing. By combining technical expertise with a collaborative approach, the company plays an active role in supporting the industry’s transition toward more efficient and sustainable production.James Lam is Business Development Manager at SEMI Europe.

The semiconductor industry is undergoing a rapid transformation. Artificial intelligence (AI) applications, such as agentic and physical AI, push compute demands to unprecedented heights, prompting the semiconductor industry to push the boundaries of 2nm technology and beyond. Yet, as we move to these advanced semiconductor technology nodes, it has become increasingly challenging for academic research to remain closely connected with the fast-evolving industrial developments, limiting academic researchers in driving innovation. Europe’s NanoIC pilot line, a pioneering European initiative, hosted by imec, is addressing this challenge by offering pathfinding process design kits (P-PDKs). To cover the potential of these P-PDKs and their impact on Europe’s semiconductor ecosystem, we sat together with Professor Mehdi Tahoori (professor at Karlsruhe Institute of Technology) and Anita Farokhnejad (DTCO Program Manager at imec).SEMI: What exactly is a P-PDK, and how does it differ from traditional PDKs?Farokhnejad: At its core, a process design kit (PDK) is a software environment that enables circuit designers to simulate, validate, and optimize chip designs using realistic models of chip technology. Consider it a blueprint or a simulation toolkit allowing chip designers to explore performance, power, and manufacturability of a new chip architecture in a virtual sandbox. What sets P-PDKs apart is that they anticipate future technologies. Unlike traditional PDKs, which are based on existing technologies, P-PDKs are built on predictive models of future nodes and architectures. This allows researchers to explore system-level trade-offs, assess architectural implications, and prepare design flows before a technology reaches maturity. SEMI: Why are they so crucial for academia?Tahoori: For decades, academic researchers could contribute to semiconductor innovation using abstraction layers that allowed them to design and test new architectures without direct access to the latest technologies. This approach worked well until the industry reached the 20-nanometer node. At that point, the complexity of semiconductor design increased, with the introduction of advanced device architectures like FinFETs, nanosheets, Forksheets, CFETs, and novel integration solutions such as 3D stacking and chiplet integration.Transistor scaling in the AI eraTraditional abstraction models could no longer keep up with these advances, and the gap between academic research and industrial practice began to widen. This growing gap started to limit academia’s ability to participate in semiconductor paradigm shifts, such as CMOS 2.0 and new computing architectures. P-PDKs, enabled by the NanoIC pilot line, aim to bridge this gap, restoring the connection between academic thinking and industrial progress.SEMI: How does this support semiconductor innovation in Europe?Tahoori: Universities are ideally positioned to drive out-of-the-box innovation and invent new paradigms for computing. This is where universities truly excel. But to do that, they need access to the latest technologies and tools. We see for example a strong focus on the AI revolution and how the microelectronics industry is enabling that transformation. To meet the demands of AI applications and the computing power they require, we need to design new computing architectures based on advanced technology nodes. This is precisely the academic area of expertise. To design these new AI computing architectures, however, we need the most advanced technologies available. The P-PDKs for advanced nodes provided by the NanoIC pilot line now make this kind of research possible at universities. Something that was not feasible before.Additionally, the P-PDKs also provide an important reference technology and platform to benchmark and validate these innovations within a next-generation design roadmap. This means researchers can test their novel architectures against realistic process and performance metrics.SEMI: Are they only available for academia?Farokhnejad: The NanoIC P-PDKs are meant to be accessible to foster innovation across Europe’s semiconductor ecosystem. These advanced PDKs are therefore also available to European research organizations, startups, and industry partners. Access is facilitated through Europractice, where eligible users can apply by signing a Design Kit License Agreement (DKLA). Once approved, they gain access to the PDKs.SEMI: What other technology nodes are NanoIC’s PDKs addressing?Farokhnejad: The first P-PDK was released in June (first version of the N2) and supports frontside and backside routing with TSVM, standard cell libraries, and multiple VT flavors for early-stage design exploration. Upcoming releases include new versions of the N2 P-PDK, as well as A14 and A7 PDKs, eDRAM and SOT memory PDKs, and advanced interconnect solutions such as redistribution layers (RDL), hybrid bonding, and interposers.Those interested in learning more about the NanoIC ecosystem and the research enabled by the P-PDKs can meet representatives and partners of the NanoIC pilot line during SEMICON Europa, November 18-21 at booth C2417 in Messe Munchen. More information about the initiative is also available on the NanoIC website.BiosMehdi Tahoori, Professor Chair of Dependable Nano-Computing - Karlsruhe Institute of Technology Mehdi B. Tahoori is Professor and Chair of Dependable Nano-Computing at the Karlsruhe Institute of Technology (KIT), Germany, and guest professor at imec, focusing on CMOS 2.0 and future chip technologies. He previously worked at Xilinx (USA), Fujitsu Labs (USA), and served as a junior professor at Boston Northeastern University (USA) and as a visiting professor at the University of Tokyo (Japan). He earned his B.S. from Sharif University (Iran) and M.S./Ph.D. from Stanford (USA). Prof. Tahoori is Deputy Editor-in-Chief of IEEE Design and Test Magazine, is a former Editor-in-Chief of Elsevier Microelectronic Reliability and has chaired major IEEE symposia. His honors include multiple best paper nominations and conference awards, the US National Science Foundation Early Faculty Development (CAREER) Award (2008), an ERC Advanced Grant (2022), and an IEEE fellowship.Anita Farokhnejad, DTCO Program Manager - imec Anita Farokhnejad earned her PhD from Universitat Rovira i Virgili (Spain), specializing in FEOL and device modelling. She joined imec in 2021 as an R D Engineer, focusing on BEOL optimization and future roadmap development. Collaborating closely with integration and physical design teams, she develops models for PnR data analysis and BEOL optimization. Her recent work on the enhanced Ring Oscillator (eRO) model aids in the early assessment of new materials and BEOL boosters. In August 2023, she advanced to team lead for PDK Enablement, translating advanced semiconductor nodes into Pathfinding-PDKs. Farokhnejad is also dedicated to education, conducting courses that make sophisticated technological concepts accessible to both industry veterans and aspiring engineers. Currently, she serves as Program Manager of DTCO at imec, where her contributions continue to drive innovation in the semiconductor industry.AcknowledgementThis work was enabled by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union’s Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. For more information, visit https://www.nanoic-project.eu.DisclaimerFunded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or Chips Joint Undertaking. Neither the European Union nor the granting authority can be held responsible for them. SEMI ContactJames Lam, Business Development ManagerEmail: [email protected]

Q3 2025 was packed with activity. From finalizing the Standards program for SEMICON West, to organizing the event’s corresponding Global Standards Summit (GSS), the Standards team is excited to share its most recent quarterly developments.On Tuesday, October 7, leaders from across the industry convened in Phoenix, Arizona, for the second annual GSS. This half-day summit focused on future standardization needs for supply chain traceability and environmental sustainability. In addition, the Standards team conducted two workshops at SEMICON West. The first, SEMI Liquid Chemicals Analytical Workshop, detailed recent advances in analytical methodology and instrumentation related to particle measurement, trace metals, and organics in liquid chemicals. The second, Enhancing Voltage Sag Immunity: SEMI F47 Standards Updates Insights Workshop, offered a forum for sharing improvements to SEMI Standard F47 to further enhance tool performance and reliability. Finally, Q3 saw the official introduction of SEMI Standards T26 and E195. SEMI T26-0925, Specification for Electronic Supply Chain Traceability Using Distributed Ledger Technology, will be crucial for improving security and transparency for the industry’s supply chain. Additionally, SEMI E195-0925 is now available for purchase. This standard, Test Method Using Adhesive Replacement Substrates to Assess Particulate Surface Contamination on Critical Chamber Components, offers a testing approach for measuring the ISO 14644-9 cleanliness of a critical chamber component.To participate in upcoming standard developments, learn more about becoming a member of the SEMI International Standards Program. Global Standards Summit The SEMI GSS made its North American debut at this year’s SEMICON West in Phoenix. Building on its inaugural event at SEMICON Japan 2024, GSS is a strategic forum dedicated to creating an industry-wide standardization roadmap for the next three and seven-year benchmarks. The 2025 GSS continued conversations from SEMICON Japan on environmental sustainability, while expanding its program to include supply chain traceability. As geopolitical tensions, mounting cybersecurity threats, and rising technological demands continue testing the limits of the industry’s supply chain, the need for global standardization is becoming increasingly apparent. The 2025 GSS program addressed these concerns and others across multiple sessions, offering insight on how these challenges are being addressed in the industry while highlighting critical areas still in need for standards development. Key outcomes from the GSS program include: Addressing data sharing across multiple supply chain tiers while protecting IP rights and a call for harmonization across standards. The presentation by Randy Hall from the Provenance Chain Network, offered approaches on how data owners can share information with authorized users without compromising sensitive manufacturing details. While there are standards gaps that hinder broader adoption, there is opportunity to address insufficient visibility across the industry’s supply chain amid ongoing cybersecurity threats by harmonizing across existing standards implementations. An integrated modeling framework for informing energy efficiency and carbon reduction approaches. Developed by the International Roadmap for Devices and Systems (IRDS) Environmental Sustainability for Semiconductor Facilities (ESSF) team, this effort helps address demands for maintaining rapid technological progress while still meeting the industry’s ambitious sustainability goals.Standardization opportunities for improving sustainability within manufacturing facilities. Nate Monosoff from Jacobs offered insight into the decision-making tradeoffs that balance sustainability with other facility performance areas, focusing on standard methods for calculating ESG performance. GSS concluded with a panel discussion that featured leaders from AMD, FTD Solutions, Intel, The Provenance Chain Network, Jacobs, Qualcomm, and Tokyo Electron. In this session, our thought leaders discussed the fundamental importance of standardization for our industry, standards adoption, incentivizing stakeholders, and how standards can be designed to remain flexible and adaptive as technologies and regulatory landscapes evolve. SEMI Standard T26In line with the 2025 GSS theme of supply chain traceability, the Standards team is pleased to introduce SEMI T26, Specification for Electronic Supply Chain Traceability Using Distributed Ledger Technology. This standard was published in September to define a secure and decentralized traceability system that all members of the electronics supply chain can safely share. This system is based on distributed ledger technology to improve industry-wide reliability assurance.Update on Document 7130CIn February, Document 7130C was approved during the North America Metrics Technical Committee Chapter Meeting. The document officially became SEMI E195 - Test Method Using Adhesive Replacement Substrates to Assess Particulate Surface Contamination of Critical Chamber Components in September.SEMI E195 describes a quantitative method for measuring the ISO 14644-9 surface cleanliness for particle concentration of a critical chamber component (CCC), by means of an adhesive replacement substrate. The purpose of this standard is to ensure measuring and reporting consistency across CCCs or processing equipment manufacturers. To help acquaint the industry with this standard, SEMI offered a combined, in-person course on SEMI E194 and SEMI E195 during SEMICON West. The course provided fundamental information on each standard, in addition to other process approaches for improving reliability and yield.Other SEMI Updates:SEMI Preventive Maintenance Automation White Paper SEMI Korea conducted a Global PM Automation Survey in August to better understand today’s preventive maintenance readiness issues for autonomous fabs. The results will be included in SEMI’s upcoming PM Automation Whitepaper and will ultimately guide future developments for related SEMI Standards. Standardized Semiconductor Cyber Assessment FrameworkIn Q3, the Semiconductor Manufacturing Cybersecurity Consortium (SMCC) released its Standardized Semiconductor Cyber Assessment (SSCA) framework. This document provides a detailed cybersecurity readiness plan for semiconductor companies across the supply chain. Its goals are to standardize industry-wide cybersecurity risk evaluations, establish and accelerate the adoption of best practices, and improve information sharing and collaboration. Download the SSCA framework for free.New Data Standard for Equipment Edge Governance In June, Document 6938C was approved during the Taiwan Information Control Technical Committee Chapter Meeting. The document officially became SEMI E196 - Guide for Equipment Edge Data Governance. SEMI E196 provides guidance for identifying equipment data supplied by manufacturers that can be used in equipment engineering or analysis applications.New Guide to Meet IRDS Yield Table RecommendationsAt the NA Summer Meetings, Document 6601B passed TC Chapter review with technical changes and a Ratification Ballot was issued in Cycle 7-2025. Pending final Procedural Review, Guide for Meeting IRDS Yield Table Recommendations for High Purity Polymer Materials and Components Used in Ultrapure Water, will cover areas that establish criteria for allowable contribution by critical components used for UPW treatment plant and distribution system. This document will be proactively updated to manage the risks associated with the high purity polymer materials used in the semiconductor process. The biggest challenges today are metals and particles and certain organics.Flex Standards Meeting at FLEX 2026Meet the leaders of the SEMI Standards Flexible Hybrid Electronics (FHE) Task Forces at Flex 2026, in Arizona, February 24-26, and learn about ongoing FHE standardization efforts!Standards Introduced in Q3 2025New and revised standards released in Q3. July 2025 StandardsAugust 2025 StandardsSeptember 2025 Standards Get InvolvedSEMI Standards development activities take place throughout the year in all major manufacturing regions. To participate, join the SEMI International Standards Program.SEMI Standards are available through individual download purchases or online via SEMIViews. Sign up for a 30-day SEMIViews trial.For more information, please visit the Standards website and events page. For any questions regarding SEMI Standards activities, please contact your local SEMI Standards staff. Paul Trio is Director of Standards at SEMI.

Atomic layer deposition (ALD) and atomic layer etching (ALE) are transforming the way semiconductors are built—layer by layer, atom by atom. These atomic-scale processes are essential to scaling future transistors, improving memory, and enabling next-generation device architectures.SEMI spoke with Sergei Ivanov, Business Technology Director of Metallics R D and Balaji Kannan, Business Technology Director of Dielectrics R D and from Merck KGaA, Darmstadt, Germany to learn about their latest material innovations. At the company’s Electronics business, materials scientists and process engineers are advancing atomic-scale engineering to address some of the semiconductor industry’s toughest challenges. From novel deposition chemistries to next-generation etch techniques, their work is helping to enable future logic, memory, and specialty devices.Pushing the Boundaries of ALD Precursor ChemistryAtomic Layer Deposition (ALD) remains a cornerstone technology for scaling transistors and enabling new architectures. Materials scientists at Merck KGaA, Darmstadt, Germany are exploring novel precursors that enhance film quality, streamline processes, and expand the operational window for complex structures:One area of focus is next-generation hafnium and zirconium precursors. “These advanced high-k dielectrics offer better thermal stability, improved step coverage, and reduced impurities while achieving higher k-values,” Sergei Ivanov explained. “Such attributes are essential for logic and memory devices that demand reliable dielectric performance with minimal defect density.”Another important development is area selective deposition (ASD). Merck KGaA, Darmstadt, Germany’s small-molecule inhibitor solutions reduce the need for advanced patterning in narrow dimensions and 3D geometries, enabling cost-effective and simpler integration for leading-edge nodes. Their selective co-reactants platform leverages digitalization techniques including multivariate analysis, digital twin technology, and machine learning to accelerate process development for critical ASD applications. This approach facilitated industry-first adoption of ASD in high volume manufacturing and enables an ever-expanding toolbox of OEM processes for ASD of high-k, Ti, Mo, Si and other thin films.Merck KGaA, Darmstadt, Germany is also broadening the scope of ALD chemistries across the periodic table. “As our customers encounter new technical challenges, we continue to expand our R D scope across new elements and ligands. Examples include europium, lanthanum, scandium, and cerium dopants with improved electrical properties, niobium and vanadium precursors for deposition of nitride and oxide films with reduced impurities and improved ALD performance, and high-performance nickel MILC solutions are finding their way out of our labs and into customer roadmaps at an ever-accelerating pace,” said Sergei Ivanov.The company’s role in molybdenum chemistry is another example. Merck KGaA, Darmstadt, Germany is a key producer of molybdenum precursors including MoO2Cl2 with industry-leading quality, density, and container utilization. The company offers MoCl5 with advanced trace impurity control paired with innovative container technology. The company’s next-generation organic metallic molybdenum precursors incorporate novel ligands that contribute to critical gains in device performance.Merck KGaA, Darmstadt, Germany’s work with organosilane precursors is also opening new possibilities. “For gate-all-around (GAA) transistor technology, precursors incorporating novel bonding structures enable highly conformal dielectric films with excellent electrical and physical properties, even in complex 3D geometries. At the same time, organosilane chemistries designed to increase silicon incorporation during deposition are supporting high-growth-rate oxides for gapfill applications, delivering the thick films required with greater throughput,” said Balaji Kannan. “Together, these innovations highlight how tailored precursor design can address both scaling challenges and manufacturability in next-generation devices.” Driving Selective and Sustainable Atomic Layer Etching (ALE)“Precision in etching is as critical as deposition. Our innovations in ALE are designed to provide ultra-selective, low-damage material removal, which is increasingly vital as device geometries become finer and more complex,” Sergei Ivanov shared. One example is metal-free ligand exchange ALE for high-k materials, where Merck KGaA, Darmstadt, Germany’s research into etching HfO₂, ZrO₂, and HfZrO₄ showcases a novel metal-free approach. This technique enables accurate and damage-minimized etching of high-k dielectrics, which is essential for integrating advanced transistors and memory stacks.These advancements address industry-wide concerns regarding pattern fidelity, material selectivity, and plasma-induced damage, ensuring greater process control and extending the lifetimes of devices.Looking AheadMerck KGaA, Darmstadt, Germany’s strategic commitment to semiconductor innovation includes ongoing R D efforts that reflect the vision of its Electronics business: providing material-centric solutions to the industry’s most complex integration and performance challenges. Whether advancing front-end device scaling or developing breakthrough materials for emerging applications, the Electronics business of Merck KGaA, Darmstadt, Germany is committed to shaping the materials roadmap for a more connected, intelligent, and efficient world.James Lam is Business Development Manager at SEMI Europe.

AI is proliferating rapidly, fueled by ever-larger models and data sets that are expanding AI use cases and improving its accuracy. Future computing systems are now required to simultaneously deliver high performance, process large amounts of data, and use the least possible energy. The growing energy footprint of AI and the strain it places on the power grid is an increasing concern for companies and even entire countries. This could adversely impact future growth and could slow the semiconductor industry’s march towards $1 trillion in revenue, which is largely driven by AI applications.This is a formidable challenge that cannot be addressed in silos by individual companies or even industry segments. The SEMI Smart Data-AI Initiative is exploring how to overcome this challenge with collaborative and innovative system-level solutions that connect the dots across the entire AI system stack. In March 2025, we hosted a successful workshop, bringing together industry leaders across the value chain for a day of thoughtful discussions and knowledge sharing. Building on this foundation, we developed an exciting Smart Data-AI session to be held at SEMICON West in Phoenix, Arizona on October 7 from 10:30 a.m.-4:40 p.m. The “Future of Computing: Energy-Efficient Computing for AI and Beyond” forum will bring together executives and thought leaders across the entire ecosystem – including design, fabrication, interconnects, system integration, hyperscale architectures, advanced materials, and emerging technologies such as photonics and quantum. Attendees will have a unique opportunity to get strategic perspectives from these distinguished experts and learn about exciting future trends.Why Attend?Gain insights from global leaders and learn about innovative paths towards an energy-efficient computing future.Network and build cross-industry collaborations for the next wave of AI, photonics and quantum.Promote a more sustainable path for continued growth of AI to benefit humanity and the planet.Join the SEMI Smart Data-AI initiative to develop solutions and take concrete actions to reduce AI’s growing energy footprint.Support the industry in achieving its goal of reaching $1 trillion in revenue. Speaker Highlights Include:AMD • Ciena • Hewlett Packard Enterprise • IBM • Merck KGaA, Darmstadt, Germany •Microsoft • Quantum Economic Development Consortium • Rapidus • Rigetti •Siemens AG • Stanford UniversityDr. Pushkar P. Apte is the Strategic Technology Advisor and leads the Smart Data-AI Initiative at SEMI.

Digital Twins are no longer a futuristic concept in semiconductor manufacturing—they’re fast becoming the backbone of next-generation fabs. But here’s the challenge: without a robust, scalable data platform to unify, secure, and interpret the torrent of information flowing across design, manufacturing, packaging, and test, digital twins cannot deliver their transformative potential. At SEMICON West in Phoenix, Arizona on October 6, 2025 from 1–5 p.m., join us for a high-impact technical workshop that explores how advanced data platforms are fueling the next wave of innovation—enabling smarter, faster, and more precise decisions across the semiconductor lifecycle.What You’ll Learn – Gain insights on proven reference architectures for scalable data platforms, integration patterns that support digital twin ecosystems, real-world use cases from fabs and OSATs applying AI/ML at scale, best practices in managing governance and security across complex data pipelines.Modern Data Platform Architectures – Designed for speed, scale, and semiconductor precisionBreaking Down Silos – Leveraging shared ontologies and data fabrics for seamless interoperabilityAI-Enhanced Digital Twins – Real-world deployments across fabs and OSATsFederated Learning in Action – Secure, multi-party collaboration without compromising IPData Security Governance – Proven practices for high-stakes manufacturing environments Distinguished Speakers – Hear directly from leaders advancing digital twin and federated learning initiatives at the SmartUSA Institute and across the semiconductor ecosystem. Anshu Bahadur, Senior Program Manager, Technology Communities at SEMI, will open the workshop and introduce speakers who will share how they’re building these next-generation platforms and deploying them across fabs, OSATs, and the full manufacturing flow. Following individual presentations, the session will close with a panel discussion featuring these executives. Ross Kunz, Director of Technology, SmartUSA Institute (Keynote Speaker)Dr. Adam Schafer, CEO, Athinia TechnologiesDhara Vaishnaw, Head of Solution Architecture, AWSDr. Gautham Unni, Head of Solutions and Business Development, Semiconductor, AWSJonathan Holt, Senior Director, Product Management, PDF SolutionsDr. Surya Kalidindi, CEO, Multiscale TechnologiesWho Should Attend? This workshop is designed for: Data Platform Architects building the next-gen semiconductor backboneSmart Manufacturing Engineers integrating fab and test dataAI/ML Practitioners scaling models into production workflowsInnovators shaping digital twin systems for complex, high-precision manufacturing Why Attend? Because the future isn’t waiting. Digital Twins, powered by scalable data platforms, are redefining how the semiconductor industry innovates, collaborates, and competes. Don’t just keep up with the future—build it. Anshu Bahadur is Senior Program Manager, Technology Communities at SEMI

John Kibarian, CEO and co-founder of PDF Solutions and a member of the ESD Alliance (ESDA) Governing Council, will deliver a keynote during the CEO Summit at SEMICON West in October titled, “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms.” He recently shared with me a summary of what his talk will cover and his perspective on why collaboration is the key to growing the semiconductor industry to $1 trillion and how we will get there.Smith: What is the major industry evolution or dynamic that's making collaboration essential today?Kibarian: The semiconductor industry has dramatically evolved from a simple, linear process to a complex, collaborative ecosystem. Previously, everything happened at the wafer fab. Testing occurred at wafer sort, package yields were high, final testing was straightforward, and products were shipped. Collaboration was mainly between foundries and fabless customers, intensive during early qualification and test chip stages, then evolved to routine yield monitoring once production stabilized.Today's advanced packaging puts multiple chiplets into single packages, creating an explosion of test insertion points. This has driven up both test complexity and costs significantly. Front-end fabs now house the most complex machines, while test and assembly facilities, once relatively simple, now feature sophisticated system-level testers with integrated robotics. Assembly tools have become highly complex, with die-attach processes requiring increasingly tight tolerances. Success now requires collaboration across the entire chain, from system companies to equipment vendors, both for new product launches and ongoing production maintenance.Companies are adopting AI and machine learning (ML) to manage these complex production flows, whether for testing or equipment control. This demands even broader collaboration since AI requires combining data from multiple sources across foundries, fabless companies, OSATs, equipment vendors, and more, data that no single entity controls. What was once a straightforward handoff between two parties has become an intricate web of interdependent relationships requiring continuous coordination.Smith: Chiplets and chiplet-based architecture is in the news and seems to be a key solution or practical solution in response to the slowing down of Moore's Law. This demands incredible levels of collaboration and coordination across the whole value chain. Is this doable at scale where it starts to move into the mainstream?Kibarian: The semiconductor industry will need unprecedented collaboration to make chiplet manufacturing work at scale. But this can be done! Consider EUV lithography: Initially expected during the 65nm generation, it took years longer than anticipated despite being an incredibly complex technology. Extraordinary engineering was needed but it also required extensive collaboration between ASML, suppliers, customers, and the broader fabless community.If the industry achieved this level of coordination for EUV, it can do the same for chiplets. However, chiplet manufacturing will require even greater collaboration as more companies will build systems using chiplets from multiple suppliers.Today's chiplet-based systems typically source all components from one manufacturer, making standards like UCIe less critical since companies control their entire supply chain. This will change as companies increasingly use third-party components for cost-effectiveness.More and more, we will see systems using components from multiple players to get to market more cost-effectively. Consequently, future production flows will be significantly more complex, requiring coordination of substrates and base dies, third-party dies and interposers, OSAT and specialized testers with specific configurations.This orchestration must work not just for initial bring-up but for the ongoing production as well, and when reconfiguring chiplet combinations for different products, all requiring rapid, automated responses.All of that must be automated for quick reaction. Considering the complexity of the manufacturing flow, people will want to apply AI/ML to anticipate what is going on in each individual product built.Manual oversight of every chip and package during manufacturing isn't feasible at scale. Automated AI agents must handle this monitoring and quality control. Expanding this automation will require close collaboration between the manufacturing entity and engineering teams at the product companies.This will also require a different level of alignment and orchestration across all the software packages managing this complex multi-company process. The financial enterprise resource planning (ERP) systems know where material is going, what the demand is, and what the forecasts are. While separately, the manufacturing execution systems needs to know which tools are going to be available when. Most often, these manufacturing systems operate in factories the product company doesn't own. The product company’s PLM systems control the bill of materials and test flows, but these tests will be conducted at the OSAT requiring complex coordination between the software systems of multiple companies controlling different process domains. This orchestration spans organizational boundaries and must be able to take data from upstream test results and make decisions on what tests to run downstream. This is required to get the right chiplets put together into a package in an efficient manner within a short cycle time and not require a Formula 1 pit team to keep everything running.Smith: The volume of data is staggering, especially now with design data. What will it take to enable this vision, at scale, where everything's connected? Kibarian: It’s a marriage of the human establishing the bounding box within which the systems operate that employ agents to do a lot of the work on a day-to-day or hour-by-hour basis. A good example is how manufacturing execution systems (MES) connect to ERP systems to share data. When a company sets up an orchestration, it creates rules that govern how information flows between systems. These rules tell the ERP system: "To calculate costs for each process step, here's the recipe information you should use."Once these rules are in place, they work like guidelines that control daily operations. An AI agent automatically creates insights based on actual data collected from the MES and moves data between systems according to these rules. The ERP AI agent will use this data to spot when costs are rising and send alerts, to notice when production yields drop, to calculate what lower yields mean for costs, and will take action to fix problems.This same process happens between equipment suppliers and manufacturing facilities. They share data automatically based on pre-set rules, and AI helps identify issues and take corrective action. Fabs determine who can access which machines and when, what types of data can be transmitted and through which channels, and how frequently these transmissions occur. When new software or AI models are introduced to run equipment, the systems specify what virus scanning and security checks must be completed before installation.Human operators primarily configure these control systems by determining the most effective collaboration protocols. However, the day-to-day execution is handled by automated agents due to the enormous scale involved, both in terms of data volume and the sheer number of transactions that occur continuously throughout operations.A human will not go through and review that data. I'll give two examples of this. One outside of our industry and one in our industry. At our 2019 user conference, board member Marco Iansiti, a Harvard Business School professor, shared insights from his book on AI in business. He compared traditional banks with Ant Bank, Alibaba's banking arm, which was experiencing explosive growth before Chinese government intervention.Ant's AI wasn't particularly sophisticated, but its process was revolutionary. While traditional banks require customers to fill out loan applications that then go to human loan officers for review, Ant's system would automatically scrape the internet and social media to verify applicant information. Within seconds, an algorithm would approve or deny the loan.The crucial difference is that Ant could scale exponentially because its only constraint was computing power. Traditional banks need to hire more loan officers to double their business, a human bottleneck that limits growth.I invited him to speak because I believed in this principle six years ago, and I'm even more convinced now.For the semiconductor industry, to build a trillion-dollar industry with complex, integrated systems, we need to minimize human intervention in data intensive processes. Despite the trust issues between stakeholders in our sector, collaboration remains essential. The solution requires establishing systematic principles that allow AI agents to operate autonomously. This is a way forward to achieving exponential growth.The Ant Bank example perfectly illustrates what our industry needs. At PDF, we believe this approach is crucial for industry advancement. Consider this: We manage petabytes of data, yet humans only examine 5-10% of it. This shows AI's potential to handle the vast majority of operations without human oversight.The reality is that our customers build millions of chips a week, billions a year. They cannot look at every dataset. Algorithms can, AI can. We launched a product called Guided Analytics last year. An engineer spoke about it during our user group last year. Her company has a couple of thousand products. Her group could not keep track of them every day, but Guided Analytics could. When her group came in the morning, the daily report noted 90% of the chips were fine or alerts pointed to where issues are. It's a simple AI bot crawling over data and identifying where the root cause seems to be.Our industry will require more agents to scale. Those agents will span the industry, and yet we as humans need to set up the governing principles under which they can operate. That's how we're going to deal with the massive amounts of design and manufacturing data to get the velocity the industry will need, and to benefit from the AI that we create for our businesses.Notes: Kibarian’s keynote, “Revolutionizing Semiconductor Collaboration: The Emergence of AI-Driven Industry Platforms” is scheduled for Wednesday, October 8, at 10:20 a.m.SEMICON West adds design to its program with “The Convergence of Semiconductor Manufacturing and Design” to highlight the collaboration between semiconductor manufacturers and chip design teams to bring advanced systems to market. The three-hour session will be held Tuesday, October 7, from 1 p.m. until 4 p.m. Learn more about the design program in our latest blog. SEMICON West 2025 will be held in Phoenix, Arizona from October 7-at the Phoenix Convention Center. SEMICON West’s homepage has links to the full program, including more details about “The Convergence of Semiconductor Manufacturing and Design,” special features, sponsor and exhibits. Registration is open. About John KibarianJohn K. Kibarian is President, Chief Executive Officer and Co-Founder of PDF Solutions. He has served as President since 1991 and CEO since 2000. Dr. Kibarian received a Bachelor of Science degree in Electrical Engineering, a Master of Science and PhD degrees in Engineering Computer Science from Carnegie Mellon University.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

Electronic Design Automation (EDA) financial analyst Jay Vleeschhouwer, Managing Director of Software Research at Griffin Securities, carefully tracks the design portion of the semiconductor industry and offers insightful analysis used by this community. He also presents the State of EDA, a yearly report on EDA, during the Design Automation Conference (DAC). After this year’s presentation, he and I talked about trends, the difference between EDA and Architecture, Engineering, and Construction (AEC), security and chiplets. A condensed version of our talk follows. Smith: Now that the Synopsys-Ansys merger closed, what changes? Vleeschhouwer: Synopsys is now the largest company by revenue and backlog in all of Engineering Software, a well over $30-billion industry, including all the parts of that market—AEC, EDA and Technical Software. The pro-forma backlog, about $9.84 billion as of the most recently reported quarter, is the largest in the industry. An important question is how will Synopsys integrate, employ and leverage the four-fifths of Ansys that is not strictly EDA? That is, other than Ansoft and Apache, the two entities that mostly comprise Ansys' EDA, and that ties into the convergence theme. Also, the question in any acquisition is the balance between leaving the operations and the portfolios as they were, or not. In other words, let them continue doing what they were doing if they were doing it well or quickly absorbing, integrating and leveraging those portfolios into the buyer's portfolio. That roadmap is something that we would be interested in hearing more about in terms of its purely EDA aspects and as well the convergence aspects.Smith: Have you observed any new trends in 2025 that surprised you? Vleeschhouwer: The short answer is that it's more of the same in terms of the main technical and business trends. Of course, the most recent important exogenous effect is the advent of tariffs and new export restrictions, or the variability around export restrictions. That's perhaps the main thing that's occurred in the last few weeks and months. We're seeing a continuation of trends that have been in place for a number of years in terms of many of the technical and business results that we've highlighted in our reports. From industry data, there continues to be multiple EDA categories that are continuing to grow. It’s observable and important that we see this breadth of product adoption and growth across multiple categories. This has been beneficial to each of the four largest EDA companies. There have been compelling technical reasons for this, and I would expect it to remain the case. In terms of those significant multi-year trends, the answer would be no. Otherwise, in terms of 2025 specifically, the thing that was interesting about this year’s DAC was the presence of more startups, something that we've not seen in EDA for a long time. It's interesting that we are seeing startup activity not only in EDA, but even in one of the other areas of Engineering Software that we cover: AEC has little to do with semiconductors and electronic systems and it too has more startup activity than we've seen for about a quarter of a century. Although the rationales for the startups in these two different areas of Engineering Software are quite different. The rationale for the EDA startups is one set of rationales, whereas in the case of AEC, it's different, which to me is analytically interesting. Smith: What is the difference between the rationales for startup activity in EDA and AEC? Vleeschhouwer: AEC has to do with the design and construction of commercial buildings, residential buildings, infrastructure, meaning roads, bridges, airports, tunnels, civil engineering, public works. Among the companies that we follow in those markets are Autodesk and Bentley Systems. Autodesk has a small connection to EDA because one of their mechanical CAD products has some integration with some PCB design tools. In any case, the rationale for startups in AEC that we've seen has mostly to do with what has been some vocal dissatisfaction with the incumbent or large incumbent products. That's different from EDA, where we can’t make a case that there is dissatisfaction or sufficient dissatisfaction with the incumbent tools that would necessitate, or be a catalyst, for startups. What we're seeing here is the ongoing, complex, rapid evolution of semiconductor design and electronic systems design because of the unusual breadth of EDA tools and functions, far more so than in AEC. There's much more opportunity for niche products to perhaps complement existing tools. As you know, it can be difficult to dislodge an existing tool in EDA. The industry has become consolidated among the big four—Ansys, Cadence, Siemens EDA and Synopsys—and now three with Synopsys/Ansys merger. Backlogs have continued to grow and book-to-bill has been positive for 15 years. It’s hard to infer any dissatisfaction with incumbent tools or insufficient satisfaction showing up in the numbers. Whereas in AEC, it's different in terms of the profile of the customers or the way the tools are used. There are far more customers than in EDA—thousands upon thousands of architectural firms and construction firms and so forth. The installed base of the AEC software is an order of magnitude more than in EDA. It just so happens that there was one tool from Autodesk that has been getting considerable attention from customers in terms of how modern it is and so forth. This created an opening for some startups. Notwithstanding the nominal dissatisfaction with this tool, however, that particular brand continues to grow. It has the largest base in the industry. At the end of the day, the largest product of its kind in the market continues to grow at a decent rate. The vendor in this case, Autodesk, has acknowledged some of the things needed to do to improve the tool, and it's investing toward that. In any case, there are differences in why these startups exist, how they're approaching the market.Smith: The big topics now are 2D and 3D and chiplets. Where is the market relative to chiplet-based design? Vleeschhouwer: It’s still early, based on commentary from the EDA vendors, about developing and delivering the tools. I don't have a precise measure as to how much of the business is attributable to it. It’s still something that has a considerable runway, which is a good thing. As more tools that can enable it come together, then we'll continue to see this cycle of enablement and delivery. That phenomenon will continue to grow. We would love to hear the vendors’ provide more precise attribution in terms of how much of the business is coming from this. For investors, it will be incumbent upon the vendors to be more explicit about the contribution from the new technical phenomena because it is a new growth catalyst. Smith: The ESD Alliance is starting to see more interest in securing the design flow. This is a huge issue. The design flow is more complex and it's going to require cooperation, collaboration and new standards. Vleeschhouwer: Yes. Siemens EDA is the largest in classical product lifecycle management (PLM) or managing the whole process, an important issue for the industrial and manufacturing markets with its Teamcenter product. Interestingly, Siemens EDA still has work to do to integrate Teamcenter with Calibre, which would seem to have been a natural thing to have done, and I think still is. Teamcenter and Calibre are the two billion-dollar brands that Siemens Industry Software has as an entity. Calibre is by far the predominant product of its kind for semiconductor manufacturing. It's got at least two-thirds market share. Teamcenter is the market leader in classical PLM. The connection between those two brands, owned by the same company, would be an interesting executable to observe.About Jay Vleeschhouwer  Jay Vleeschhouwer, Managing Director of Software Research at Griffin Securities, has more than 40 years of research analyst experience in the technology sector, including software, semiconductors and computer hardware. Vleeschhouwer does a yearly presentation on the State of EDA during the Design Automation Conference (DAC). The slides can be found at: DAC presentation (June 2025) 2.pdf Note: The ESD Alliance will host a three-hour design track “The Convergence of Semiconductor Manufacturing and Design” Tuesday, October 7, from 1 p.m. until 4 p.m. during SEMICON West in Phoenix, Ariz. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

As the volume of regulations grows across all levels of government, both in the U.S. and abroad, the semiconductor industry is increasingly struggling to keep up with its reporting obligations. Potential consequences include shipments delayed by customs, existing stocks of materials, parts, and components unexpectedly being made obsolete, and disruptions to multiple tiers of the supply chain that persist over time.To minimize the burden of numerous, varied reporting expectations, the SEMI PFAS Transparency Working Group, led by Intel and Tokyo Electron, is working to:Enable standardized communication on the presence of Per- and polyfluoroalkyl substances (PFAS) in chemical formulations, materials, tools, parts, and fab infrastructure to minimize the burden of varied reporting expectations;Enable traceability; andProtect confidential business information. While the initial focus of the effort is on PFAS, the intent of the group is for the methodology to be applicable to other substance reporting requirements.The group will be holding a working session at SEMICON West in Phoenix, Arizona on Wednesday, October 8 from 10:30 a.m.-12:00 noon at the North Building, 200 Level, Room 229A of the Phoenix Convention Center. All segments of the semiconductor manufacturing supply chain are invited to join the meeting and contribute to this critical effort. This session is intended for individuals involved in: Data management and reportingSupply chain managementMajor business continuity planning and crisis managementRisk assessment and mitigationEHS/regulatory complianceSub-supply chain visibility challengesThe PFAS transparency effort will also be introduced during the SEMI EHS Summit and SEMI Global Standards Summit, both scheduled on Tuesday, October 7.For additional resources, download the PFAS Explainer or SEMI PFAS Position Paper. Contact [email protected] for questions or more information about the working group session.James Amano is Senior Director of EHS at SEMI.