Technology and Trends

RF-SOI is in every smart phone out there, and with 5G, there are lots more applications on the horizon. If you’d like to learn more about designing in RF-SOI, there’s a great short course coming up the day before and in conjunction with the EuroSOI-ULIS Conference in Granada, Spain.The title of this short course is RFSOI: from basics to practical use of wireless technology. Program and registration details can be found here. The course runs for the full day on Sunday, 18 March 2018.The talks, which are being given by a stellar line-up of experts, include: RF SOI, fabrication, materials and eco-system - Ionut Radu Director of Advanced R D, Soitec Fundamentals of RF SOI technology - Jean-Pierre Raskin, Professor, UCL 22nm FDSOI Technology optimized for RF/mmWave Applications - David L. Harame, RF CTO Development and Enablement, GlobalFoundries RF SOI technology and components for 5G connectivity - Christine Raynaud, Program Manager (Business Development – Technology to Design), CEA-Leti Analog and RF design on SOI - Barend van Liempd, Senior Researcher, imec Techniques and tricks for RF measurements on SOI - Andrej Rumiantsev, Director RF Technologies, MPI Corporation FOSS TCAD/EDA tools for advanced SOI-device modeling - Wladek Grabinski, R D CM Manager, MOS-AK RF design flow for SOI - Ian Dennison, Design Systems Senior Group Director, Cadence The course is being organized by SOI Consortium members Incize and Soitec. BTW, this year marks the 4th joint EUROSOI – ULIS Conference. The EuroSOI Conference, which has been ongoing for decades, is well paired with the ULtimate Integration on Silicon Conference. The joint conference provides an interactive forum for scientists and engineers working in the field of SOI technology and advanced nanoscale devices. One of the key objectives is to promote collaboration and partnership between different players from academia, research and industry. As such, it covers technical topics, industry trends and updates from pertinent European programs. EuroSOI-ULIS will take place 19–21 March 2018 at the University of Granada in Spain. For information on the program and how to register, see the website. Following the conference, the papers will be available at the IEEE Xplore® digital library, and the best papers will be published in a special issue of Solid-State Electronics.

GlobalFoundries' 45nm RF-SOI platform is qualified and ready for volume production on 300mm wafers (read the company's full press release here). It was just at the beginning of last year that GF announced the PDK availability for 45RFSOI (we covered it here). Now there are several customers engaged for this advanced RF SOI process, which is targeted for 5G mmWave front-end module (FEM) applications, including smartphones and next-generation mmWave beamforming systems in future base stations. In case you missed it, at the Consortium's Shanghai symposium GF's Mr. RF -- Peter Rabbeni -- gave a great talk on the company's RF-SOI capabilities, which are very impressive (they've shipped over 32 billion RF-SOI devices, after all). His slides from that day are available here on the SOI Consortium website. See his slide 12 for an indication of how 45RFSOI fits into the overall picture. [caption id="attachment_11482" align="alignnone" width="768"] Slide 12 from Peter Rabbeni's talk at the RF-SOI Symposium in Shanghai. (Courtesy: GlobalFoundries and the SOI Consortium).[/caption] As they explain it, next-generation systems are moving to frequencies above 24GHz, so higher performance RF silicon solutions are required to exploit the large available bandwidth in the mmWave spectrum. GF’s 45RFSOI platform is optimized for beam forming FEMs, with features that improve RF performance through combining high-frequency transistors, high-resistivity SOI substrates and ultra-thick copper wiring. Moreover, the SOI technology enables easy integration of power amplifiers, switches, LNAs, phase shifters, up/down converters and VCO/PLLs that lowers cost, size and power compared to competing technologies targeting tomorrow’s multi-gigabit-per-second communication systems, including internet broadband satellite, smartphones and 5G infrastructure. Psemi and Anokiwave are among those companies at the forefront of 45RFSOI use. Citing the drive to deliver faster, higher-quality video, and multimedia content and services Anokiwave CEO Bob Donahue said, “GF's RF SOI technology leadership and 45RFSOI platform enables Anokiwave to develop differentiated solutions designed to operate between the mmWave and sub-6GHz frequency band for high-speed wireless communications and networks.” The production line is in East Fishkill, N.Y.

ASN asked Carlos Mazure and Giorgio Cesana, the Executive Directors of the SOI Consortium, to take a moment to share their outlook for 2018. Here’s what they had to say. First of all, we’d like to wish everybody in the SOI ecosystem a safe, happy and prosperous 2018. We just finished up a great year, and now look forward to exciting prospects in the months to come. Taking a quick look back, 2017 was marked by significant growth for RF-SOI markets, and with key product announcements for FD-SOI (accompanied by a very positive change in how it is viewed). In both domains, the foundries announced their roadmaps, so now the current sweet spots and future directions are clearly established. Let’s take a moment to consider RF-SOI. As those following wireless markets know, RF-SOI has been the basis for antenna front-end modules in all the world’s smart phones for a few years now. With 2018, we see the industry turn its attention to 5G, with sub-6GHz in priority but also addressing the mmW space. Thanks to various flavors of RF-SOI, and RF integration in FD-SOI, we’ll move into a new phase where wireless will get faster and lower power than ever before. This will be a hot topic in both the SOI Consortium symposiums around the world this year, and in articles coming your way here in ASN. Another hot topic will be exciting new products coming out on FD-SOI. Chip design and manufacturing is of course always a fairly long process, and we’ve talked about the importance of building the ecosystem over the last few years. Now, a good ecosystem is in place. The design tools are ready and validated at the fabs, and key IP is ready. Of course with time there will be more and more IP, but lack of IP is no longer a barrier to design starts. Embedded memory – eMRAM – is another subject that designers want to learn more about, so that will be part of what we’ll be covering. [caption id="attachment_11476" align="alignleft" width="247"] Photo courtesy: SOI Consortium / Adele Hars[/caption] Last year we saw a growing list of successful FD-SOI tape-outs. In 2018, these chips will be ramping in volume. So this year, we look at products. We’ll be inviting those companies that are ramping in silicon to present their chips at the various symposia we organize around the world: Silicon Valley in the spring, Tokyo in the summer, China in the fall. Our symposia will again be accompanied by tutorial days, which have been very popular and successful. In this year’s tutorials there will be a particular focus on RF, analog and mixed-signal design, and they’ll dive deeper into how to use back biasing techniques for further boosting performance and lowering power. So we’re at the beginning of what should be a very exciting year. We’d like to take a moment to thank all the member companies in the SOI Consortium for their enthusiastic support. And we look forward to welcoming new members over the course of this year. With warm regards, Giorgio Cesana and Carlos Mazure Executive Directors of the SOI Consortium

Long promised by science fiction stories, we're now at the threshold of a real revolution where sensors, flexible electronics and printed batteries could finally be playing a key role in the way people mediate their social image through fashion. As an industry veteran, I trust that fashion—not industrial designers—will be in charge of designing successful form factors (plus, it won't be long before IBM Watson helps quantify the "cool" index", the "chic" index, the "comfy" index of any given product).The global apparel market is valued at US$3 trillion, accounting for two percent of the world's GDP. Premium and luxury segments are doing well. In fact, The McKinsey Global Fashion Index forecasts industry sales growth to nearly triple between 2016 and 2018, from 1.5 percent to between 3.5 to 4.5 percent. Yes, some still regard fashion as a frivolous topic, instead of the social identity tool it has always been. It is especially powerful with Millennials, for whom it belongs to pop culture, like social media, music, TV series, sports or gaming.Photo: The author's display on the intersection of fashion and tech at Collette, a luxury retail store in ParisThis in fact might have been the missing key of success for the first generations of "wearables". Although they started by targeting the fashion market, they somehow missed seducing the prestige market. No doubt that their current re-marketing shift into the health sector—especially obvious during the recent CES—will make these devices more relevant and sought-after tools.But as they're stepping into their smart age, fashion brands will have to be more proactive in understanding and integrating electronics. Most of the luxury groupsin Europe and the US have opened some sort of tech pathway. But what about the indie designers, usually the most creative and copied talent of the fashion industry? How can they even dream of getting to the Silicon Valley designers and integrators, with their $500K to $1M prototype price tags?This is why I am excited to be leading the messaging to these brands on the electronics developments and their implications. I am participating at technology industry events (including the upcoming 2018FLEX in Monterrey, California) to gather my own data. Some of the things I am excited about: In a couple of years, mixed reality goggles will miniaturized enough to become a chic accessory on my nose, branded by Saint Laurent or Dior, powered by ODG or Ostendo Technologies. My fashion friends won't be troubled any longer by the "douchetooth" look coming from their Apple Airpods: Cartier Smart Jewelry will work its magic on chic hybrids, gold earrings/airbuds. Instead of lighting Lady Gaga's dresses, designers will finally turn the LEDs inside our garments for a discreet pro-collagen treatment. The NBA Nike jerseys will collect sweat, via fabrics powered by bacteria and movements. Those athletes' biometrics data will be a bounty for coaches and doctors eager to prevent health issues. At home, the NFC tag of my coat will remind me that it could use laundry. All my electronics will power on-the-go thanks to induction charging hidden (printed? woven? embroidered?) in my pockets. Which of these trends can you help start? Send me an invite to meet with you at 2018FLEX! Download the 2018FLEX app to request meetings with any attendees!

EDA companies Cadence, Synopsys and Silvaco all gave excellent presentations at the SOI Consortium forums in Nanjing and Shanghai.Here's a recap of what the Cadence folks said. (I'll cover the Synopsys and Silvaco presentations in my next posts.)Design WinsAt the Shanghai FD-SOI Forum. Dr. Qui Wang, VP Chief of Staff, talked about FD-SOI Foundry Enablement: From Concept to Mass Production. Cadence, he reminded the packed ballroom, is not just EDA, but also system design enablement targeting verticals. “We’re ready!” he stated.In the last three years, they’ve done a lot of work on FD-SOI, he said, even working with ARM, GF and Dream Chip on the demo board as a reference design for automotive or vision applications, to show real data to their customers. It uses a quad implementation of the configurable Tensilica Vision P6 core.To simplify back biasing for the library folks, they worked with the foundries to create interpolations. And as Cadence is traditionally strong in RF/mixed-signal, there’s a new back-biasing tool to simplify board-chip communications, and make the bridge between power and thermal analysis.Cadence Has It All Jonathon Smith, Director of Strategic Alliances at Cadence, presented Enabling an Interconnected Digital World -- Cadence EDA IP Update at the Nanjing SOI summit. As he explained, his job is to ensure that design customers can use Cadence tools effectively, not just with Cadence IP, but also with 3rd party IP for the foundry nodes.He pointed out that the numbers for IoT predictions vary widely, and that industrial IoT (IIoT) will probably account for about 10% of the market. What is sure is that it will contain a large mixed-signal component (RF/digital/analog) and complex packaging.His customers want to know how fast and easy it is to work in FD-SOI. “Cadence custom and digital tools are ready for FD-SOI,” he said. They have the PDKs and tech files, and the EDA tools are enabled. The reference flows (both digital and custom analog) are tested and ready (Cadence customers who use p-cells and RF look especially for a good mixed-signal flow). [caption id="attachment_11432" align="alignnone" width="768"] EDA requirements for FD-SOI are complete. (Courtesy: Cadence SOI Consortium)[/caption] Customers also ask for proof points, and want to know the number of tape-outs they’ve done, performance benchmarks for working silicon and proven IP: this is what gives designers confidence, he said. Examples like Dream Chip’s Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FD-SOI (which they announced at Mobile World Congress in 2017 – see the press release here) have really helped build confidence further, he observed. (In case you missed it, DreamChip presented at the Silicon Valley SOI event in April 2017 – you can get that presentation here.)Cadence sees SOI as a driving force in IoT markets. They’ve also had some big digital wins recently, he added, and have made some major announcements with the foundries.For example, in September, they announced that their set of Design for Manufacturing (DFM) tools (signoff solutions) are now qualified on Samsung’s 28nm FD-SOI. This enables customers to create complex, advanced-node designs for the automotive, mobile, IoT, high-performance compute (HPC) and consumer markets (read the press release here). The Samsung Foundry's PDKs for 28nm FD-SOI are available for download now and incorporate the Cadence Litho Physical Analyzer (LPA), Physical Verification System (PVS) and Cadence CMP Predictor (CCP). In addition to signoff quality, the Cadence DFM tools offer an integration with the Virtuoso® platform and the Innovus™ Implementation System, providing designers with automated fixing capabilities and overall ease of use.And in October, Cadence announced that its digital and signoff flow, from synthesis to timing and power analysis, supports body-bias interpolation for GlobalFoundries 22FDX™ (read the press release here). The Cadence® tools enable advanced-node customers across a variety of vertical markets—including automotive, mobile, IoT and consumer applications—to use GF’s FD-SOI architecture to optimize power, performance and area (PPA).Cadence tools for ST’s 28nm FD-SOI foundry process were ready in 2016, btw – there’s a nice video testimonial from ST on power signoff, for example, which you can see here.

Big News: Samsung has officially revealed that their next FD-SOI node is 18nm. The announcement was made at the recent Samsung Foundry Forum, which showcased a number of new technologies that the company says will help enable the development of new devices connecting consumers in entirely new ways. (You can read the full press release here.) Samsung also announced new features for its 28nm FD-SOI offering, which is called 28FDS. Noting that it is well suited for IoT applications, Samsung said it will gradually expand its 28FDS technology into a broader platform offering by incorporating RF and eMRAM(embedded Magnetic RAM) options. 18FDS is the next generation node on Samsung’s FD-SOI roadmap with enhanced PPA (Power/Performance/Area). [caption id="attachment_10762" align="alignnone" width="705"] Kinam Kim, President of Samsung Electronics’ Semiconductor Business, introduces the company’s newest foundry process technologies and solutions. (Courtesy: Samsung)[/caption] The FD-SOI news was part of an announcement covering Samsung's newest process technology roadmap. “The ubiquitous nature of smart, connected machines and everyday consumer devices signals the beginning of the next industrial revolution,” said Jong Shik Yoon, Executive Vice President of the Foundry Business at Samsung Electronics. “To successfully compete in today’s fast-paced business environment, our customers need a foundry partner with a comprehensive roadmap at the advanced process nodes to achieve their business goals and objectives.”

Prior to 1997, the industry enjoyed the “mask maker’s holiday” when IC feature sizes were larger than the lithography wavelength and the industry enjoyed the number of transistors per area doubling for no additional cost. This era ended when 248nm lithography was adopted. 248nm lithography enabled device manufacturers to extend traditional optical lithography but forced the adoption of resolution enhancement techniques such optical proximity correction and phase shift masks. 193nm lithography was introduced for 90nm features and the industry was required to adopt increasingly complex strategies to shrink device geometries further such as liquid immersion, double patterning, and more recently multiple patterning. These techniques have enabled device manufacturers to extend traditional optical lithography while next-generation lithography approaches, including extreme ultraviolet (EUV), maskless lithography, and nanoimprint remain in the background.EUV is the most favored next-generation lithography and has received the lion’s share of press and research dollars. EUV was initially scheduled to be used for 65nm feature processing but persistent challenges with this technology remain unsolved. Key obstacles associated with EUV are: finding adequate source power, EUV photoresists, and developing mask manufacturing infrastructure. Significant progress has been made and there are now beta EUV tools in the field. The extended delay of EUV forced chipmakers to extend 193nm immersion lithography with multiple patterning down to sub-10nm. With so much invested in optical lithography, even when EUV is ready, it is expected that chip makers will use a combination of EUV and 193nm immersion with multi-patterning for leading-edge devices.The delay in EUV for volume production has impacted the photomask market. Last month, SEMI reported that the worldwide semiconductor photomask market recorded a record high in 2016, reaching $3.32 billion. SEMI also noted that captive mask suppliers have significantly increased their market share due to the capital intensity required by leading-edge manufacturing.It remains to be seen what lithography solutions the industry will implement to maintain Moore’s law as the costs of advanced lithography increase faster than increased device density gains. What is clear is that the photomask market is mature and that captive shops, with their deep pockets, are assuming an increasingly important role. Still merchant shops continue to serve a vital function by servicing standard mask sets and providing manufacturing capability in the event of a service disruption.A recent SEMI published report, Photomask Characterization Summary, provides details on the 2016 Photomask Market for seven regions of world including North America, Japan, Europe, Taiwan, Korea, China, and Rest of World. The report also includes data for each of these regions from 2003 to 2018 and summarizes lithography developments over the past year.Please click here to download a copy of the SEMI Photomask Market Characterization Executive Summary. For information on all SEMI Market Information, visit: www.semi.org/en/MarketInfo.

They're calling it, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” It's NXP's new i.MX 7ULP general-purpose processor, and it's on 28nm FD-SOI. They've got a nifty video summing it all up – you can watch it here. [caption id="attachment_10388" align="alignleft" width="300"] NXP is first to market with a general-purpose processor on FD-SOI: the i.MX 7ULP. It's got both ultra-low power consumption and rich graphics for battery powered applications. (Courtesy: NXP)[/caption] With the i.MX 7ULP, NXP is first to market with an FD-SOI applications processor offering the industry’s lowest power consumption. The debut was made at the recent Embedded World Conference in Nuremberg, Germany, and it made a big splash in media across the globe. (Read the full press release here.) In deep sleep mode, it boasts power consumption of just 15 uW or less: 17 times less than previous (and highly successful) low power i.MX 7 devices. Dynamic power efficiency is improved by 50 percent on the real-time domain.The i.MX 7ULP applications processor family is currently sampling to select customers. Broader availability of pre-production samples is scheduled for Q3 2017.Hello, IoT!The high-performance, low-power solution is optimized for customers developing applications that spend a significant amount of time in standby mode with short bursts of performance-intense activity that require exceptional graphics processing. Sounds like IoT – and indeed it is, and more.With the i.MX 7ULP, NXP's targeting wearables, portable healthcare, smart home controls, gaming accessories, building automation, general embedded control and IoT edge solutions. Bottom line: it's designed to enable ultra-low-power and secure, portable applications – especially those demanding long battery life. (Read the current fact sheet here.)The detailsThe i.MX 7ULP features an advanced implementation of the ARM® Cortex®-A7 core, the ARM Cortex-M4 core, as well as a 3D and 2D Graphic Processing Units (GPUs). It's got a 32-bit LPDDR2/LPDDR3 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera sensors. [caption id="attachment_10387" align="alignnone" width="834"] (Courtesy: NXP)[/caption] NXP says this new design, based on FD-SOI’s lower voltage capability, enables rich user experience through extremely power-efficient graphics acceleration, a fundamental requirement in many of today’s consumer and industrial battery-operated devices that incorporate robust graphic interfaces. Further enablement includes rich Linux or Android ecosystem with the real-time capability supported by FreeRTOS.Leveraging body biasing and moreNXP credits the design’s extreme low leakage and operating voltage (Vdd) scalability to that FD-SOI specialty: reverse and forward body biasing (RBB/FBB) of the transistors, and its smart power system architecture.In presenting the new i.MX 7ULP to the tech press, the company highlighted the following FD-SOI design advantages: Large dynamic gate and body biasing voltage range Domain and subsystem optimization with custom standard cell library with mixed voltages Low quiescent current (Iq) bias generators Enhanced ADC performance with unique FD-SOI attributes Fail Safe I/O for simplified low power system design To that, add a note about security. As the chip's fact sheet says, “The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption secure boot, and tamper detection.” Those are just the sort of things that demand the bursts of high performance that dynamic forward body biasing delivers where and when it's needed.Samsung fabs, Verisilicon adds IPTwo other SOI Consortium members – Samsung and Verisilicon – are particularly pleased with NXP's results.“We are excited that NXP is the first to bring the benefits of FD-SOI (28FDS) technology to the general purpose market,” says Ryan Lee, VP of the Foundry Marketing Team at Samsung Electronics. “28FDS technology will satisfy a growing and critical need for ultra low power designs that require power-performance at very low voltages. We plan to evolve 28FDS technology to a differentiated low-power single platform by implementing RF and embedded Non-Volatile Memory (eNVM) solution for our customers’ success.”NXP’s processor design enables robust low power graphics for the IoT and wearable markets through two graphic processor units (GPU) from Vivante: the GC7000 NanoUltra 3D GPU with a low power single shader, and the GC320 Composition Processing Core (CPC) for 2D graphics. The 3D GPU plays a critical role in enabling rich 3D based user interfaces, while the CPC can accelerate both rich 3D and simpler 2D user interfaces. Processors based on the combination of the two GPUs enable efficient display systems which offload and significantly reduce system resources, in turn providing rich user interfaces at low power levels to extend the battery life of devices.“Our 3D GPU is a result of a joint collaboration between Vivante and NXP to deliver industry-leading 3D capabilities with the lowest power consumption,” said Wei-Jin Dai CEO at Vivante Corporation and Chief Strategy Officer and GM of the IP Division at Verisilicon. “The power savings from using the right GPU in an ultra low power processor is one of the major attributes and advantages of the architecture.”So, now shall we dig in a little deeper into the “why FD-SOI” question? Read on in Part 2 of this article.-- By Adele Hars, ASN Editor-in-Chief

GlobalFoundries has announced availability of its 45nm RF-SOI technology (read the press release here). Dubbed 45RFSOI, the company says it’s the first 300mm RF solution for next-gen mmWave beamforming applications in future 5G base stations and smart phones. The technology supports mmWave spectrum operation from 24GHz to 100GHz band, 5x more than 4G operating frequencies. Skyworks’ CTO Peter Gammel says that the 45RFSOI process, “…is enabling Skyworks to create RF solutions that will revolutionize emerging 5G markets and further advance the deployment of highly integrated RF front-ends for evolving mmWave applications.” The news was quickly picked up by publications across the industry, with EETimes noting that RFSOI has been a big GF success story. Production will be at the company’s East Fishkill fab. The PDKs are available now. The 45RFSOI news follows hard on the heels of GF’s announcement a few days prior that the company is teaming up to build a fab offering 22nm FD-SOI in western China, that it’s expanding its Dresden FD-SOI capability by 40 percent, and that it’s adding new RF-SOI capabilities to its fab in Singapore. GlobalFoundries is a member of the SOI Industry Consortium.

With back bias,12nm FD-SOI beats 10nm FinFET on performance. This excellent news comes in by way of Peter Clarke of EETimes Europe (read the whole article here). Rutger Wijburg, GM of GloFo’s Dresden fab told him, "If you look at performance with back-bias 22FDX is the same or better than 16/14nm FinFET process. With 12FDX with back bias you get better than 10nm FinFET processes."