Technology and Trends

SEMI spoke with Udo Gómez, senior vice president at Robert Bosch GmbH, about MEMS technology requirements relative to standard IC design and manufacturing. Gómez highlighted solutions to challenges of MEMS technology development and manufacturing ahead of his presentation at the 22nd Fab Management Forum at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here.SEMI: Regarding standard processes for MEMS, the situation used to be known as the MEMS law: "one product, one process." Today, the variety of MEMS sensors and their application requirements have drastically increased. What is the status of process standardization today?Gómez: Today, standardization in MEMS is certainly not as advanced as it is for conventional semiconductor processes and model environments. However, MEMS technology has developed very much in recent years. The understanding of the numerous interactions between mechanical, chemical and electrical parameters has grown enormously. Improved process tolerances and optimized simulation tools already allow the design of standard components and their manufacture using largely standardized processes and systems.This also enables standardized MEMS process platforms in foundries for fabless suppliers, since adapting process parameters to standard designs no longer means maximum effort. But the situation changes significantly if you want to implement more powerful MEMS components for demanding applications. In this case, much effort is still required in technology development to bring new and innovative designs to mass production readiness.SEMI: How does this situation interfere with the need for a fast, market-driven product development and production ramp-up?Gómez: The constant advancement of (MEMS) technology to new limits requires enormous efforts and time. Thus, fast product cycles in consumer electronics (CE) pose particular challenges. Close interaction between product and technology development is a key success factor here, as well as a deep understanding of the cause-effect relationships. This is the only way to identify and minimize process risks at an early stage.However, the steep product ramp-ups usually required in CE also offer advantages, since learning curves are run through at much shorter time-intervals than, for example, the comparatively slow ramp-ups in the automotive industry. In this way, automotive products benefit directly from the results of CE components. Conversely, CE products benefit from the higher requirements in the automotive sector, whose technologies can be developed and tested on longer time scales.SEMI: What are the critical and different design and manufacturing requirements for MEMS products versus standard IC products, which typically run in highly standardized processes?Gómez: A very special feature of MEMS devices is their multi-physics character – mechanical, electrical, magnetic, fluidic, and even chemical and/or optical effects may play a role. This is very different from standard semiconductors. Depending on the type of sensor or actuator, dedicated and often quite sophisticated models need to be developed to ensure proper function of the device – and not least to ensure full functionality after misuse. For example, shocks or drop events are usually not relevant for standard ICs but they may be extremely relevant for MEMS devices with their fragile mechanical structures.Similarly, the influence of packaging effects like bending or thermomechanical stress may be much more significant in MEMS devices than for standard semiconductors. And last but not least, a physical/magnetic/chemical/optical … stimulus usually needs to be applied when testing MEMS devices. All of this adds complexity to the manufacturing flow and requires dedicated know-how both during the engineering stage and in mass production.SEMI: BOSCH is working to extend the process platform to include complex 3D structures. What are the advantages and benefits of using 3D structures compared to standard 2D structures? Are there 3D structured products already in mass production?Gómez: We have recently extended our well-established surface micromachining process for MEMS inertial sensors (which basically uses one functional silicon layer for the movable MEMS device) to an advanced process using a second functional micromechanical layer. This opens up a large variety of design options and allows the realization of entirely new sensor topologies. For example, our most recent z-axis accelerometers for automotive and CE applications have 3D-like structures for the movable mass.This has several advantages: Firstly, the sensors can be further miniaturized as they now have fixed electrodes for capacitive readout above and below the movable mass, i.e. a larger capacitance per area. Secondly, due to their improved symmetry, these sensors have greatly improved immunity against several parasitic effects, e.g. mechanical stress from soldering or bending on a PCB. Overall, this technology enables us to offer better performance at still very competitive product size and cost. Both automotive and CE sensors are in high volume production for different applications and customers. SEMI: What do you expect from SEMICON Europa 2018 and why do you recommend attending the Fab Management Forum?Gómez: After our very positive impressions of SEMICON Europa 2017, we are convinced that SEMICON 2018 will again meet with widespread interest within the semiconductor industry. SEMICON is an excellent opportunity for us to meet our customers and partners. The Fab Management Forum, which ideally takes place parallel to SEMICON, is a highly valuable addition for us to exchange ideas with leading industry partners and to gain new insights into current trends and technical progress. Within that context, the Forum will make a valuable contribution toward strengthening the European position in semiconductor and MEMS manufacturing. As senior vice president of Robert Bosch GmbH, Dr. Gómez heads Sensor Engineering at Bosch Automotive Electronics (AE/NE-SE) in Reutlingen, Germany, the world’s largest MEMS supplier serving the Automotive, Consumer Electronics and IoT industry. Dr. Gómez started his career at Robert Bosch GmbH in 1999 at Corporate Sector Research and Advanced Engineering (MEMS technology) after completing his doctorate in physics. Before joining Bosch Automotive Electronics in April 2018, he worked in various management positions at Bosch and also held the position of Chief Expert for MEMS sensor technology. From 2013 to March 2018, he was Chief Technical Officer of Bosch Sensortec GmbH - a fully-owned subsidiary of Robert Bosch GmbH, responsible for research and development of micro-electro-mechanical sensors (MEMS) for consumer electronics, smartphones, security systems, industrial technology and logistics.Dr. Gómez has served as Deputy Chairman of the Board of VDE/VDI-Society Microelectronics, Microsystems and Precision Engineering (GMM) since 2014 has been a member of the GSA (Global Semiconductor Alliance) EMEA Leadership Council since 2015.Serena Brischetto is a marketing and communications manager at SEMI Europe.

SEMI met with Heinz Martin Esser, managing director at Fabmatics GmbH, to discuss how existing 200mm semiconductor fabs can master the challenges of a 24x7 production under highest cost and quality pressure by implementing intralogistics automation solutions. The two spoke ahead to his presentation at the Fab Management Forum at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Looking at the latest production capacity data for 2018 – it is a 200mm fab boom. Growing demand for analog, MEMS and RF chips continues to cause acute shortages for both 200mm fab capacity and equipment. Do you think this trend will continue the next years or is it only a short term run on 200mm fabs?Esser: We at Fabmatics believe in a long-term trend. The emergence of the Internet of Things and growing digitalization in all areas of life will continue to increase demand for integrated circuits (ASICs), analog ICs, high-performance components and micro-mechanical sensors (MEMS) in the coming years. Many of these semiconductor elements should be produced in 200 mm fabs.SEMI: How does Fab automation contribute to increase capacity of existing, mature 200mm fabs?Esser: We are convinced that fab automation is one of the greatest potentials for older 200mm factories to effectively master increased demand, increasing efficiency, quality assurance and flexibility at the same time. In particular, material flow automation, which is often the missing link between existing equipment in different production areas, can help increase productivity in an elementary way.If you analyze how long valuable tools typically wait for loading and unloading, you can see a direct effect of the intralogistics automation system, which leads to a significantly higher utilization of process equipment by making the material flow independent from human performance. Additional side effects such as reduced cycle time, stable fab flow factor or flattened WIP shafts further increase the contribution of material flow automation to get the most out of existing mature factories. Older does not mean obsolete.SEMI: What are the biggest challenges for a successful implementation?Esser: There is no single challenge when you automate an existing mature fab. Instead, you face a whole variety of challenges you have to tackle, ranging from historically grown non-aligned fab layouts over non-linear material flows and older non-standardized equipment to “automation unfriendly” fab environment. Also you should not underestimate the efforts to overcome the practice manual fab operation people in the cleanroom are so familiar with for many years. Before doing automation you have to think automation, i.e. you have to question all processes to make them ready for automation.SEMI: What are the key drivers to automate a mature fab today: costs, process stability, quality or a combination of them?Esser: This question should be better asked to our customers, but we believe it is a mix of many impacts. Most likely everybody sees the cost reduction at first, but we get more aware of process and performance stability as well as quality requirements – and here our customers’ play the most important role – become more and more focused.SEMI: What do you expect from SEMICON Europa 2018 and why do you recommend attending the Fab Management Forum?Esser: This year SEMICON Europa will co-locate with electronica. So it`s going to be the greatest trade fair for electronics manufacturing in Europe. We will meet innovators and decision-makers across the whole electronics supply chain. The Fab Management Forum addresses a highly topical question that concerns all semiconductor manufacturers not only in Europe - how to handle complexity and enable the necessary flexibility to cope with customers' needs. High-ranking speakers will give an insight into the latest technologies and best practices. I am looking forward to the lively exchange with the participants and taking away new impulses for our business. Heinz Martin Esser is managing director at Fabmatics GmbH, responsible for sales and marketing, customer service and administration. He studied supply engineering at the University of Applied Sciences in Cologne and later earned a university degree in business administration. Serena Brischetto is a marketing and communications manager at SEMI Europe.

SEMI spoke with Balaji Nandhivaram Muthuraman, Package and Material Simulation engineer at Dialog Semiconductor, about the state of reliability testing for wafer-level chip scale packages ahead of his presentation at the Advanced Packaging Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Since the beginning of package development reliability testing has played a key role in Wafer Level Chips Scale package (WLCSP) investigation. Lately, the role of simulation and predictive reliability significantly contributed in reducing package development time. To what extend can we predict potential failures for WLCSP packages in an early design phase by simulation?Muthuraman: Reliability testing is essential and crucial for the electronic packages. It is during the package development phase that several design iterations need to be considered and, in some cases, many feasibility studies for the package are executed. This means we require significant reliability test measurements, which could influence product-development time. For example, Temperature Cycling on Board (TCoB) reliability testing would take approximately 65-75 days for testing the package reliability subjected to 1500 temperature cycles. Each cycle involves exposing the device at hot and cold temperatures with a specified temperature profile. Executing such Board Level Reliability (BLR) tests for all feasible package designs is a tedious process that could lead to an increase in package development time. This is the stage where numerical simulation methodology helps us to foresee potential failures in Board Level Reliability. Predicting delamination or cracking of passivation/metal interface layers based on the WLCSP design layout and estimating the characteristic life of smart device subjected to temperature load are some classic examples of predicting WLCSP package behavior in an early design phase by simulation methodology.SEMI: We can definitely say that predictions occurring during the early stage are key to success. But how exactly can numerical simulation help estimating?Muthuraman: From a thermal reliability point of view, determination of the optimum material combination – bill of materials for device – is used to predict whether a heat sink is required for the device to meet thermal performance. This is not all. At an early design stage, the simulation methodology can be used to estimate device performance under varying thermomechanical loads. Numerical simulation at early package development phase helps the researchers by predicting the possible temperature contour field and stress contour field of the smart device under a given loading condition. The estimation accuracy of potential issues through numerical simulation depends on the material models implemented and consideration of realistic load condition under which the package operate in real life situation. For example, engineering judgements can be made using numerical simulation of Solder Joint Reliability (SJR) analysis to decide whether an Underfill material is required between the Package and the Printed Circuit Board (PCB).SEMI: Are all conditions tested during the reliability investigations specific to fit a certain type of applications or do these vary?Muthuraman: Reliability investigations are based on the end application of the electronic devices. For example, handheld device applications will be exposed to a reliability condition up to a maximum of +85oC, whereas smart devices designed for an automotive application would be tested with a typical temperature of +125 oC or up to +150 oC. In some cases, the testing conditions are customized based on specific customer requirements. Moreover, reliability conditions can also be customized to study some specific failure mechanism. SEMI: Can you describe for which one?Muthuraman: Thermal cycling profile is based on device application and/or specific requirement from our customer. For example, handheld devices use a typical temperature range of +85°C to -40°C with 20°C/min ramp time and 20 minutes of dwell time. There is possibility of adjusting the ramp and dwell time of the Temperature Cycling qualification test, provided such accelerated test does not lead to other failure modes.SEMI: What failure mechanism was the subject of the study in this specific case?Muthuraman: Electronic package reliability behavior without and with underfilled devices is explained in this study with the help of temperature cycling on board (TCoB) measurements and validated with numerical simulation. In the paper to be presented at SEMICON Europa, failure occurring at the interface of the solder and Under-Bump Metallization (UBM) structure is discussed. Behavior of such failure mechanism is illustrated with different WLCSP package sizes subjected to varying thermal load condition. One of the key aspects of the subject is the board-level reliability (BLR) measurement and simulation validation showing how the failure mode could be shifted from solder joint to the metal interface layers between UBM and interconnection to Silicon Chip, depending on the WLCSP design layout. The reasons for such shifts in Failure phenomenon are explained and necessary design optimization is suggested for improvement. Another key aspect of this study is determination of Fatigue Life Model for WLCSP family using the SACQ solder. SEMI: Are you currently working and experimenting on something particularly exciting?Muthuraman: Recently, we concluded our engineering analysis of thermomechanical reliability of Large Wafer Level Chip Scale packages. In September 2018, I presented this research work in an International Conference held in Dresden, Germany. Dialog Semiconductor GmbH was awarded the “Best Paper Presentation for the year 2018” for this work. This success is attributed to the entire team of Package and Material simulation experts at Dialog Semiconductor GmbH lead by Mr. Baltazar Canete and IC Package-Design Simulation group managed by Mr. Rajesh Aiyandra. We have started our investigation on the influence of Board Level Reliability of WLCSPs due to varying metal concentration of inter-metallic layer. We, at Dialog, are also working on possibility of thinner WLCSP. All these activities would include extensive Temperature Cycling on Board (TCoB) measurements, Statistical Analysis of measurement Data and would then be validated by Numerical Simulation. SEMI: What are your expectations for the future and why would you recommend attending SEMICON Europa Advance Packaging Conference?Muthuraman: SEMICON Europa is an important platform for Dialog Semiconductor GmbH to showcase the latest developments in the semiconductor industry. It is an opportunity to meet other industry experts, partners, and customers, and exchange various innovative ideas and to get new insights. Many semiconductor companies are based around the Munich area as well world-class universities. We are particularly interested in innovation, workforce and talent development themes. SEMICON Europa gives us a platform for greater interaction with the academicians and research scientists. This way, we bridge the gap between industry and University researches, thereby moving forward in innovative technologies. We, as Dialog Semiconductor GmbH, have also a development center near Munich (Germering). Our expectations for the future are very positive and vibrant. We are always ready to take up the industry challenges and demands and provide the best-in-class solutions to our product users. Dialog Semiconductor GmbH is certainly poised for higher growth in coming years. Balaji Nandhivaram Muthuraman BioBalaji Nandhivaram Muthuraman is a Packaging and Material Simulation engineer at Dialog Semiconductor GmbH, Germany. He has authored/co-authored conference publications including in the area of molecular dynamics simulation on assembly of carbon nanostructures; Analysis of thermoset material used in smart devices and reliability of wafer level packages. Recently, he has been awarded with the “Best Paper Presentation for year 2018” in the area of Board Level Reliability of Wafer Level Chip Scale Packages, in a recently held international semiconductor conference. His current areas of working interest include reliability investigation of electronic packages and developing fatigue models for reliability assessment of Dialogs products. He obtained his Bachelor’s degree in Aeronautical Engineering from Anna University, India and Master’s degree in Computational Mechanics of Materials and Structures from University of Stuttgart, Germany. Serena Brischetto is a marketing and communications manager at SEMI Europe.

SEMI met with Gerald Beyer, program manager at imec, to discuss the co-existence of various 3D interconnect technologies and their need for new materials and integration solutions. The two talked in the runup to his presentation at the Advanced Packaging Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Can you confirm this trend towards heterogeneous integration and do you think it will be a long-term development trend?Beyer: We consider heterogeneous integration as a scaling booster for functional partitioning and as a fashion method to create systems, which would not be possible or economical on such as a single chip. As you can apply it to numerous systems, we expect it to stay for the long term.SEMI: What are the new critical challenges for the combination of different technologies into one package?Beyer: When you create a complex system, there is usually more than just one challenge. On one side, you need to be able to design such a system. If you disintegrate a large chip, you need to decide how to reconstruct it, i.e. which function goes into which strata. You would like to do that not manually but with a set of tools supporting the designer. Only recently EDA (Electronic Design Automation) and design houses have started to support this idea.On the technology side, interconnections between some strata of such a reconstructed chip will require small pitch interconnects of the order of 1µm pitch and less. Today, wafer-to-wafer bonding technologies have sufficient overlay margins for 1µm pitch. Wafer-to-wafer bonding technologies, however, have a number of constraints such as equal die size and the necessity to realize chip stacking rather in a fab environment than in a traditional packaging house. Die-to-wafer assembly technologies still need to bridge the gap to deep sub 10µm pitch in terms of alignment and cleanliness.SEMI: What kind of new materials or integration solutions do you expect to be developed? Are you working on it already?Beyer: As explained above, die partitioning requires sub 1µm pitch interconnects. We are investigating fine pitch wafer-to-wafer and die-to-wafer (direct) bonding. For the latter, not only new alignment capabilities but also die cleaning and thin die handling technologies need to be developed. To build a complete system with data processing, memories etc., novel integration schemes such as Flip Chip – Fan Out Wafer Level Packaging with high density 2D and 3D interconnect capabilities are being investigated. These new systems differentiate from current ones by high density Through Package Vias (TPV), Si bridges and sub 2µm line/spacing RDL. The new integration approaches push the materials such Temporary Bond Materials (TBM), Wafer Level UnderFill’s (WLUF), photo patternable polymers for fine Line/Spacings to name a few, to the limits. Hence, development of new materials is a key aspect.SEMI: What trends and developments do you expect in the near future and why would you recommend attending the Advanced Packaging Conference?Beyer: The development and commercialization of products using heterogeneous integration is a big effort drawing on resources from EDA vendors, materials and packaging tool suppliers, OSATs, foundries, memory suppliers and IEDMs and academia alike. The agenda of the Advanced Packaging Conference at SEMICON Europa reflects this diversity and I am looking forward to interesting discussions with all participants. Gerald Beyer has been working in the field of 3D Technologies since 2012 as the technology program manager of the 3D System Integration Program of imec. Prior to this role, he was the interconnect program manager and group leader of BEOL integration. He received a PhD in materials science from Imperial College, London and a MSc from Thames Polytechnic, London.Serena Brischetto is a marketing and communications manager at SEMI Europe.

Korea is on track to top all other regions in fab investment, spending $63 billion between 2017 and 2020, with powerhouses Samsung Electronics Co. and SK Hynix leading the way, according to latest World Fab Forecast Report by SEMI. Samsung Electronics increased fab investments $770 million to $12 billion this year, and SK Hynix upped its spending a significant $2.8 billion to $7.25 billion in 2018.Korea's investment companies anticipate continued growth for both companies in the second half of 2018.Under this halo of extraordinary investment, nearly 380 SEMI Korea members and industry analysts gathered for 2018 SEMI Korea Members Day on September 13 to share insights on semiconductor market trends and new technologies that could help members bolster their competitiveness. Following are key takeaways from the event. Korea semiconductor market to grow 16% in 2018That’s according to IDC Korea VP Kim Soo-kyung, who noted that data center, memory and Internet of Things (IoT) are becoming key growth drivers for the semiconductor industry. He encouraged semiconductor companies to closely track development of automotive technology and the industry semiconductor market, both key growth areas. SEMI Korea president H.D. Cho opens SEMI Korea Members Day 2018 Continuing fab investment will lead to oversupply, but display will shineMarket entry by Chinese companies will also spur the oversupply, said Jeong Won-Seok, an analyst at HI Investment Corp. He noted that the oversupply will force Korea into stiffer competition with other regions. However, with OLED used for a wide variety of devices and the display industry seeing rapid growth, the sector will remain ripe for growth among Korean companies.Interconnecting various applications is a big semiconductor industry trendThe need for these interconnections will stand out in the mobility and high-performance computing (HPC) markets, said Park Sung-Soon, principal research fellow at Amkor Technology Korea, who addressed trends in packaging technology. He also emphasized interconnection cost efficiency as key to maximizing competitiveness.Smart Manufacturing is driving mass customizationAs semiconductor industry growth continues, production methods are shifting from ‘mass production’ to ‘mass customization,’ increasing the importance of Smart Manufacturing in driving greater production efficiency, noted BISTel VP Jeon Kyeong-Sik. Building a Smart Manufacturing platform to support large-scale production of specialized database and artificial intelligence (AI) chips will boost production efficiency, reduce costs and improve risk management. Virtual simulation will be a key enabling technology. SEMI analyst Clark Tseng presenting at SEMI Korea Members Day 2018 Surge in data volume and technology advances to drive long-term semiconductor industry growthThese key industry drivers will continue to power fab investment growth, with spending focused on 3D NAND, DRAM, and foundry, said Clark Tseng, director of Industry Research and Statistics at SEMI. China alone will see eye-watering growth with the region’s investments in domestic companies surging 46% from 2018 to 2019 and fab investment by Chinese domestic companies outpacing spending by foreign companies in China, Tseng predicted. SEMI membership rises with industry growthCulminating the event, SEMI Korea president H.D. Cho said, "With the growth of the semiconductor market, the number of SEMI members is gradually increasing, and we will help member companies grow with various activities such as Korea Members Day.”Jaegwan Shim is a marketing specialist at SEMI Korea.

[caption id="attachment_12359" align="alignright" width="300"] (Courtesy: PRNewsfoto/QuickLogic Corporation)[/caption] Some great pieces of FD-SOI news from QuickLogic. The company recently demonstrated its ultra-low power ArcticPro™ embedded FPGA (eFPGA) solutions at the GlobalFoundries Technology Conferences in Santa Clara, California, Munich and Shanghai. The technology is available now. ArcticPro is the industry's first eFPGA offering for GF's 22FDX® process (btw they've been shipping it in volume for GF's 65nm and 40nm bulk processes for years). The company says its ultra-low power eFPGA architecture and mature software offer semiconductor and system companies the ability to integrate programmable hardware accelerators to lower power consumption and the flexibility to reconfigure a device's functionality in the field. [caption id="attachment_12360" align="alignleft" width="300"] (Image courtesy: QuickLogic)[/caption] QuickLogic has also announced that the technical university ETH Zurich will integrate QuickLogic's ArcticPro technology onto the university's PULP platform. PULP is a silicon-proven open-source parallel platform for ultra-low power computing created with the objective of delivering high compute bandwidth combined with high-energy efficiency. ETH will become the first licensee of eFPGA technology from QuickLogic on GF's 22FDX process node. They will develop an SoC integrating ETHZ's open-source RISC-V cores and eFPGA technology, enabling users to offload critical functions from the processor(s) and implement them in eFPGA fabric. This approach creates multiple hardware co-processors that increase system efficiency and performance while decreasing power consumption. "The main goal of the PULP program is to use a multi-disciplinary approach to achieve extremely high-power efficiency for computing applications," said QuickLogic CTO Dr. Timothy Saxe. "QuickLogic has a tremendous depth of experience in achieving low power consumption across a broad range of applications, including AI and IoT at the edge and security, and we look forward to contributing what we've learned along with our eFPGA technology to this groundbreaking initiative in low power computing." ETH's PULP platform with the fully integrated eFPGA is expected to be available Q1' 2019. QuickLogic is part of GF's fast-growing FDXcelerator™ partner ecosystem, offering customers ultra-low power (eFPGA) Intellectual Property, complete software tools and a compiler.

Excellent news and exciting applications made headlines at the recent FD-SOI and RF-SOI events in Shanghai. During the FD-SOI day, Amazon/Blink and Intellifusion shared news about their new chips, and we got updates from GF and Samsung. The RF-SOI day featured a great talk with details about China Mobile's 5G plans, and peeks at Nokia's groundbreaking approach and Qorvo's outlook. [caption id="attachment_12354" align="alignright" width="300"] (Photo courtesy: Verisilicon)[/caption] The hall was absolutely full – with over 300 people attending each day. The FD-SOI event was by invitation only, and there were far more people wanting to attend than there was room for, even given the big room in which the events were held. The events got excellent coverage in the China tech press. For example, EEWorld started with an overview article and added five supporting pieces zooming in on key presentations and companies: one on GlobalFoundries, one on Samsung, one on Verisilicon, and two on Soitec (CEO and top exec interviews). These pieces are in Chinese, but just open the links through your favorite translation site. Many of the key slides are captured in these articles, so if you can't wait for the ppts to be posted on the SOI Consortium website, you can get some quick previews now. The Verisilicon PR folks also wrote up highlights of the FD-SOI event in real time with lots of great pictures – you can read that here. Many thanks to that team, too, for flagging the coverage in the China press and posting it on their WeChat account. On the RF-SOI side, the Simgui folks wrote that up – you can read it here. They also sponsored a gala dinner with awards given to Qorvo and SmarterMicro – you can read about that here. Most of the presentations will be posted on the SOI Consortium website over the next few weeks, at which point we'll cover them in-depth here at ASN. But for now, here's a quick round-up of some of the highlights. FD-SOI Highlights [caption id="attachment_12347" align="alignright" width="300"] (Courtesy: Blink, Verisilicon)[/caption] Boston-area based Blink, which makes very popular home security systems, was recently bought by Amazon (see their current product page here). They just taped out a new chip on Samsung's 28FDS FD-SOI technology, and they're really happy about it. “I believe for battery powered devices at home, FD-SOI is the way to go,” said Yantoa Jia, Head of ASIC China Ops at Blink. Their goal in the move from 55nm bulk to 28nm FD-SOI was to double battery life, add features and control costs: and they did it. Even adding two more CPU cores and lots more features, “The power drop is fantastic,” he said. Design was no problem, he continued, and there was plenty of IP. Once the new generation is officially announced, he promised to sit down with ASN and give us more details. Attendees also heard about a new chipset from Intellifusion, which is putting its face recognition technology onto GlobalFoundries' 22FDX FD-SOI with design house Verisilicon. CEO Nin Chen gave an impromptu talk about how their technology is used to find missing people and property. The new chip, which is especially designed for use in cities, is network-to-cloud leveraging AI. For his part Thomas Morgenstern, GlobalFoundries SVP and GM of the Dresden Fab 1, said they're seeing high yields and increasing capacity for 22FDX. The marketing and manufacturing ecosystem has been built around the fab in Europe. Now, he said, the key is to build an FD-SOI ecosystem in China. The market needs of China largely parallel those of Europe, he noted, for performance and efficiency at the right cost point. The ecosystem enables fast time-to-market and 1st-time-right. [caption id="attachment_12343" align="alignleft" width="300"] (Photo courtesy: Cadence)[/caption] Samsung SVP Gitae Jeong sees their FD-SOI technology as the right solution for the 4th Revolution, which includes everything from energy harvesting to self-driving cars. They've just taped out their first 5G mmWave cellular chip on 28FDS, he revealed. eMRAM is looking very good, only requiring three additional masks and getting stable yields from -40o to 105oC. 18FDS is on schedule, with PDK 0.5 now being released, and 1.0 on track for release in March 2019. They expect a very fast ramp, and are looking at a 35% area reduction, power cut in half and performance up 22% compared to 28FDS. RF-SOI Highlights [caption id="attachment_12350" align="alignright" width="300"] China Mobile, Project Manager Danni Song (Photo courtesy: Simgui)[/caption] When China Mobile talks, the world listens. Project Manager Danni Song presented again this year (she gave a great talk last year, too). China has a very ambitious 5G project underway, and under two years in which to roll it out. The biggest challenges are power consumption and cost (a problem made worse by the additional power amplifiers needed for MIMO). Can RF-SOI help solve these challenges, she asked? One thing she did clarify during the panel discussion was with respect to the mmWave part of the 5G puzzle. Their initial 2020 rollout will only focus on sub-6GHz, with mmWave following a year or two later. Michael Reiha, Head of RFIC R D at Nokia Mobile Networks clarified the worldwide 5G rollout during the panel discussion. Different locations on the planet have different histories and needs, so will rollout 5G in different ways. For historical reasons (and a lack of choice), the US will lead with mmWave, he said. Europe, meanwhile, will focus on 24GHz to meet the needs of automotive radar. In his presentation, Reiha described Nokia's approach to power amplifiers (PA), which is very different from what others are doing. With RF-SOI, he said, you can add sensors and logic for a level of preventative care, so you can gauge and protect your equipment using AI. He believes this disruptive approach will put them two years ahead of the industry, enabling massive MIMO to be deployed in dense urban areas with 60% lower power consumption and 50% savings in material costs. Go read about their Reefshark tech, he urged, which he says will beat GaAs. “The future is very bright with RF-SOI,” he concluded. “I can state that with confidence.” [caption id="attachment_12351" align="alignleft" width="300"] Julio Costa, Director of Technology Development, Qorvo (Photo courtesy: Simgui)[/caption] Julio Costa, Director of Technology Development at Qorvo sees it differently. Traditionally a GaAs house, all their RF-SOI work is fabless. While RF front end modules (FEMs) are loaded with RF-SOI, he said, and are a big winner for antenna tuning, Qorvo still sees GaAs for high-efficiency amplifiers and envelope tracking. But, he said, it will be a battle. GaAs wins in terms of area and power consumption he contends, but adds that SOI wins in terms of cost. Power levels, he predicts, will be the determining factor. So that's the quick overview – we'll drill down into the presentations as they're posted, so stay tuned!

With one of the oldest and largest public education systems in the developed world, how well does the US public education system serve the global electronics industry? Public education in the US has had time on its side. In 1635 the Boston Latin School became the first public school in the US. Boston Latin was originally a boys-only secondary school that taught Greek, Latin and the humanities. It wasn’t until 1918, however, that the US government required all children to obtain at least an elementary-school education – available to them through free public schools. As public education increasingly served the masses rather than just the elite, a balance of humanities, mathematics and science began to replace the classics.While free public education in the US got a comparatively early start, most American students score lower in science and math than students in many other developed nations. According to a 2017 Pew Research Study, 15-year-old American students ranked 24th in the world in international standardized age-group science testing and 38th in the world in standardized mathematics testing. While test scores are just one measure of proficiency, do they in some way reflect a lack of motivation to study science and math because of students’ unfamiliarity with STEM careers? Source: Pew Research. See article. Make STEM RelevantIf we want the US to remain a leader in the global electronics industry, we need to pay attention to the disconnects between academics and workforce development. We must help show students at an early age that STEM careers can be exciting, creative and fulfilling, and that math and science are essential to STEM.Ways to Get InvolvedWhether you work for a large publicly traded electronics manufacturer, an equipment or materials supplier, a foundry or a startup, you can take action to support student engagement in STEM. Here are a few ways to get involved:Participate in Community Programs One fun way to inspire budding technologists is to sponsor one of the FIRST programs for students. These age-segmented competitive programs range from FIRST LEGO League, Jr. Challenge for six-ten year-olds to FIRST Robotics Challenges for high school and college students, giving you the opportunity to sponsor a team or even to coach.Our company sponsors Team TNT, a Southern Oregon-based team that placed among the world’s top high school robotics teams at the spring 2018 world championships. We also brought two members of Team TNT to SEMICON West 2018, where they attended SEMI’s three-day High Tech U and presented their insights on building their FIRST Challenge robot at the Smart Workforce Pavilion. Margaux Quady (L) and Matthew Mills (R), Team TNT members, presented at SEMI’s Smart Workforce Pavilion at SEMICON West (Rogue Valley Microdevices) Concerned about the dearth of girls interested in STEM — and the small numbers of women in engineering careers? Look for your local equivalent of the Advocates for Women in Science, Engineering, and Math (AWSEM) Symposium, a day-long program for middle school girls. One of our engineers, Jennifer Devin, gave a hands-on workshop on deconstructing smartphones to showcase the silicon chips inside them. If you cannot find something like AWSEM, check out national programs such as the Society for Women Engineers (SWE)’s SWENext program for girls ages 13-18 as well as Girl Powered.Partner with Local SchoolsYou would be surprised at the opportunities to present what you do in the classrooms of school-age children. Take after Allyson Hartzell, managing engineer at Veryst Engineering in Needham, MA. Allyson speaks with students in her local elementary schools of Somerville and Cambridge, Massachusetts because she thinks that we must reach younger children to get them excited about STEM learning. “Waiting until middle school or high school to help students visualize the real-world appeal of STEM careers is just too late,” said Hartzell. “I’ve had amazing experiences working with local elementary-school students. Students become engaged when you show them real-world examples such as electron micrographs of MEMS.”Many middle schools and high schools also look to their communities to provide tutors in STEM subjects. Check with the community liaison at your local school to get started.Engage in Internship ProgramsInvolvement doesn’t stop in the K-12 grades. Seek out a local university’s internship program and hire some interns in that program to work at your company. The interns will gain valuable applied experience in your environment, and you might find young engineers who would love to join your company after they graduate. Oregon’s MECOP, an engineering-specific internship program founded on close industry-university collaboration, has been amazing for our recruitment. Some of our finest engineers were once in the MECOP program, including our engineering manager.Anything you do to get involved in inspiring coming generations of students to explore STEM — no matter how small your action — will make a positive difference in helping US students become better prepared to enter a technology-focused workforce. Through collaboration and creativity, we can help US companies keep the global electronics industry moving toward greater innovation. Jessica Gomez, CEO and co-founder of Rogue Valley Microdevices, entered the semiconductor manufacturing field in 1998 at Standard Microsystems Corporation of Hauppauge, New York where she acquired valuable knowledge in both semiconductor processing and production management. Jessica also held positions at Integrated Micromachines and Xponent Photonics prior to co-founding Rogue Valley Microdevices in 2003. As head of a technology company, Jessica recognizes the criticality of workforce development – and has become an advocate of STEM education. Rogue Valley Microdevices supports STEM initiatives for middle-school girls, a competitive robotics team for high school students, and a college internship program specifically for engineers.Expanding her energies beyond the company she co-founded, Jessica is also applying her passion for change to politics. She is currently campaigning for the Oregon State Senate.For more information, visit Rogue Valley Microdevices.

Over the last three years the number of battery-operated electronic-component solutions for the Internet of Things (IoT) and Industrial IoT (IIoT) applications has been increasing steadily. This trend will continue for years to come, particularly with the growing popularity of mobile devices of all flavors. Addressing power consumption for battery-powered always-on IoT/IIoT devices – which rely on dozens of electronic components, including sensors — is critical to their commercial success.The demand for ultra-low-power sensors has accelerated the race to squeeze every last mW from components. Compared to previous-generations of sensors, semiconductor suppliers have managed to drastically reduce power by as much as 50%-60% over older solutions. Leveraging new state-of-the-art analog design techniques, we have effectively optimized capacitive readings of MEMS structures. How effective are they? We estimate that with the right mix of our company’s power-saving technologies, it is possible our customers could save 3MW/year globally[1].What’s next?While the semiconductor industry continues to investigate novel technologies, approaches and analog IP for greater energy efficiency, we believe that bigger gains in reducing power consumption will come from thinking at the system level. The sensor node is a good place to start.A typical IoT node is composed of a set of sensors, a microcontroller, a radio frequency (RF) link, and a power-supply system, often based on Li-Po batteries.Of these, the microcontroller and RF link consume the most energy and, in the RF link, power consumption is a function of the distance between end point and receiver and of the amount of data transmitted. Thus, at longer distances reducing the amount of data transmitted can save power. We can achieve this by including some pre-elaboration capabilities on-board and by extracting more meaningful information from the raw sensor data.We address this by moving some computation and data analysis inside the sensors, where smart hardware “digital blocks” perform faster and more efficiently than software-based routines running in the microcontroller. We can achieve this by using dedicated hardware resources to reduce overall system power consumption. The beauty of this solution is that it allows the microcontroller to operate in low-power states by only transmitting significant information in batches. The SensorTile development kit can speed up prototyping of ultra-low-power IoT devices by integrating an ultra-low-power MCU and BlueNRG Bluetooth radio with sensors. Some examples of these advanced digital blocks are the Advanced Embedded Pedometer, the Finite State Machine and Decision Tree, and Compressed FIFO in an IMU.The Advanced Embedded Pedometer is a hard-wired step counter that works independently inside the sensor, without CPU intervention: By comparing sensor outputs to pre-defined and -loaded patterns, it autonomously decides whether the user is walking or running to start and stop counting the user’s steps. The sensor then makes this information available to the microprocessor for further elaboration or for simple notification to the user.The Finite State Machine and Decision Tree are new functions dedicated to pattern recognition (machine learning) and decision-making: They can perform complex classifications and state detection, and can send dedicated warning and signaling to the microprocessor. A good real-world example is industrial predictive maintenance, where the sensor can categorize and identify different malfunctioning states in the equipment before waking the microprocessor to react.Our products, on average, save about 1 mA (1e-3) over competitive devices or over our previous-generation parts. So 2.0 x 1e-3 x 1.5e9 = 3MW. Programmable Sensor and Decision Tree Finite State Machine Integrating programmable sensors and decision trees as well as finite state machines in the sensor allows the sensor to do more of the work while the MCU sleeps. Source: STMicroelectronics Another example is compressed FIFO (first-in, first-out) buffer, which can store sensor data in the sensor, not in raw format, by using efficient compression algorithms. In addition to saving memory (and therefore silicon area) inside the sensor chip, it also saves power by reducing the number of bytes transferred to the processor and by shortening the communication data flow, which reduces processor-active time.These examples – the Advanced Embedded Pedometer, the Finite State Machine and Decision Tree, and compressed FIFO buffer – are just some showing that we can develop low-power IoT/IIoT devices through intelligent management of sensors, microcontrollers and other components in any given system. Your starting point is an IoT/IIoT node that lets you selectively allocate some power-hungry tasks — such as computation and data analysis — to sensors instead of the microcontroller. Leveraging data blocks that reside in the sensors alleviates the microcontroller’s typical power drain, allowing the microcontroller to operate with maximum efficiency.[1] ST sells about 1.5 billion pieces/year (1.5e9), which typically run from a 2V supply. Luca Fontanella joined ST Microsystems in 1995 as an analog designer. In 2001 he joined the MEMS team in a marketing role and today he is marketing manager in the MEMS Sensor Division. Luca has contributed to 25+ international patents and has presented at multiple conferences. He earned a degree in Electronic Engineering from Padua University. Simone Ferri joined STMicroelectronics in 1999 as Central R D engineer, moved to the Audio Division as a digital designer and is now director of the Consumer MEMS Business Unit. He holds a degree in Electronic Engineering and an MBA from the Polytechnic of Milan. _______________________________________________________________________________________________Brush up on the latest MEMS and sensors trends and gain a new perspective on emerging applications. Register today!

Materials innovation has always been vital to the semiconductor industry. In the past, it was high-κ gate dielectrics. Today, Cobalt is seen as a replacement for Tungsten in middle-of-line (MOL) contacts.What materials innovation will the future bring?A likely answer is Graphene, the wonder material discovered in 2004.Graphene is one atomic layer of carbon, the thinnest and strongest material that has ever existed. It is 200 times stronger than steel and the lightest material known to man (1 square meter weighing around 0.77 mg). It is an excellent electrical and thermal conductor at room temperature with an electron mobility of ~ 200,000cm2.V-1.s-1. At one atomic layer, graphene is flexible and transparent. Other notable properties of Graphene are its uniform absorption of light across the visible and near infrared spectrum and its applicability towards spintronics-based devices.Graphene and Moore’s LawMoore’s Law scaling can be broken down into 4 key areas: Lithography FET Advanced Packaging (2.5D and 3D IC) Interconnect Material Solutions for upcoming nodes are starting to emerge in the first two areas (EUV and Nanowire- or Nanosheet-based FET respectively). Graphene play an important role in the latter two areas. For advanced packaging, Graphene can be used as a heat spreader (to lower overall thermal resistance), or as an EM shield (to lower crosstalk) as part of a 3D IC package.Active Graphene device layers can potentially be stacked on top of each other using a low-temperature transfer process ( 400°C) to allow for a dense heterogeneous “memory near compute” configuration. This is an area DARPA is actively researching as part of its new $1.5 billion Electronics Resurgence Initiative.Regarding interconnects, Copper interconnects are running out of steam and becoming a major IC bottleneck (projected 40% total delay for 7 nm node). Graphene’s high electron mobility and thermal conductivity make it an attractive interconnect material for MOL and back-end-of-line (BEOL), especially at line widths 30 nm.Graphene Device ApplicationsGraphene-based semiconductor applications are already starting to hit the market. A fully integrated optical transceiver (with a Graphene modulator and photodetector) operating at 25 Gb/s/channel was on display at the recent Mobile World Congress in Barcelona. San Diego-based Nanomedical Diagnostics is selling a medical device that uses a Graphene biosensor. Europe-based Emberion is building Graphene optoelectronic sensors that might find a home in LIDAR applications, where there is currently a focus on improving sensing in low-light conditions.What will the overall Graphene roadmap in the semiconductor industry look like? The history of ion implantation serves as a good example of how a fundamental scientific discovery moves from the lab to the foundry floor.The dominant view in the semiconductor industry at the time was that ion implantation would not work in practice (vs. thermal diffusion) and that, if it did, it would only marginally improve the manufacturing yields of existing products. There was nothing obvious about the transfer of ion bombardment techniques from nuclear physics research to semiconductor production.Varian (led by British physicist Peter Rose) built a new, advanced ion implant tool that Mostek (DRAM manufacturer based in Texas) was able to use to create MOS ICs with clear competitive advantages. The successful collaboration between Varian and Mostek was the turning point in the development of ion implantation as a major semiconductor manufacturing process. Over the next few years, semiconductor firms used ion implantation in a growing number of process steps and, by the late 1970s, it became one of the main processes used in semiconductor manufacturing.Likewise, the Graphene world needs to work closely with the semiconductor industry to develop the tools and techniques required to solve fundamental issues around Graphene growth (good uniformity over large area, low defect density) and Graphene transfer (high throughput, CMOS compatible). It is only then will we fully realize a future that includes 2D materials.The first step in this process is cross-industry education and initiating the dialogue between semiconductor industry and graphene companies. The National Graphene Association will be hosting the largest gathering of graphene companies and commercial stakeholders at the Global Graphene Expo Conference, October 15-17, 2018, in Austin, Texas.Learn more about graphene at the upcoming Global Graphene Expo Conference with dedicated panels of experts and investors, and roundtable discussions on how Graphene will impact the semiconductor industry. The event promo code is SEMINGA. About the AuthorAnand Chamarthy is the CEO and Co-Founder of Lab 91, an Austin-based startup that is working towards Graphene/CMOS integration at the foundry level. Anand can be reached at [email protected]. About the National Graphene AssociationThe National Graphene Association is the main organization and body in the U.S. promoting and advocating for commercialization of graphene and addressing critical issues such as standards and policy development.